[people/ms/u-boot.git] / board / esd / pmc440 / cmd_pmc440.c

/*
 * (C) Copyright 2007-2008
 * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <command.h>
#include <console.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/processor.h>
#if defined(CONFIG_LOGBUFFER)
#include <logbuff.h>
#endif

#include "pmc440.h"

int is_monarch(void);
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
			   uchar *buffer, unsigned cnt);
int eeprom_write_enable(unsigned dev_addr, int state);

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_CMD_BSP)

static int got_fifoirq;
static int got_hcirq;

int fpga_interrupt(u32 arg)
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
	int rc = -1; /* not for us */
	u32 status = FPGA_IN32(&fpga->status);

	/* check for interrupt from fifo module */
	if (status & STATUS_FIFO_ISF) {
		/* disable this int source */
		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
		rc = 0;
		got_fifoirq = 1; /* trigger backend */
	}

	if (status & STATUS_HOST_ISF) {
		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
		rc = 0;
		got_hcirq = 1;
	}

	return rc;
}

int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;

	got_hcirq = 0;

	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);

	irq_install_handler(IRQ0_FPGA,
			    (interrupt_handler_t *)fpga_interrupt,
			    fpga);

	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);

	while (!got_hcirq) {
		/* Abort if ctrl-c was pressed */
		if (ctrlc()) {
			puts("\nAbort\n");
			break;
		}
	}
	if (got_hcirq)
		printf("Got interrupt!\n");

	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	irq_free_handler(IRQ0_FPGA);
	return 0;
}
U_BOOT_CMD(
	waithci,	1,	1,	do_waithci,
	"Wait for host control interrupt",
	""
);

void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
{
	u32 ctrl;

	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
		printf("%5d  %d    %3d  %08x",
		       (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
		       FPGA_IN32(&fpga->fifo[f].data));
		if (ctrl & FIFO_OVERFLOW) {
			printf(" OVERFLOW\n");
			FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
		} else
			printf("\n");
	}
}

int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
	int i;
	int n = 0;
	u32 ctrl, data, f;
	char str[] = "\\|/-";
	int abort = 0;
	int count = 0;
	int count2 = 0;

	switch (argc) {
	case 1:
		/* print all fifos status information */
		printf("fifo level status\n");
		printf("______________________________\n");
		for (i=0; i<FIFO_COUNT; i++) {
			ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
			printf(" %d    %3d  %s%s%s %s\n",
			       i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
			       ctrl & FIFO_FULL ? "FULL     " : "",
			       ctrl & FIFO_EMPTY ? "EMPTY    " : "",
			       ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
			       ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
		}
		break;

	case 2:
		/* completely read out fifo 'n' */
		if (!strcmp(argv[1],"read")) {
			printf("  #   fifo level data\n");
			printf("______________________________\n");

			for (i=0; i<FIFO_COUNT; i++)
				dump_fifo(fpga, i, &n);

		} else if (!strcmp(argv[1],"wait")) {
			got_fifoirq = 0;

			irq_install_handler(IRQ0_FPGA,
					    (interrupt_handler_t *)fpga_interrupt,
					    fpga);

			printf("  #   fifo level data\n");
			printf("______________________________\n");

			/* enable all fifo interrupts */
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
			for (i=0; i<FIFO_COUNT; i++) {
				/* enable interrupts from all fifos */
				FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
			}

			while (1) {
				/* wait loop */
				while (!got_fifoirq) {
					count++;
					if (!(count % 100)) {
						count2++;
						putc(0x08); /* backspace */
						putc(str[count2 % 4]);
					}

					/* Abort if ctrl-c was pressed */
					if ((abort = ctrlc())) {
						puts("\nAbort\n");
						break;
					}
					udelay(1000);
				}
				if (abort)
					break;

				/* simple fifo backend */
				if (got_fifoirq) {
					for (i=0; i<FIFO_COUNT; i++)
						dump_fifo(fpga, i, &n);

					got_fifoirq = 0;
					/* unmask global fifo irq */
					FPGA_OUT32(&fpga->hostctrl,
						   HOSTCTRL_FIFOIE_GATE |
						   HOSTCTRL_FIFOIE_FLAG);
				}
			}

			/* disable all fifo interrupts */
			FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
			for (i=0; i<FIFO_COUNT; i++)
				FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);

			irq_free_handler(IRQ0_FPGA);

		} else {
			printf("Usage:\nfifo %s\n", cmdtp->help);
			return 1;
		}
		break;

	case 4:
	case 5:
		if (!strcmp(argv[1],"write")) {
			/* get fifo number or fifo address */
			f = simple_strtoul(argv[2], NULL, 16);

			/* data paramter */
			data = simple_strtoul(argv[3], NULL, 16);

			/* get optional count parameter */
			n = 1;
			if (argc >= 5)
				n = (int)simple_strtoul(argv[4], NULL, 10);

			if (f < FIFO_COUNT) {
				printf("writing %d x %08x to fifo %d\n",
				       n, data, f);
				for (i=0; i<n; i++)
					FPGA_OUT32(&fpga->fifo[f].data, data);
			} else {
				printf("writing %d x %08x to fifo port at "
				       "address %08x\n",
				       n, data, f);
				for (i=0; i<n; i++)
					out_be32((void *)f, data);
			}
		} else {
			printf("Usage:\nfifo %s\n", cmdtp->help);
			return 1;
		}
		break;

	default:
		printf("Usage:\nfifo %s\n", cmdtp->help);
		return 1;
	}
	return 0;
}
U_BOOT_CMD(
	fifo,	5,	1,	do_fifo,
	"Fifo module operations",
	"wait\nfifo read\n"
	"fifo write fifo(0..3) data [cnt=1]\n"
	"fifo write address(>=4) data [cnt=1]\n"
	"  - without arguments: print all fifo's status\n"
	"  - with 'wait' argument: interrupt driven read from all fifos\n"
	"  - with 'read' argument: read current contents from all fifos\n"
	"  - with 'write' argument: write 'data' 'cnt' times to "
	"'fifo' or 'address'"
);

int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong sdsdp[5];
	ulong delay;
	int count=16;

	if (argc < 2) {
		printf("Usage:\nsbe %s\n", cmdtp->help);
		return -1;
	}

	if (argc > 1) {
		if (!strcmp(argv[1], "400")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 400MHz\n");
			sdsdp[0]=0x8678624e;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else if (!strcmp(argv[1], "533")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 533MHz\n");
			sdsdp[0]=0x87788252;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else if (!strcmp(argv[1], "667")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 667MHz\n");
			sdsdp[0]=0x8778a256;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else {
			printf("Usage:\nsbe %s\n", cmdtp->help);
			return -1;
		}
	}

	if (argc > 2) {
		sdsdp[4] = 0;
		if (argv[2][0]=='1')
			sdsdp[4]=0x19750100;
		else if (argv[2][0]=='0')
			sdsdp[4]=0x19750000;
		if (sdsdp[4])
			count += 4;
	}

	if (argc > 3) {
		delay = simple_strtoul(argv[3], NULL, 10);
		if (delay > 20)
			delay = 20;
		sdsdp[4] |= delay;
	}

	printf("Writing boot EEPROM ...\n");
	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
				   0, (uchar*)sdsdp, count) != 0)
		printf("bootstrap_eeprom_write failed\n");
	else
		printf("done (dump via 'i2c md 52 0.1 14')\n");

	return 0;
}
U_BOOT_CMD(
	sbe, 4, 0, do_setup_bootstrap_eeprom,
	"setup bootstrap eeprom",
	"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
);

#if defined(CONFIG_PRAM)
#include <environment.h>
#include <search.h>
#include <errno.h>

int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	u32 pram, nextbase, base;
	char *v;
	u32 param;
	ulong *lptr;

	env_t *envp;
	char *res;
	int len;

	v = getenv("pram");
	if (v)
		pram = simple_strtoul(v, NULL, 10);
	else {
		printf("Error: pram undefined. Please define pram in KiB\n");
		return 1;
	}

	base = (u32)gd->ram_size;
#if defined(CONFIG_LOGBUFFER)
	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
#endif
	/*
	 * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
	 */
	param = base - (pram << 10);
	printf("PARAM: @%08x\n", param);
	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);

	/* clear entire PA ram */
	memset((void*)param, 0, (pram << 10));

	/* reserve 4k for pointer field */
	nextbase = base - 4096;
	lptr = (ulong*)(base);

	/*
	 * *(--lptr) = item_size;
	 * *(--lptr) = base - item_base = distance from field top;
	 */

	/* env is first (4k aligned) */
	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
	envp = (env_t *)nextbase;
	res = (char *)envp->data;
	len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
	if (len < 0) {
		error("Cannot export environment: errno = %d\n", errno);
		return 1;
	}
	envp->crc = crc32(0, envp->data, ENV_SIZE);

	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
	*(--lptr) = base - nextbase;  /* offset | type=0 */

	/* free section */
	*(--lptr) = nextbase - param; /* size */
	*(--lptr) = (base - param) | 126; /* offset | type=126 */

	/* terminate pointer field */
	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
	*(--lptr) = 0;                /* offset=0 -> terminator */
	return 0;
}
U_BOOT_CMD(
	painit,	1,	1,	do_painit,
	"prepare PciAccess system",
	""
);
#endif /* CONFIG_PRAM */

int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	in_be32((void*)CONFIG_SYS_RESET_BASE);
	return 0;
}
U_BOOT_CMD(
	selfreset,	1,	1,	do_selfreset,
	"assert self-reset# signal",
	""
);

int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;

	/* requiers bootet FPGA and PLD_IOEN_N active */
	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
		printf("Error: resetout requires a bootet FPGA\n");
		return -1;
	}

	if (argc > 1) {
		if (argv[1][0] == '0') {
			/* assert */
			printf("PMC-RESETOUT# asserted\n");
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_PMCRSTOUT_GATE);
		} else {
			/* deassert */
			printf("PMC-RESETOUT# deasserted\n");
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_PMCRSTOUT_GATE |
				   HOSTCTRL_PMCRSTOUT_FLAG);
		}
	} else {
		printf("PMC-RESETOUT# is %s\n",
		       FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
		       "inactive" : "active");
	}

	return 0;
}
U_BOOT_CMD(
	resetout,	2,	1,	do_resetout,
	"assert PMC-RESETOUT# signal",
	""
);

int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	if (is_monarch()) {
		printf("This command is only supported in non-monarch mode\n");
		return -1;
	}

	if (argc > 1) {
		if (argv[1][0] == '0') {
			/* assert */
			printf("inta# asserted\n");
			out_be32((void*)GPIO1_TCR,
				 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
		} else {
			/* deassert */
			printf("inta# deasserted\n");
			out_be32((void*)GPIO1_TCR,
				 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
		}
	} else {
		printf("inta# is %s\n",
		       in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
		       "active" : "inactive");
	}
	return 0;
}
U_BOOT_CMD(
	inta,	2,	1,	do_inta,
	"Assert/Deassert or query INTA# state in non-monarch mode",
	""
);

/* test-only */
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong pciaddr;

	if (argc > 1) {
		pciaddr = simple_strtoul(argv[1], NULL, 16);

		pciaddr &= 0xf0000000;

		/* map PCI address at 0xc0000000 in PLB space */

		/* PMM1 Mask/Attribute - disabled b4 setting */
		out32r(PCIL0_PMM1MA, 0x00000000);
		/* PMM1 Local Address */
		out32r(PCIL0_PMM1LA, 0xc0000000);
		/* PMM1 PCI Low Address */
		out32r(PCIL0_PMM1PCILA, pciaddr);
		/* PMM1 PCI High Address */
		out32r(PCIL0_PMM1PCIHA, 0x00000000);
		/* 256MB + No prefetching, and enable region */
		out32r(PCIL0_PMM1MA, 0xf0000001);
	} else {
		printf("Usage:\npmm %s\n", cmdtp->help);
	}
	return 0;
}
U_BOOT_CMD(
	pmm,	2,	1,	do_pmm,
	"Setup pmm[1] registers",
	"<pciaddr> (pciaddr will be aligned to 256MB)"
);

#if defined(CONFIG_SYS_EEPROM_WREN)
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int query = argc == 1;
	int state = 0;

	if (query) {
		/* Query write access state. */
		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
		if (state < 0) {
			puts("Query of write access state failed.\n");
		} else {
			printf("Write access for device 0x%0x is %sabled.\n",
			       CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
			state = 0;
		}
	} else {
		if ('0' == argv[1][0]) {
			/* Disable write access. */
			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
		} else {
			/* Enable write access. */
			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
		}
		if (state < 0) {
			puts("Setup of write access state failed.\n");
		}
	}

	return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
	"Enable / disable / query EEPROM write access",
	""
);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */

#endif /* CONFIG_CMD_BSP */
Commit	Line	Data
407843a5	1	/*
034394ab	2	* (C) Copyright 2007-2008
407843a5 MF	3	* Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
407843a5 MF	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
407843a5	6	*/
407843a5 MF	7	#include <common.h>
407843a5 MF	8	#include <command.h>
24b852a7	9	#include <console.h>
407843a5 MF	10	#include <asm/io.h>
	11	#include <asm/cache.h>
	12	#include <asm/processor.h>
75183b1a MF	13	#if defined(CONFIG_LOGBUFFER)
	14	#include <logbuff.h>
	15	#endif
407843a5 MF	16
	17	#include "pmc440.h"
	18
	19	int is_monarch(void);
034394ab MF	20	int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
034394ab MF	21	uchar *buffer, unsigned cnt);
407843a5 MF	22	int eeprom_write_enable(unsigned dev_addr, int state);
	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	#if defined(CONFIG_CMD_BSP)
	27
	28	static int got_fifoirq;
	29	static int got_hcirq;
	30
	31	int fpga_interrupt(u32 arg)
	32	{
	33	pmc440_fpga_t fpga = (pmc440_fpga_t )arg;
	34	int rc = -1; /* not for us */
	35	u32 status = FPGA_IN32(&fpga->status);
	36
	37	/* check for interrupt from fifo module */
	38	if (status & STATUS_FIFO_ISF) {
	39	/* disable this int source */
	40	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
	41	rc = 0;
	42	got_fifoirq = 1; /* trigger backend */
	43	}
	44
	45	if (status & STATUS_HOST_ISF) {
	46	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
	47	rc = 0;
	48	got_hcirq = 1;
	49	}
	50
	51	return rc;
	52	}
	53
54841ab5	54	int do_waithci(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	55	{
	56	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	57
	58	got_hcirq = 0;
	59
	60	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	61	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
	62
	63	irq_install_handler(IRQ0_FPGA,
	64	(interrupt_handler_t *)fpga_interrupt,
	65	fpga);
	66
	67	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
	68
	69	while (!got_hcirq) {
	70	/* Abort if ctrl-c was pressed */
	71	if (ctrlc()) {
	72	puts("\nAbort\n");
	73	break;
	74	}
	75	}
	76	if (got_hcirq)
	77	printf("Got interrupt!\n");
	78
	79	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	80	irq_free_handler(IRQ0_FPGA);
	81	return 0;
	82	}
	83	U_BOOT_CMD(
	84	waithci, 1, 1, do_waithci,
2fb2604d	85	"Wait for host control interrupt",
a89c33db WD	86	""
a89c33db WD	87	);
407843a5	88
407843a5 MF	89	void dump_fifo(pmc440_fpga_t fpga, int f, int n)
	90	{
	91	u32 ctrl;
	92
	93	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
	94	printf("%5d %d %3d %08x",
	95	(*n)++, f, ctrl & (FIFO_LEVEL_MASK \| FIFO_FULL),
	96	FPGA_IN32(&fpga->fifo[f].data));
	97	if (ctrl & FIFO_OVERFLOW) {
	98	printf(" OVERFLOW\n");
	99	FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
	100	} else
	101	printf("\n");
	102	}
	103	}
	104
54841ab5	105	int do_fifo(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	106	{
	107	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	108	int i;
	109	int n = 0;
	110	u32 ctrl, data, f;
	111	char str[] = "\\\|/-";
	112	int abort = 0;
	113	int count = 0;
	114	int count2 = 0;
	115
	116	switch (argc) {
	117	case 1:
	118	/* print all fifos status information */
	119	printf("fifo level status\n");
	120	printf("______________________________\n");
	121	for (i=0; i<FIFO_COUNT; i++) {
	122	ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
	123	printf(" %d %3d %s%s%s %s\n",
	124	i, ctrl & (FIFO_LEVEL_MASK \| FIFO_FULL),
	125	ctrl & FIFO_FULL ? "FULL " : "",
	126	ctrl & FIFO_EMPTY ? "EMPTY " : "",
	127	ctrl & (FIFO_FULL\|FIFO_EMPTY) ? "" : "NOT EMPTY",
	128	ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
	129	}
	130	break;
	131
	132	case 2:
	133	/* completely read out fifo 'n' */
	134	if (!strcmp(argv[1],"read")) {
	135	printf(" # fifo level data\n");
	136	printf("______________________________\n");
	137
	138	for (i=0; i<FIFO_COUNT; i++)
	139	dump_fifo(fpga, i, &n);
	140
	141	} else if (!strcmp(argv[1],"wait")) {
	142	got_fifoirq = 0;
	143
	144	irq_install_handler(IRQ0_FPGA,
	145	(interrupt_handler_t *)fpga_interrupt,
	146	fpga);
	147
	148	printf(" # fifo level data\n");
	149	printf("______________________________\n");
	150
	151	/* enable all fifo interrupts */
	152	FPGA_OUT32(&fpga->hostctrl,
	153	HOSTCTRL_FIFOIE_GATE \| HOSTCTRL_FIFOIE_FLAG);
	154	for (i=0; i<FIFO_COUNT; i++) {
	155	/* enable interrupts from all fifos */
	156	FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
	157	}
	158
	159	while (1) {
	160	/* wait loop */
	161	while (!got_fifoirq) {
	162	count++;
	163	if (!(count % 100)) {
	164	count2++;
	165	putc(0x08); /* backspace */
	166	putc(str[count2 % 4]);
	167	}
	168
	169	/* Abort if ctrl-c was pressed */
170	if ((abort = ctrlc())) {
171	puts("\nAbort\n");
172	break;
173	}
174	udelay(1000);
175	}
176	if (abort)
177	break;
178
179	/* simple fifo backend */
180	if (got_fifoirq) {
181	for (i=0; i<FIFO_COUNT; i++)
182	dump_fifo(fpga, i, &n);
183
184	got_fifoirq = 0;
185	/* unmask global fifo irq */
186	FPGA_OUT32(&fpga->hostctrl,
034394ab MF	187	HOSTCTRL_FIFOIE_GATE \|
034394ab MF	188	HOSTCTRL_FIFOIE_FLAG);
407843a5 MF	189	}
	190	}
	191
	192	/* disable all fifo interrupts */
	193	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
	194	for (i=0; i<FIFO_COUNT; i++)
	195	FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
	196
	197	irq_free_handler(IRQ0_FPGA);
	198
	199	} else {
	200	printf("Usage:\nfifo %s\n", cmdtp->help);
	201	return 1;
	202	}
	203	break;
	204
	205	case 4:
	206	case 5:
	207	if (!strcmp(argv[1],"write")) {
	208	/* get fifo number or fifo address */
	209	f = simple_strtoul(argv[2], NULL, 16);
	210
	211	/* data paramter */
	212	data = simple_strtoul(argv[3], NULL, 16);
	213
	214	/* get optional count parameter */
	215	n = 1;
	216	if (argc >= 5)
	217	n = (int)simple_strtoul(argv[4], NULL, 10);
	218
	219	if (f < FIFO_COUNT) {
	220	printf("writing %d x %08x to fifo %d\n",
	221	n, data, f);
	222	for (i=0; i<n; i++)
	223	FPGA_OUT32(&fpga->fifo[f].data, data);
	224	} else {
034394ab MF	225	printf("writing %d x %08x to fifo port at "
034394ab MF	226	"address %08x\n",
407843a5 MF	227	n, data, f);
407843a5 MF	228	for (i=0; i<n; i++)
bb57ad4b	229	out_be32((void *)f, data);
407843a5 MF	230	}
	231	} else {
	232	printf("Usage:\nfifo %s\n", cmdtp->help);
	233	return 1;
	234	}
	235	break;
	236
	237	default:
	238	printf("Usage:\nfifo %s\n", cmdtp->help);
	239	return 1;
	240	}
	241	return 0;
	242	}
	243	U_BOOT_CMD(
	244	fifo, 5, 1, do_fifo,
2fb2604d	245	"Fifo module operations",
407843a5 MF	246	"wait\nfifo read\n"
	247	"fifo write fifo(0..3) data [cnt=1]\n"
	248	"fifo write address(>=4) data [cnt=1]\n"
	249	" - without arguments: print all fifo's status\n"
	250	" - with 'wait' argument: interrupt driven read from all fifos\n"
	251	" - with 'read' argument: read current contents from all fifos\n"
034394ab	252	" - with 'write' argument: write 'data' 'cnt' times to "
a89c33db WD	253	"'fifo' or 'address'"
a89c33db WD	254	);
407843a5	255
54841ab5	256	int do_setup_bootstrap_eeprom(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	257	{
	258	ulong sdsdp[5];
	259	ulong delay;
	260	int count=16;
	261
	262	if (argc < 2) {
	263	printf("Usage:\nsbe %s\n", cmdtp->help);
	264	return -1;
	265	}
	266
	267	if (argc > 1) {
	268	if (!strcmp(argv[1], "400")) {
ff5fb8a6	269	/* PLB=133MHz, PLB/PCI=3 */
407843a5 MF	270	printf("Bootstrapping for 400MHz\n");
407843a5 MF	271	sdsdp[0]=0x8678624e;
ff5fb8a6	272	sdsdp[1]=0x095fa030;
407843a5 MF	273	sdsdp[2]=0x40082350;
	274	sdsdp[3]=0x0d050000;
	275	} else if (!strcmp(argv[1], "533")) {
	276	/* PLB=133MHz, PLB/PCI=3 */
	277	printf("Bootstrapping for 533MHz\n");
	278	sdsdp[0]=0x87788252;
	279	sdsdp[1]=0x095fa030;
	280	sdsdp[2]=0x40082350;
	281	sdsdp[3]=0x0d050000;
	282	} else if (!strcmp(argv[1], "667")) {
79941d63	283	/* PLB=133MHz, PLB/PCI=3 */
407843a5 MF	284	printf("Bootstrapping for 667MHz\n");
407843a5 MF	285	sdsdp[0]=0x8778a256;
407843a5 MF	286	sdsdp[1]=0x095fa030;
	287	sdsdp[2]=0x40082350;
	288	sdsdp[3]=0x0d050000;
	289	} else {
	290	printf("Usage:\nsbe %s\n", cmdtp->help);
	291	return -1;
	292	}
	293	}
	294
	295	if (argc > 2) {
	296	sdsdp[4] = 0;
	297	if (argv[2][0]=='1')
	298	sdsdp[4]=0x19750100;
	299	else if (argv[2][0]=='0')
	300	sdsdp[4]=0x19750000;
	301	if (sdsdp[4])
	302	count += 4;
	303	}
	304
	305	if (argc > 3) {
	306	delay = simple_strtoul(argv[3], NULL, 10);
	307	if (delay > 20)
	308	delay = 20;
	309	sdsdp[4] \|= delay;
	310	}
	311
	312	printf("Writing boot EEPROM ...\n");
6d0f6bcf	313	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
407843a5 MF	314	0, (uchar*)sdsdp, count) != 0)
	315	printf("bootstrap_eeprom_write failed\n");
	316	else
	317	printf("done (dump via 'i2c md 52 0.1 14')\n");
	318
	319	return 0;
	320	}
	321	U_BOOT_CMD(
	322	sbe, 4, 0, do_setup_bootstrap_eeprom,
2fb2604d	323	"setup bootstrap eeprom",
407843a5	324	"<cpufreq:400\|533\|667> [<console-uart:0\|1> [<bringup delay (0..20s)>]]"
a89c33db	325	);
407843a5	326
407843a5 MF	327	#if defined(CONFIG_PRAM)
407843a5 MF	328	#include <environment.h>
a6569c63 MF	329	#include <search.h>
a6569c63 MF	330	#include <errno.h>
407843a5	331
54841ab5	332	int do_painit(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5	333	{
75183b1a	334	u32 pram, nextbase, base;
407843a5 MF	335	char *v;
	336	u32 param;
	337	ulong *lptr;
	338
a6569c63 MF	339	env_t *envp;
	340	char *res;
	341	int len;
	342
407843a5 MF	343	v = getenv("pram");
	344	if (v)
	345	pram = simple_strtoul(v, NULL, 10);
	346	else {
	347	printf("Error: pram undefined. Please define pram in KiB\n");
	348	return 1;
	349	}
	350
f39c5d1e	351	base = (u32)gd->ram_size;
75183b1a MF	352	#if defined(CONFIG_LOGBUFFER)
	353	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
	354	#endif
	355	/*
f39c5d1e	356	* gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
75183b1a MF	357	*/
75183b1a MF	358	param = base - (pram << 10);
407843a5	359	printf("PARAM: @%08x\n", param);
f39c5d1e	360	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
407843a5	361
75183b1a	362	/* clear entire PA ram */
407843a5	363	memset((void*)param, 0, (pram << 10));
407843a5	364
75183b1a MF	365	/* reserve 4k for pointer field */
	366	nextbase = base - 4096;
	367	lptr = (ulong*)(base);
	368
	369	/*
	370	* *(--lptr) = item_size;
	371	* *(--lptr) = base - item_base = distance from field top;
	372	*/
	373
	374	/* env is first (4k aligned) */
	375	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
a6569c63 MF	376	envp = (env_t *)nextbase;
a6569c63 MF	377	res = (char *)envp->data;
be11235a	378	len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
a6569c63 MF	379	if (len < 0) {
	380	error("Cannot export environment: errno = %d\n", errno);
	381	return 1;
	382	}
	383	envp->crc = crc32(0, envp->data, ENV_SIZE);
	384
75183b1a MF	385	(--lptr) = CONFIG_ENV_SIZE; / size */
75183b1a MF	386	(--lptr) = base - nextbase; / offset \| type=0 */
407843a5	387
75183b1a MF	388	/* free section */
	389	(--lptr) = nextbase - param; / size */
	390	(--lptr) = (base - param) \| 126; / offset \| type=126 */
	391
	392	/* terminate pointer field */
	393	(--lptr) = crc32(0, (void)(base - 0x10), 0x10);
	394	(--lptr) = 0; / offset=0 -> terminator */
407843a5 MF	395	return 0;
	396	}
	397	U_BOOT_CMD(
	398	painit, 1, 1, do_painit,
2fb2604d	399	"prepare PciAccess system",
a89c33db WD	400	""
a89c33db WD	401	);
407843a5 MF	402	#endif /* CONFIG_PRAM */
407843a5 MF	403
54841ab5	404	int do_selfreset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5	405	{
75183b1a	406	in_be32((void*)CONFIG_SYS_RESET_BASE);
407843a5 MF	407	return 0;
	408	}
	409	U_BOOT_CMD(
75183b1a	410	selfreset, 1, 1, do_selfreset,
2fb2604d	411	"assert self-reset# signal",
a89c33db WD	412	""
a89c33db WD	413	);
407843a5	414
54841ab5	415	int do_resetout(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	416	{
	417	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	418
	419	/* requiers bootet FPGA and PLD_IOEN_N active */
	420	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
	421	printf("Error: resetout requires a bootet FPGA\n");
	422	return -1;
	423	}
	424
	425	if (argc > 1) {
	426	if (argv[1][0] == '0') {
	427	/* assert */
	428	printf("PMC-RESETOUT# asserted\n");
	429	FPGA_OUT32(&fpga->hostctrl,
	430	HOSTCTRL_PMCRSTOUT_GATE);
	431	} else {
	432	/* deassert */
	433	printf("PMC-RESETOUT# deasserted\n");
	434	FPGA_OUT32(&fpga->hostctrl,
034394ab MF	435	HOSTCTRL_PMCRSTOUT_GATE \|
034394ab MF	436	HOSTCTRL_PMCRSTOUT_FLAG);
407843a5 MF	437	}
	438	} else {
	439	printf("PMC-RESETOUT# is %s\n",
	440	FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
	441	"inactive" : "active");
	442	}
	443
	444	return 0;
	445	}
	446	U_BOOT_CMD(
	447	resetout, 2, 1, do_resetout,
2fb2604d	448	"assert PMC-RESETOUT# signal",
a89c33db WD	449	""
a89c33db WD	450	);
407843a5	451
54841ab5	452	int do_inta(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	453	{
	454	if (is_monarch()) {
	455	printf("This command is only supported in non-monarch mode\n");
	456	return -1;
	457	}
	458
	459	if (argc > 1) {
	460	if (argv[1][0] == '0') {
	461	/* assert */
	462	printf("inta# asserted\n");
	463	out_be32((void*)GPIO1_TCR,
	464	in_be32((void*)GPIO1_TCR) \| GPIO1_INTA_FAKE);
	465	} else {
	466	/* deassert */
	467	printf("inta# deasserted\n");
	468	out_be32((void*)GPIO1_TCR,
	469	in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
	470	}
	471	} else {
034394ab MF	472	printf("inta# is %s\n",
	473	in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
	474	"active" : "inactive");
407843a5 MF	475	}
	476	return 0;
	477	}
	478	U_BOOT_CMD(
	479	inta, 2, 1, do_inta,
2fb2604d	480	"Assert/Deassert or query INTA# state in non-monarch mode",
a89c33db WD	481	""
a89c33db WD	482	);
407843a5	483
407843a5	484	/* test-only */
54841ab5	485	int do_pmm(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	486	{
	487	ulong pciaddr;
	488
	489	if (argc > 1) {
	490	pciaddr = simple_strtoul(argv[1], NULL, 16);
	491
	492	pciaddr &= 0xf0000000;
	493
	494	/* map PCI address at 0xc0000000 in PLB space */
034394ab	495
02e38920	496	/* PMM1 Mask/Attribute - disabled b4 setting */
ddc922ff	497	out32r(PCIL0_PMM1MA, 0x00000000);
02e38920	498	/* PMM1 Local Address */
ddc922ff	499	out32r(PCIL0_PMM1LA, 0xc0000000);
02e38920	500	/* PMM1 PCI Low Address */
ddc922ff	501	out32r(PCIL0_PMM1PCILA, pciaddr);
02e38920	502	/* PMM1 PCI High Address */
ddc922ff	503	out32r(PCIL0_PMM1PCIHA, 0x00000000);
02e38920	504	/* 256MB + No prefetching, and enable region */
ddc922ff	505	out32r(PCIL0_PMM1MA, 0xf0000001);
407843a5 MF	506	} else {
	507	printf("Usage:\npmm %s\n", cmdtp->help);
	508	}
	509	return 0;
	510	}
	511	U_BOOT_CMD(
	512	pmm, 2, 1, do_pmm,
2fb2604d	513	"Setup pmm[1] registers",
a89c33db WD	514	"<pciaddr> (pciaddr will be aligned to 256MB)"
a89c33db WD	515	);
407843a5	516
6d0f6bcf	517	#if defined(CONFIG_SYS_EEPROM_WREN)
54841ab5	518	int do_eep_wren(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	519	{
	520	int query = argc == 1;
	521	int state = 0;
	522
	523	if (query) {
	524	/* Query write access state. */
6d0f6bcf	525	state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
407843a5 MF	526	if (state < 0) {
	527	puts("Query of write access state failed.\n");
	528	} else {
	529	printf("Write access for device 0x%0x is %sabled.\n",
6d0f6bcf	530	CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
407843a5 MF	531	state = 0;
	532	}
	533	} else {
	534	if ('0' == argv[1][0]) {
	535	/* Disable write access. */
6d0f6bcf	536	state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
407843a5 MF	537	} else {
407843a5 MF	538	/* Enable write access. */
6d0f6bcf	539	state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
407843a5 MF	540	}
	541	if (state < 0) {
	542	puts("Setup of write access state failed.\n");
	543	}
	544	}
	545
	546	return state;
	547	}
	548	U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
a89c33db WD	549	"Enable / disable / query EEPROM write access",
	550	""
	551	);
6d0f6bcf	552	#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
407843a5 MF	553
407843a5 MF	554	#endif /* CONFIG_CMD_BSP */