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72c5d52a MF |
1 | /* |
2 | * | |
3 | * See file CREDITS for list of people who contributed to this | |
4 | * project. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <ppc_asm.tmpl> | |
61f2b38a | 23 | #include <asm/mmu.h> |
72c5d52a MF |
24 | #include <config.h> |
25 | ||
3b4bd2d7 | 26 | /* |
72c5d52a MF |
27 | * TLB TABLE |
28 | * | |
29 | * This table is used by the cpu boot code to setup the initial tlb | |
30 | * entries. Rather than make broad assumptions in the cpu source tree, | |
31 | * this table lets each board set things up however they like. | |
32 | * | |
33 | * Pointer to the table is returned in r1 | |
34 | * | |
3b4bd2d7 | 35 | */ |
72c5d52a MF |
36 | .section .bootpg,"ax" |
37 | .globl tlbtab | |
38 | ||
39 | tlbtab: | |
40 | tlbtab_start | |
41 | ||
42 | /* | |
43 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
44 | * speed up boot process. It is patched after relocation to enable SA_I | |
45 | */ | |
46 | #ifndef CONFIG_NAND_SPL | |
6d0f6bcf | 47 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) |
72c5d52a | 48 | #else |
6d0f6bcf | 49 | tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) |
72c5d52a MF |
50 | #endif |
51 | ||
3b4bd2d7 | 52 | /* TLB entries for DDR2 SDRAM are generated dynamically */ |
72c5d52a | 53 | |
6d0f6bcf | 54 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
72c5d52a | 55 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
6d0f6bcf | 56 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) |
72c5d52a MF |
57 | #endif |
58 | ||
59 | /* TLB-entry for PCI Memory */ | |
6d0f6bcf JCPV |
60 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) |
61 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) | |
62 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) | |
63 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) | |
72c5d52a MF |
64 | |
65 | /* TLB-entries for EBC */ | |
66 | /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral | |
67 | * tlb entry. | |
68 | * This dummy entry is only for convinience in order not to modify the | |
69 | * amount of entries. Currently OS/9 relies on this :-) | |
70 | */ | |
71 | tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
72 | ||
73 | /* TLB-entry for NAND */ | |
6d0f6bcf | 74 | tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
72c5d52a MF |
75 | |
76 | /* TLB-entry for Internal Registers & OCM */ | |
77 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) | |
78 | ||
79 | /*TLB-entry PCI registers*/ | |
80 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
81 | ||
82 | /* TLB-entry for peripherals */ | |
83 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) | |
84 | ||
85 | /* TLB-entry PCI IO space */ | |
86 | tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) | |
87 | ||
88 | /* TODO: what about high IO space */ | |
89 | tlbtab_end | |
90 | ||
91 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
92 | /* | |
93 | * For NAND booting the first TLB has to be reconfigured to full size | |
94 | * and with caching disabled after running from RAM! | |
95 | */ | |
6d0f6bcf JCPV |
96 | #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) |
97 | #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) | |
72c5d52a MF |
98 | #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) |
99 | ||
100 | .globl reconfig_tlb0 | |
101 | reconfig_tlb0: | |
102 | sync | |
103 | isync | |
104 | addi r4,r0,0x0000 /* TLB entry #0 */ | |
105 | lis r5,TLB00@h | |
106 | ori r5,r5,TLB00@l | |
107 | tlbwe r5,r4,0x0000 /* Save it out */ | |
108 | lis r5,TLB01@h | |
109 | ori r5,r5,TLB01@l | |
110 | tlbwe r5,r4,0x0001 /* Save it out */ | |
111 | lis r5,TLB02@h | |
112 | ori r5,r5,TLB02@l | |
113 | tlbwe r5,r4,0x0002 /* Save it out */ | |
114 | sync | |
115 | isync | |
116 | blr | |
117 | #endif |