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72c5d52a | 1 | /* |
492aa9ea | 2 | * (C) Copyright 2007-2008 |
72c5d52a MF |
3 | * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
72c5d52a MF |
6 | */ |
7 | ||
8 | #ifndef __PMC440_H__ | |
9 | #define __PMC440_H__ | |
10 | ||
492aa9ea | 11 | /* |
72c5d52a MF |
12 | * GPIOs |
13 | */ | |
14 | #define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ | |
15 | #define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */ | |
16 | #define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */ | |
17 | #define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */ | |
18 | #define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */ | |
19 | #define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */ | |
20 | #define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */ | |
21 | ||
22 | #define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */ | |
23 | #define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */ | |
24 | #define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ | |
25 | #define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ | |
26 | #define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ | |
72c5d52a | 27 | |
492aa9ea MF |
28 | /* |
29 | * FPGA programming pin configuration | |
30 | */ | |
72c5d52a MF |
31 | #define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ |
32 | #define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ | |
33 | #define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ | |
34 | #define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */ | |
35 | #define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ | |
36 | #define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ | |
37 | ||
492aa9ea | 38 | /* |
72c5d52a MF |
39 | * FPGA interface |
40 | */ | |
6d0f6bcf | 41 | #define FPGA_BA CONFIG_SYS_FPGA_BASE0 |
72c5d52a MF |
42 | #define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v)) |
43 | #define FPGA_IN32(p) in_be32((void*)(p)) | |
44 | #define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v)) | |
45 | #define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v)) | |
46 | ||
47 | struct pmc440_fifo_s { | |
48 | u32 data; | |
49 | u32 ctrl; | |
50 | }; | |
51 | ||
52 | /* fifo ctrl register */ | |
53 | #define FIFO_IE (1 << 15) | |
54 | #define FIFO_OVERFLOW (1 << 10) | |
55 | #define FIFO_EMPTY (1 << 9) | |
56 | #define FIFO_FULL (1 << 8) | |
57 | #define FIFO_LEVEL_MASK 0x000000ff | |
58 | ||
59 | #define FIFO_COUNT 4 | |
60 | ||
61 | struct pmc440_fpga_s { | |
62 | u32 ctrla; | |
63 | u32 status; | |
64 | u32 ctrlb; | |
65 | u32 pad1[0x40 / sizeof(u32) - 3]; | |
66 | u32 irig_time; /* offset: 0x0040 */ | |
67 | u32 irig_tod; | |
68 | u32 irig_cf; | |
69 | u32 pad2; | |
70 | u32 irig_rx_time; /* offset: 0x0050 */ | |
71 | u32 pad3[3]; | |
72 | u32 hostctrl; /* offset: 0x0060 */ | |
73 | u32 pad4[0x20 / sizeof(u32) - 1]; | |
74 | struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */ | |
75 | }; | |
76 | ||
77 | typedef struct pmc440_fpga_s pmc440_fpga_t; | |
78 | ||
79 | /* ctrl register */ | |
80 | #define CTRL_HOST_IE (1 << 8) | |
81 | ||
82 | /* outputs */ | |
83 | #define RESET_EN (1 << 31) | |
84 | #define CLOCK_EN (1 << 30) | |
85 | #define RESET_OUT (1 << 19) | |
86 | #define CLOCK_OUT (1 << 22) | |
87 | #define RESET_OUT (1 << 19) | |
88 | #define IRIGB_R_OUT (1 << 14) | |
89 | ||
72c5d52a MF |
90 | /* status register */ |
91 | #define STATUS_VERSION_SHIFT 24 | |
92 | #define STATUS_VERSION_MASK 0xff000000 | |
93 | #define STATUS_HWREV_SHIFT 20 | |
94 | #define STATUS_HWREV_MASK 0x00f00000 | |
95 | ||
96 | #define STATUS_CAN_ISF (1 << 11) | |
97 | #define STATUS_CSTM_ISF (1 << 10) | |
98 | #define STATUS_FIFO_ISF (1 << 9) | |
99 | #define STATUS_HOST_ISF (1 << 8) | |
100 | ||
72c5d52a MF |
101 | /* inputs */ |
102 | #define RESET_IN (1 << 0) | |
103 | #define CLOCK_IN (1 << 1) | |
104 | #define IRIGB_R_IN (1 << 5) | |
105 | ||
72c5d52a MF |
106 | /* hostctrl register */ |
107 | #define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) | |
108 | #define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) | |
109 | #define HOSTCTRL_CSTM1IE_GATE (1 << 7) | |
110 | #define HOSTCTRL_CSTM1IW_FLAG (1 << 6) | |
111 | #define HOSTCTRL_CSTM0IE_GATE (1 << 5) | |
112 | #define HOSTCTRL_CSTM0IW_FLAG (1 << 4) | |
113 | #define HOSTCTRL_FIFOIE_GATE (1 << 3) | |
114 | #define HOSTCTRL_FIFOIE_FLAG (1 << 2) | |
115 | #define HOSTCTRL_HCINT_GATE (1 << 1) | |
116 | #define HOSTCTRL_HCINT_FLAG (1 << 0) | |
117 | ||
6d0f6bcf | 118 | #define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000) |
72c5d52a MF |
119 | #define NGCC_CTRL_FPGARST_N (1 << 2) |
120 | ||
492aa9ea | 121 | /* |
72c5d52a MF |
122 | * FPGA to PPC interrupt |
123 | */ | |
124 | #define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ | |
125 | #define IRQ1_FPGA (32+30) /* UIC1 - custom module */ | |
126 | #define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */ | |
127 | #define IRQ_ETH0 (64+ 4) /* UIC2 */ | |
128 | #define IRQ_ETH1 ( 27) /* UIC0 */ | |
129 | #define IRQ_RTC (64+ 0) /* UIC2 */ | |
130 | #define IRQ_PCIA (64+ 1) /* UIC2 */ | |
131 | #define IRQ_PCIB (32+18) /* UIC1 */ | |
132 | #define IRQ_PCIC (32+19) /* UIC1 */ | |
133 | #define IRQ_PCID (32+20) /* UIC1 */ | |
134 | ||
135 | #endif /* __PMC440_H__ */ |