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c2e49f70 RA |
1 | /* |
2 | * pci.c -- esd VME8349 PCI board support. | |
3 | * Copyright (c) 2006 Wind River Systems, Inc. | |
4 | * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. | |
a0daa2e0 RA |
5 | * Copyright (c) 2009 esd gmbh. |
6 | * | |
7 | * Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
c2e49f70 RA |
8 | * |
9 | * Based on MPC8349 PCI support but w/o PIB related code. | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <asm/mmu.h> | |
32 | #include <asm/io.h> | |
33 | #include <common.h> | |
34 | #include <mpc83xx.h> | |
35 | #include <pci.h> | |
36 | #include <i2c.h> | |
37 | #include <asm/fsl_i2c.h> | |
a0daa2e0 | 38 | #include "vme8349pin.h" |
c2e49f70 RA |
39 | |
40 | DECLARE_GLOBAL_DATA_PTR; | |
41 | ||
42 | static struct pci_region pci1_regions[] = { | |
43 | { | |
44 | bus_start: CONFIG_SYS_PCI1_MEM_BASE, | |
45 | phys_start: CONFIG_SYS_PCI1_MEM_PHYS, | |
46 | size: CONFIG_SYS_PCI1_MEM_SIZE, | |
47 | flags: PCI_REGION_MEM | PCI_REGION_PREFETCH | |
48 | }, | |
49 | { | |
50 | bus_start: CONFIG_SYS_PCI1_IO_BASE, | |
51 | phys_start: CONFIG_SYS_PCI1_IO_PHYS, | |
52 | size: CONFIG_SYS_PCI1_IO_SIZE, | |
53 | flags: PCI_REGION_IO | |
54 | }, | |
55 | { | |
56 | bus_start: CONFIG_SYS_PCI1_MMIO_BASE, | |
57 | phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, | |
58 | size: CONFIG_SYS_PCI1_MMIO_SIZE, | |
59 | flags: PCI_REGION_MEM | |
60 | }, | |
61 | }; | |
62 | ||
63 | /* | |
64 | * pci_init_board() | |
65 | * | |
66 | * NOTICE: PCI2 is not supported. There is only one | |
67 | * physical PCI slot on the board. | |
68 | * | |
69 | */ | |
70 | void | |
71 | pci_init_board(void) | |
72 | { | |
73 | volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; | |
74 | volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; | |
75 | volatile law83xx_t *pci_law = immr->sysconf.pcilaw; | |
76 | struct pci_region *reg[] = { pci1_regions }; | |
77 | u8 reg8; | |
78 | int monarch = 0; | |
79 | ||
80 | i2c_set_bus_num(1); | |
81 | /* Read the PCI_M66EN jumper setting */ | |
82 | if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) || | |
83 | (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) { | |
84 | if (reg8 & 0x40) { | |
85 | clk->occr = 0xff000000; /* 66 MHz PCI */ | |
86 | printf("PCI: 66MHz\n"); | |
87 | } else { | |
88 | clk->occr = 0xffff0003; /* 33 MHz PCI */ | |
89 | printf("PCI: 33MHz\n"); | |
90 | } | |
91 | if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0)) | |
92 | monarch = 1; | |
93 | } else { | |
94 | clk->occr = 0xffff0003; /* 33 MHz PCI */ | |
95 | printf("PCI: 33MHz (I2C read failed)\n"); | |
96 | } | |
97 | udelay(2000); | |
98 | ||
99 | /* | |
a0daa2e0 | 100 | * Assert/deassert VME reset |
c2e49f70 | 101 | */ |
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102 | clrsetbits_be32(&immr->gpio[1].dat, |
103 | GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N, | |
104 | GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N); | |
105 | setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N | | |
106 | GPIO2_TSI_POWERUP_RESET_N | | |
107 | GPIO2_VME_RESET_N | | |
108 | GPIO2_L_RESET_EN_N); | |
109 | clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON); | |
c2e49f70 | 110 | udelay(200); |
a0daa2e0 | 111 | setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N); |
c2e49f70 | 112 | udelay(200); |
a0daa2e0 | 113 | setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N); |
c2e49f70 | 114 | udelay(600000); |
a0daa2e0 | 115 | clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N); |
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116 | |
117 | /* Configure PCI Local Access Windows */ | |
118 | pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; | |
119 | pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; | |
120 | ||
121 | pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; | |
122 | pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; | |
123 | ||
124 | udelay(2000); | |
125 | ||
a0daa2e0 | 126 | if (monarch == 0) { |
c2e49f70 | 127 | mpc83xx_pci_init(1, reg, 0); |
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128 | } else { |
129 | /* | |
130 | * Release PCI RST Output signal | |
131 | */ | |
132 | out_be32(&immr->pci_ctrl[0].gcr, 0); | |
133 | udelay(2000); | |
134 | out_be32(&immr->pci_ctrl[0].gcr, 1); | |
135 | } | |
c2e49f70 | 136 | } |