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c2e49f70 RA |
1 | /* |
2 | * vme8349.c -- esd VME8349 board support | |
3 | * | |
4 | * Copyright (c) 2008-2009 esd gmbh. | |
5 | * | |
6 | * (C) Copyright 2006 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
10 | * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) | |
11 | * | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
c2e49f70 RA |
13 | */ |
14 | ||
15 | #include <common.h> | |
16 | #include <ioports.h> | |
17 | #include <mpc83xx.h> | |
18 | #include <asm/mpc8349_pci.h> | |
19 | #if defined(CONFIG_OF_LIBFDT) | |
20 | #include <libfdt.h> | |
21 | #endif | |
22 | #include <asm/io.h> | |
23 | #include <asm/mmu.h> | |
1dee9be6 RA |
24 | #include <spd.h> |
25 | #include <spd_sdram.h> | |
26 | #include <i2c.h> | |
27 | #include <netdev.h> | |
c2e49f70 | 28 | |
088454cd SG |
29 | DECLARE_GLOBAL_DATA_PTR; |
30 | ||
c2e49f70 RA |
31 | void ddr_enable_ecc(unsigned int dram_size); |
32 | ||
088454cd | 33 | int initdram(void) |
c2e49f70 RA |
34 | { |
35 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
36 | u32 msize = 0; | |
37 | ||
38 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) | |
088454cd | 39 | return -ENXIO; |
c2e49f70 | 40 | |
1dee9be6 | 41 | /* DDR SDRAM - Main memory */ |
c2e49f70 RA |
42 | im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; |
43 | ||
1dee9be6 | 44 | msize = spd_sdram(); |
c2e49f70 RA |
45 | |
46 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
47 | /* | |
48 | * Initialize and enable DDR ECC. | |
49 | */ | |
50 | ddr_enable_ecc(msize * 1024 * 1024); | |
51 | #endif | |
52 | ||
53 | /* Now check memory size (after ECC is initialized) */ | |
54 | msize = get_ram_size(0, msize); | |
55 | ||
56 | /* return total bus SDRAM size(bytes) -- DDR */ | |
088454cd SG |
57 | gd->ram_size = msize * 1024 * 1024; |
58 | ||
59 | return 0; | |
c2e49f70 RA |
60 | } |
61 | ||
62 | int checkboard(void) | |
63 | { | |
1dee9be6 RA |
64 | #ifdef VME_CADDY2 |
65 | puts("Board: esd VME-CADDY/2\n"); | |
66 | #else | |
67 | puts("Board: esd VME-CPU/8349\n"); | |
68 | #endif | |
c2e49f70 RA |
69 | |
70 | return 0; | |
71 | } | |
72 | ||
1dee9be6 RA |
73 | #ifdef VME_CADDY2 |
74 | int board_eth_init(bd_t *bis) | |
75 | { | |
76 | return pci_eth_init(bis); | |
77 | } | |
78 | #endif | |
79 | ||
c2e49f70 | 80 | #if defined(CONFIG_OF_BOARD_SETUP) |
e895a4b0 | 81 | int ft_board_setup(void *blob, bd_t *bd) |
c2e49f70 RA |
82 | { |
83 | ft_cpu_setup(blob, bd); | |
1dee9be6 | 84 | |
c2e49f70 RA |
85 | #ifdef CONFIG_PCI |
86 | ft_pci_setup(blob, bd); | |
87 | #endif | |
e895a4b0 SG |
88 | |
89 | return 0; | |
c2e49f70 RA |
90 | } |
91 | #endif | |
1dee9be6 RA |
92 | |
93 | int misc_init_r() | |
94 | { | |
95 | immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
96 | ||
f51cdaf1 | 97 | clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0); |
1dee9be6 RA |
98 | |
99 | return 0; | |
100 | } | |
101 | ||
102 | /* | |
103 | * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 | |
104 | * and VME-CADDY/2) have different SDRAM configurations. | |
105 | */ | |
106 | #ifdef VME_CADDY2 | |
107 | #define SMALL_RAM 0xff | |
108 | #define LARGE_RAM 0x00 | |
109 | #else | |
110 | #define SMALL_RAM 0x00 | |
111 | #define LARGE_RAM 0xff | |
112 | #endif | |
113 | ||
114 | #define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM)) | |
115 | ||
116 | static spd_eeprom_t default_spd_eeprom = { | |
117 | SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */ | |
118 | SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */ | |
119 | SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */ | |
120 | SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */ | |
121 | SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */ | |
122 | SPD_VAL(0x00, 0x00), /* 05 */ | |
123 | SPD_VAL(0x40, 0x40), /* 06 */ | |
124 | SPD_VAL(0x00, 0x00), /* 07 */ | |
125 | SPD_VAL(0x05, 0x05), /* 08 */ | |
126 | SPD_VAL(0x30, 0x30), /* 09 */ | |
127 | SPD_VAL(0x45, 0x45), /* 10 */ | |
128 | SPD_VAL(0x02, 0x02), /* 11 ecc used */ | |
129 | SPD_VAL(0x82, 0x82), /* 12 */ | |
130 | SPD_VAL(0x10, 0x10), /* 13 */ | |
131 | SPD_VAL(0x08, 0x08), /* 14 */ | |
132 | SPD_VAL(0x00, 0x00), /* 15 */ | |
133 | SPD_VAL(0x0c, 0x0c), /* 16 */ | |
134 | SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */ | |
135 | SPD_VAL(0x38, 0x38), /* 18 */ | |
136 | SPD_VAL(0x00, 0x00), /* 19 */ | |
137 | SPD_VAL(0x02, 0x02), /* 20 */ | |
138 | SPD_VAL(0x00, 0x00), /* 21 */ | |
139 | SPD_VAL(0x03, 0x03), /* 22 */ | |
140 | SPD_VAL(0x3d, 0x3d), /* 23 */ | |
141 | SPD_VAL(0x45, 0x45), /* 24 */ | |
142 | SPD_VAL(0x50, 0x50), /* 25 */ | |
143 | SPD_VAL(0x45, 0x45), /* 26 */ | |
144 | SPD_VAL(0x3c, 0x3c), /* 27 */ | |
145 | SPD_VAL(0x28, 0x28), /* 28 */ | |
146 | SPD_VAL(0x3c, 0x3c), /* 29 */ | |
147 | SPD_VAL(0x2d, 0x2d), /* 30 */ | |
148 | SPD_VAL(0x20, 0x80), /* 31 */ | |
149 | SPD_VAL(0x20, 0x20), /* 32 */ | |
150 | SPD_VAL(0x27, 0x27), /* 33 */ | |
151 | SPD_VAL(0x10, 0x10), /* 34 */ | |
152 | SPD_VAL(0x17, 0x17), /* 35 */ | |
153 | SPD_VAL(0x3c, 0x3c), /* 36 */ | |
154 | SPD_VAL(0x1e, 0x1e), /* 37 */ | |
155 | SPD_VAL(0x1e, 0x1e), /* 38 */ | |
156 | SPD_VAL(0x00, 0x00), /* 39 */ | |
157 | SPD_VAL(0x00, 0x06), /* 40 */ | |
158 | SPD_VAL(0x37, 0x37), /* 41 */ | |
159 | SPD_VAL(0x4b, 0x7f), /* 42 */ | |
160 | SPD_VAL(0x80, 0x80), /* 43 */ | |
161 | SPD_VAL(0x18, 0x18), /* 44 */ | |
162 | SPD_VAL(0x22, 0x22), /* 45 */ | |
163 | SPD_VAL(0x00, 0x00), /* 46 */ | |
164 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
165 | SPD_VAL(0x10, 0x10), /* 62 */ | |
166 | SPD_VAL(0x7e, 0x1d), /* 63 */ | |
167 | { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, | |
168 | SPD_VAL(0x00, 0x00), /* 72 */ | |
169 | #ifdef VME_CADDY2 | |
170 | { "vme-caddy/2 ram " } | |
171 | #else | |
172 | { "vme-cpu/2 ram " } | |
173 | #endif | |
174 | }; | |
175 | ||
176 | int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len) | |
177 | { | |
00f792e0 | 178 | int old_bus = i2c_get_bus_num(); |
1dee9be6 RA |
179 | unsigned int l, sum; |
180 | int valid = 0; | |
181 | ||
00f792e0 | 182 | i2c_set_bus_num(0); |
1dee9be6 RA |
183 | |
184 | if (i2c_read(chip, addr, alen, buffer, len) == 0) | |
185 | if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) { | |
186 | sum = 0; | |
187 | for (l = 0; l < 63; l++) | |
188 | sum = (sum + buffer[l]) & 0xff; | |
189 | if (sum == buffer[63]) | |
190 | valid = 1; | |
191 | else | |
192 | printf("Invalid checksum in EEPROM %02x %02x\n", | |
193 | sum, buffer[63]); | |
194 | } | |
195 | ||
196 | if (valid == 0) { | |
197 | memcpy(buffer, (void *)&default_spd_eeprom, len); | |
198 | sum = 0; | |
199 | for (l = 0; l < 63; l++) | |
200 | sum = (sum + buffer[l]) & 0xff; | |
201 | if (sum != buffer[63]) | |
202 | printf("Invalid checksum in FLASH %02x %02x\n", | |
203 | sum, buffer[63]); | |
204 | buffer[63] = sum; | |
205 | } | |
206 | ||
00f792e0 | 207 | i2c_set_bus_num(old_bus); |
1dee9be6 RA |
208 | |
209 | return 0; | |
210 | } |