[people/ms/u-boot.git] / board / esd / voh405 / voh405.c

/*
 * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

/* ------------------------------------------------------------------------- */

#if 0
#define FPGA_DEBUG
#endif

extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);

/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);


/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp_320[] =
{
#include "logo_320_240_4bpp.c"
};

unsigned char logo_bmp_640[] =
{
#include "logo_640_480_24bpp.c"
};


/*
 * include common lcd code (for esd boards)
 */
#include "../common/lcd.c"

#include "../common/s1d13704_320_240_4bpp.h"
#include "../common/s1d13806_320_240_4bpp.h"
#include "../common/s1d13806_640_480_16bpp.h"


int board_early_init_f (void)
{
	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFFB5);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
	mtebc (epcr, 0xa8400000); /* ebc always driven */

	return 0;
}


int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
	volatile unsigned short *lcd_contrast =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
	volatile unsigned short *lcd_backlight =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	char *str;

	dst = malloc(CFG_FPGA_MAX_SIZE);
	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_INIT pin
	 */
	out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT);  /* reset low */
	udelay(1000); /* wait 1ms */
	out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT);   /* reset high */
	udelay(1000); /* wait 1ms */

	/*
	 * Reset external DUARTs
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
	udelay(10); /* wait 10us */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
	udelay(1000); /* wait 1ms */

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;

	/*
	 * Init lcd interface and display logo
	 */
	str = getenv("bd_type");
	if (strcmp(str, "voh405_bw") == 0) {
		lcd_setup(0, 1);
		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
			 regs_13704_320_240_4bpp,
			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
			 logo_bmp_320, sizeof(logo_bmp_320));
	} else if (strcmp(str, "voh405_bwbw") == 0) {
		lcd_setup(0, 1);
		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
			 regs_13704_320_240_4bpp,
			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
			 logo_bmp_320, sizeof(logo_bmp_320));
		lcd_setup(1, 1);
		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
			 regs_13806_320_240_4bpp,
			 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
			 logo_bmp_320, sizeof(logo_bmp_320));
	} else if (strcmp(str, "voh405_bwc") == 0) {
		lcd_setup(0, 1);
		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
			 regs_13704_320_240_4bpp,
			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
			 logo_bmp_320, sizeof(logo_bmp_320));
		lcd_setup(1, 0);
		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
			 regs_13806_640_480_16bpp,
			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
			 logo_bmp_640, sizeof(logo_bmp_640));
	} else {
		printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
		return 0;
	}

	/*
	 * Set invert bit in small lcd controller
	 */
	*(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;

	/*
	 * Set default contrast voltage on epson vga controller
	 */
	*lcd_contrast = 0x4646;

	/*
	 * Enable backlight
	 */
	*lcd_backlight = 0xffff;

	return (0);
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming VOH405");
	} else {
		puts(str);
	}

	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
		printf(" (%s)", str);
	} else {
		puts(" (Missing bd_type!)");
	}

	putc ('\n');

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
	volatile unsigned short *fpga_mode =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);

	/*
	 * Assert or deassert CompactFlash Reset Pin
	 */
	if (on) {		/* assert RESET */
		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
	} else {		/* release RESET */
		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
	}
}
#endif /* CONFIG_IDE_RESET */
Commit	Line	Data
22a40b0a	1	/*
cd5396fa	2	* (C) Copyright 2001-2004
22a40b0a SR	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <malloc.h>
	28
	29	/* ------------------------------------------------------------------------- */
	30
	31	#if 0
	32	#define FPGA_DEBUG
	33	#endif
	34
	35	extern int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[]);
cd5396fa	36	extern void lxt971_no_sleep(void);
22a40b0a SR	37
	38	/* fpga configuration data - gzip compressed and generated by bin2c */
	39	const unsigned char fpgadata[] =
	40	{
	41	#include "fpgadata.c"
	42	};
	43
	44	/*
	45	* include common fpga code (for esd boards)
	46	*/
	47	#include "../common/fpga.c"
	48
	49
	50	/* Prototypes */
eedcd078	51	int gunzip(void , int, unsigned char , unsigned long *);
22a40b0a SR	52
22a40b0a SR	53
cd5396fa SR	54	/* logo bitmap data - gzip compressed and generated by bin2c */
	55	unsigned char logo_bmp_320[] =
	56	{
	57	#include "logo_320_240_4bpp.c"
	58	};
	59
	60	unsigned char logo_bmp_640[] =
	61	{
	62	#include "logo_640_480_24bpp.c"
	63	};
	64
	65
	66	/*
	67	* include common lcd code (for esd boards)
	68	*/
	69	#include "../common/lcd.c"
	70
	71	#include "../common/s1d13704_320_240_4bpp.h"
	72	#include "../common/s1d13806_320_240_4bpp.h"
	73	#include "../common/s1d13806_640_480_16bpp.h"
	74
	75
c837dcb1	76	int board_early_init_f (void)
22a40b0a SR	77	{
	78	/*
	79	* IRQ 0-15 405GP internally generated; active high; level sensitive
	80	* IRQ 16 405GP internally generated; active low; level sensitive
	81	* IRQ 17-24 RESERVED
	82	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	83	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	84	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	85	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	86	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	87	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	88	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	89	*/
	90	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	91	mtdcr(uicer, 0x00000000); /* disable all ints */
	92	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
	93	mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */
	94	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	95	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	96	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	97
	98	/*
	99	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	100	*/
	101	mtebc (epcr, 0xa8400000); /* ebc always driven */
	102
	103	return 0;
	104	}
	105
	106
22a40b0a SR	107	int misc_init_f (void)
	108	{
	109	return 0; /* dummy implementation */
	110	}
	111
	112
	113	int misc_init_r (void)
	114	{
	115	volatile unsigned char duart0_mcr = (unsigned char )((ulong)DUART0_BA + 4);
	116	volatile unsigned char duart1_mcr = (unsigned char )((ulong)DUART1_BA + 4);
cd5396fa	117	volatile unsigned short *lcd_contrast =
22a40b0a	118	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
cd5396fa SR	119	volatile unsigned short *lcd_backlight =
cd5396fa SR	120	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
22a40b0a SR	121	unsigned char *dst;
	122	ulong len = sizeof(fpgadata);
	123	int status;
	124	int index;
	125	int i;
cd5396fa	126	char *str;
22a40b0a SR	127
22a40b0a SR	128	dst = malloc(CFG_FPGA_MAX_SIZE);
eedcd078	129	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
22a40b0a SR	130	printf ("GUNZIP ERROR - must RESET board to recover\n");
	131	do_reset (NULL, 0, 0, NULL);
	132	}
	133
	134	status = fpga_boot(dst, len);
	135	if (status != 0) {
	136	printf("\nFPGA: Booting failed ");
	137	switch (status) {
	138	case ERROR_FPGA_PRG_INIT_LOW:
	139	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	140	break;
	141	case ERROR_FPGA_PRG_INIT_HIGH:
	142	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	143	break;
	144	case ERROR_FPGA_PRG_DONE:
	145	printf("(Timeout: DONE not high after programming FPGA)\n ");
	146	break;
	147	}
	148
	149	/* display infos on fpgaimage */
	150	index = 15;
	151	for (i=0; i<4; i++) {
	152	len = dst[index];
	153	printf("FPGA: %s\n", &(dst[index+1]));
	154	index += len+3;
	155	}
	156	putc ('\n');
	157	/* delayed reboot */
	158	for (i=20; i>0; i--) {
	159	printf("Rebooting in %2d seconds \r",i);
	160	for (index=0;index<1000;index++)
	161	udelay(1000);
	162	}
	163	putc ('\n');
	164	do_reset(NULL, 0, 0, NULL);
	165	}
	166
	167	puts("FPGA: ");
	168
	169	/* display infos on fpgaimage */
	170	index = 15;
	171	for (i=0; i<4; i++) {
	172	len = dst[index];
	173	printf("%s ", &(dst[index+1]));
	174	index += len+3;
	175	}
	176	putc ('\n');
	177
	178	free(dst);
	179
	180	/*
cd5396fa	181	* Reset FPGA via FPGA_INIT pin
22a40b0a	182	*/
cd5396fa SR	183	out32(GPIO0_TCR, in32(GPIO0_TCR) \| FPGA_INIT); /* setup FPGA_INIT as output */
cd5396fa SR	184	out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
22a40b0a	185	udelay(1000); /* wait 1ms */
cd5396fa	186	out32(GPIO0_OR, in32(GPIO0_OR) \| FPGA_INIT); /* reset high */
22a40b0a SR	187	udelay(1000); /* wait 1ms */
	188
	189	/*
	190	* Reset external DUARTs
	191	*/
	192	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_DUART_RST); /* set reset to high */
	193	udelay(10); /* wait 10us */
	194	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
	195	udelay(1000); /* wait 1ms */
	196
22a40b0a SR	197	/*
	198	* Enable interrupts in exar duart mcr[3]
	199	*/
	200	*duart0_mcr = 0x08;
	201	*duart1_mcr = 0x08;
	202
cd5396fa SR	203	/*
	204	* Init lcd interface and display logo
	205	*/
	206	str = getenv("bd_type");
	207	if (strcmp(str, "voh405_bw") == 0) {
	208	lcd_setup(0, 1);
	209	lcd_init((uchar )CFG_LCD_SMALL_REG, (uchar )CFG_LCD_SMALL_MEM,
	210	regs_13704_320_240_4bpp,
	211	sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
	212	logo_bmp_320, sizeof(logo_bmp_320));
	213	} else if (strcmp(str, "voh405_bwbw") == 0) {
	214	lcd_setup(0, 1);
	215	lcd_init((uchar )CFG_LCD_SMALL_REG, (uchar )CFG_LCD_SMALL_MEM,
	216	regs_13704_320_240_4bpp,
	217	sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
	218	logo_bmp_320, sizeof(logo_bmp_320));
	219	lcd_setup(1, 1);
	220	lcd_init((uchar )CFG_LCD_BIG_REG, (uchar )CFG_LCD_BIG_MEM,
	221	regs_13806_320_240_4bpp,
	222	sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
	223	logo_bmp_320, sizeof(logo_bmp_320));
	224	} else if (strcmp(str, "voh405_bwc") == 0) {
	225	lcd_setup(0, 1);
	226	lcd_init((uchar )CFG_LCD_SMALL_REG, (uchar )CFG_LCD_SMALL_MEM,
	227	regs_13704_320_240_4bpp,
	228	sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
	229	logo_bmp_320, sizeof(logo_bmp_320));
	230	lcd_setup(1, 0);
	231	lcd_init((uchar )CFG_LCD_BIG_REG, (uchar )CFG_LCD_BIG_MEM,
	232	regs_13806_640_480_16bpp,
	233	sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
	234	logo_bmp_640, sizeof(logo_bmp_640));
	235	} else {
	236	printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
	237	return 0;
	238	}
	239
	240	/*
	241	* Set invert bit in small lcd controller
	242	*/
	243	(unsigned char )(CFG_LCD_SMALL_REG + 2) \|= 0x01;
	244
22a40b0a SR	245	/*
	246	* Set default contrast voltage on epson vga controller
	247	*/
cd5396fa SR	248	*lcd_contrast = 0x4646;
	249
	250	/*
	251	* Enable backlight
	252	*/
	253	*lcd_backlight = 0xffff;
22a40b0a SR	254
	255	return (0);
	256	}
	257
	258
	259	/*
	260	* Check Board Identity:
	261	*/
	262
	263	int checkboard (void)
	264	{
77ddac94	265	char str[64];
22a40b0a SR	266	int i = getenv_r ("serial#", str, sizeof(str));
	267
	268	puts ("Board: ");
	269
	270	if (i == -1) {
	271	puts ("### No HW ID - assuming VOH405");
	272	} else {
	273	puts(str);
	274	}
	275
cd5396fa SR	276	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
	277	printf(" (%s)", str);
	278	} else {
	279	puts(" (Missing bd_type!)");
	280	}
	281
22a40b0a SR	282	putc ('\n');
22a40b0a SR	283
cd5396fa SR	284	/*
	285	* Disable sleep mode in LXT971
	286	*/
	287	lxt971_no_sleep();
	288
22a40b0a SR	289	return 0;
	290	}
	291
	292	/* ------------------------------------------------------------------------- */
	293
	294	long int initdram (int board_type)
	295	{
	296	unsigned long val;
	297
	298	mtdcr(memcfga, mem_mb0cf);
	299	val = mfdcr(memcfgd);
	300
	301	#if 0
	302	printf("\nmb0cf=%x\n", val); /* test-only */
	303	printf("strap=%x\n", mfdcr(strap)); /* test-only */
	304	#endif
	305
	306	return (410241024 << ((val & 0x000e0000) >> 17));
	307	}
	308
	309	/* ------------------------------------------------------------------------- */
	310
	311	int testdram (void)
	312	{
	313	/* TODO: XXX XXX XXX */
	314	printf ("test: 16 MB - ok\n");
	315
	316	return (0);
	317	}
	318
	319	/* ------------------------------------------------------------------------- */
	320
	321	#ifdef CONFIG_IDE_RESET
	322	void ide_set_reset(int on)
	323	{
	324	volatile unsigned short *fpga_mode =
	325	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
	326
	327	/*
	328	* Assert or deassert CompactFlash Reset Pin
	329	*/
	330	if (on) { /* assert RESET */
	331	*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
	332	} else { /* release RESET */
	333	*fpga_mode \|= CFG_FPGA_CTRL_CF_RESET;
	334	}
	335	}
	336	#endif /* CONFIG_IDE_RESET */