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23b80982 TR |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
23b80982 TR |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * Ilko Iliev <www.ronetix.at> | |
6 | * | |
95d50e5c | 7 | * (C) Copyright 2009-2011 |
23b80982 TR |
8 | * Eric Benard <eric@eukrea.com> |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
23b80982 TR |
11 | */ |
12 | ||
13 | #include <common.h> | |
95d50e5c | 14 | #include <asm/io.h> |
23b80982 | 15 | #include <asm/arch/at91sam9260.h> |
23b80982 TR |
16 | #include <asm/arch/at91sam9_smc.h> |
17 | #include <asm/arch/at91_common.h> | |
95d50e5c | 18 | #include <asm/arch/at91_matrix.h> |
23b80982 TR |
19 | #include <asm/arch/at91_pmc.h> |
20 | #include <asm/arch/at91_rstc.h> | |
c2b2a07e EB |
21 | #include <asm/arch/at91_pio.h> |
22 | #include <asm/arch/clk.h> | |
23b80982 TR |
23 | #include <asm/arch/hardware.h> |
24 | #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) | |
25 | #include <net.h> | |
26 | #endif | |
27 | #include <netdev.h> | |
28 | ||
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | /* ------------------------------------------------------------------------- */ | |
32 | /* | |
33 | * Miscelaneous platform dependent initialisations | |
34 | */ | |
35 | ||
36 | #ifdef CONFIG_CMD_NAND | |
37 | static void cpu9260_nand_hw_init(void) | |
38 | { | |
39 | unsigned long csa; | |
95d50e5c EB |
40 | at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC; |
41 | at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; | |
42 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; | |
23b80982 TR |
43 | |
44 | /* Enable CS3 */ | |
c2b2a07e EB |
45 | csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; |
46 | writel(csa, &matrix->csa); | |
23b80982 TR |
47 | |
48 | /* Configure SMC CS3 for NAND/SmartMedia */ | |
49 | #if defined(CONFIG_CPU9G20) | |
c2b2a07e EB |
50 | writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | |
51 | AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), | |
52 | &smc->cs[3].setup); | |
53 | writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | | |
54 | AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), | |
55 | &smc->cs[3].pulse); | |
56 | writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), | |
57 | &smc->cs[3].cycle); | |
58 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | | |
59 | AT91_SMC_MODE_EXNW_DISABLE | | |
60 | AT91_SMC_MODE_DBW_8 | | |
61 | AT91_SMC_MODE_TDF_CYCLE(3), | |
62 | &smc->cs[3].mode); | |
23b80982 | 63 | #elif defined(CONFIG_CPU9260) |
c2b2a07e EB |
64 | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | |
65 | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), | |
66 | &smc->cs[3].setup); | |
67 | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | | |
68 | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), | |
69 | &smc->cs[3].pulse); | |
70 | writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), | |
71 | &smc->cs[3].cycle); | |
72 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | | |
73 | AT91_SMC_MODE_EXNW_DISABLE | | |
74 | AT91_SMC_MODE_DBW_8 | | |
75 | AT91_SMC_MODE_TDF_CYCLE(2), | |
76 | &smc->cs[3].mode); | |
23b80982 TR |
77 | #endif |
78 | ||
95d50e5c | 79 | writel(1 << ATMEL_ID_PIOC, &pmc->pcer); |
23b80982 TR |
80 | |
81 | /* Configure RDY/BSY */ | |
c2b2a07e | 82 | at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); |
23b80982 TR |
83 | |
84 | /* Enable NandFlash */ | |
c2b2a07e | 85 | at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); |
23b80982 TR |
86 | } |
87 | #endif | |
88 | ||
89 | #ifdef CONFIG_MACB | |
90 | static void cpu9260_macb_hw_init(void) | |
91 | { | |
c2b2a07e | 92 | unsigned long rstcmr; |
95d50e5c EB |
93 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
94 | at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; | |
23b80982 TR |
95 | |
96 | /* Enable clock */ | |
95d50e5c | 97 | writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); |
c2b2a07e EB |
98 | |
99 | at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); | |
100 | ||
101 | rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; | |
23b80982 TR |
102 | |
103 | /* Need to reset PHY -> 500ms reset */ | |
c2b2a07e EB |
104 | writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) | |
105 | AT91_RSTC_MR_URSTEN, &rstc->mr); | |
23b80982 | 106 | |
c2b2a07e | 107 | writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); |
23b80982 TR |
108 | |
109 | /* Wait for end hardware reset */ | |
c2b2a07e | 110 | while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) |
23b80982 TR |
111 | ; |
112 | ||
113 | /* Restore NRST value */ | |
c2b2a07e | 114 | writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr); |
23b80982 TR |
115 | |
116 | at91_macb_hw_init(); | |
117 | } | |
118 | #endif | |
119 | ||
c2b2a07e | 120 | int board_early_init_f(void) |
23b80982 | 121 | { |
95d50e5c | 122 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
c2b2a07e | 123 | |
95d50e5c EB |
124 | writel((1 << ATMEL_ID_PIOA) | |
125 | (1 << ATMEL_ID_PIOB) | | |
126 | (1 << ATMEL_ID_PIOC), | |
c2b2a07e EB |
127 | &pmc->pcer); |
128 | ||
95d50e5c | 129 | at91_seriald_hw_init(); |
c2b2a07e EB |
130 | |
131 | return 0; | |
132 | } | |
23b80982 | 133 | |
c2b2a07e EB |
134 | |
135 | int board_init(void) | |
136 | { | |
23b80982 TR |
137 | /* arch number of the board */ |
138 | #if defined(CONFIG_CPU9G20) | |
94d50c52 | 139 | gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20; |
23b80982 TR |
140 | #elif defined(CONFIG_CPU9260) |
141 | gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260; | |
142 | #endif | |
143 | ||
144 | /* adress of boot parameters */ | |
c2b2a07e | 145 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
23b80982 | 146 | |
23b80982 TR |
147 | #ifdef CONFIG_CMD_NAND |
148 | cpu9260_nand_hw_init(); | |
149 | #endif | |
150 | #ifdef CONFIG_MACB | |
151 | cpu9260_macb_hw_init(); | |
152 | #endif | |
153 | #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) | |
154 | status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); | |
155 | #endif | |
156 | return 0; | |
157 | } | |
158 | ||
159 | int dram_init(void) | |
160 | { | |
a55d23cc | 161 | gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, |
c2b2a07e | 162 | CONFIG_SYS_SDRAM_SIZE); |
23b80982 TR |
163 | return 0; |
164 | } | |
165 | ||
23b80982 TR |
166 | int board_eth_init(bd_t *bis) |
167 | { | |
168 | int rc = 0; | |
169 | #ifdef CONFIG_MACB | |
95d50e5c | 170 | rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0); |
23b80982 TR |
171 | #endif |
172 | return rc; | |
173 | } |