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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* sdram_init.c - automatic memory sizing */ | |
9 | ||
10 | #include <common.h> | |
11 | #include <74xx_7xx.h> | |
12 | #include <galileo/memory.h> | |
13 | #include <galileo/pci.h> | |
14 | #include <galileo/gt64260R.h> | |
15 | #include <net.h> | |
b191c701 | 16 | #include <linux/compiler.h> |
c609719b WD |
17 | |
18 | #include "eth.h" | |
19 | #include "mpsc.h" | |
20 | #include "i2c.h" | |
21 | #include "64260.h" | |
22 | ||
d87080b7 WD |
23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
c609719b WD |
25 | /* #define DEBUG */ |
26 | #define MAP_PCI | |
27 | ||
28 | #ifdef DEBUG | |
29 | #define DP(x) x | |
30 | #else | |
31 | #define DP(x) | |
32 | #endif | |
33 | ||
34 | #define GB (1 << 30) | |
35 | ||
36 | /* structure to store the relevant information about an sdram bank */ | |
37 | typedef struct sdram_info { | |
38 | uchar drb_size; | |
39 | uchar registered, ecc; | |
40 | uchar tpar; | |
41 | uchar tras_clocks; | |
42 | uchar burst_len; | |
43 | uchar banks, slot; | |
bf9e3b38 | 44 | int size; /* detected size, not from I2C but from dram_size() */ |
c609719b WD |
45 | } sdram_info_t; |
46 | ||
47 | #ifdef DEBUG | |
bf9e3b38 | 48 | void dump_dimm_info (struct sdram_info *d) |
c609719b | 49 | { |
bf9e3b38 WD |
50 | static const char *ecc_legend[] = { "", " Parity", " ECC" }; |
51 | ||
52 | printf ("dimm%s %sDRAM: %dMibytes:\n", | |
53 | ecc_legend[d->ecc], | |
54 | d->registered ? "R" : "", (d->size >> 20)); | |
55 | printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n", | |
56 | d->drb_size, d->tpar, d->tras_clocks, d->burst_len, | |
57 | d->banks, d->slot); | |
c609719b WD |
58 | } |
59 | #endif | |
60 | ||
61 | static int | |
bf9e3b38 WD |
62 | memory_map_bank (unsigned int bankNo, |
63 | unsigned int bankBase, unsigned int bankLength) | |
c609719b WD |
64 | { |
65 | #ifdef DEBUG | |
66 | if (bankLength > 0) { | |
bf9e3b38 WD |
67 | printf ("mapping bank %d at %08x - %08x\n", |
68 | bankNo, bankBase, bankBase + bankLength - 1); | |
c609719b | 69 | } else { |
bf9e3b38 | 70 | printf ("unmapping bank %d\n", bankNo); |
c609719b WD |
71 | } |
72 | #endif | |
73 | ||
bf9e3b38 | 74 | memoryMapBank (bankNo, bankBase, bankLength); |
c609719b WD |
75 | |
76 | return 0; | |
77 | } | |
78 | ||
79 | #ifdef MAP_PCI | |
80 | static int | |
bf9e3b38 WD |
81 | memory_map_bank_pci (unsigned int bankNo, |
82 | unsigned int bankBase, unsigned int bankLength) | |
c609719b WD |
83 | { |
84 | PCI_HOST host; | |
bf9e3b38 WD |
85 | |
86 | for (host = PCI_HOST0; host <= PCI_HOST1; host++) { | |
87 | const int features = | |
c609719b WD |
88 | PREFETCH_ENABLE | |
89 | DELAYED_READ_ENABLE | | |
90 | AGGRESSIVE_PREFETCH | | |
91 | READ_LINE_AGGRESSIVE_PREFETCH | | |
92 | READ_MULTI_AGGRESSIVE_PREFETCH | | |
bf9e3b38 | 93 | MAX_BURST_4 | PCI_NO_SWAP; |
c609719b | 94 | |
bf9e3b38 | 95 | pciMapMemoryBank (host, bankNo, bankBase, bankLength); |
c609719b | 96 | |
bf9e3b38 WD |
97 | pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, |
98 | bankLength); | |
c609719b | 99 | |
bf9e3b38 WD |
100 | pciSetRegionFeatures (host, bankNo, features, bankBase, |
101 | bankLength); | |
c609719b WD |
102 | } |
103 | return 0; | |
104 | } | |
105 | #endif | |
106 | ||
107 | /* ------------------------------------------------------------------------- */ | |
108 | ||
109 | /* much of this code is based on (or is) the code in the pip405 port */ | |
110 | /* thanks go to the authors of said port - Josh */ | |
111 | ||
112 | ||
113 | /* | |
114 | * translate ns.ns/10 coding of SPD timing values | |
115 | * into 10 ps unit values | |
116 | */ | |
bf9e3b38 | 117 | static inline unsigned short NS10to10PS (unsigned char spd_byte) |
c609719b WD |
118 | { |
119 | unsigned short ns, ns10; | |
120 | ||
121 | /* isolate upper nibble */ | |
122 | ns = (spd_byte >> 4) & 0x0F; | |
123 | /* isolate lower nibble */ | |
124 | ns10 = (spd_byte & 0x0F); | |
125 | ||
bf9e3b38 | 126 | return (ns * 100 + ns10 * 10); |
c609719b WD |
127 | } |
128 | ||
129 | /* | |
130 | * translate ns coding of SPD timing values | |
131 | * into 10 ps unit values | |
132 | */ | |
bf9e3b38 | 133 | static inline unsigned short NSto10PS (unsigned char spd_byte) |
c609719b | 134 | { |
bf9e3b38 | 135 | return (spd_byte * 100); |
c609719b WD |
136 | } |
137 | ||
138 | #ifdef CONFIG_ZUMA_V2 | |
bf9e3b38 | 139 | static int check_dimm (uchar slot, sdram_info_t * info) |
c609719b | 140 | { |
8bde7f77 | 141 | /* assume 2 dimms, 2 banks each 256M - we dont have an |
c609719b WD |
142 | * dimm i2c so rely on the detection routines later */ |
143 | ||
bf9e3b38 | 144 | memset (info, 0, sizeof (*info)); |
c609719b WD |
145 | |
146 | info->slot = slot; | |
147 | info->banks = 2; /* Detect later */ | |
bf9e3b38 | 148 | info->registered = 0; |
c609719b WD |
149 | info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit |
150 | but doesn't matter, both do same | |
151 | thing in setup_sdram() */ | |
bf9e3b38 WD |
152 | info->tpar = 3; |
153 | info->tras_clocks = 5; | |
154 | info->burst_len = 4; | |
c609719b WD |
155 | #ifdef CONFIG_ECC |
156 | info->ecc = 0; /* Detect later */ | |
157 | #endif /* CONFIG_ECC */ | |
158 | return 0; | |
159 | } | |
160 | ||
12f34241 WD |
161 | #elif defined(CONFIG_P3G4) |
162 | ||
bf9e3b38 | 163 | static int check_dimm (uchar slot, sdram_info_t * info) |
12f34241 | 164 | { |
bf9e3b38 | 165 | memset (info, 0, sizeof (*info)); |
12f34241 WD |
166 | |
167 | if (slot) | |
168 | return 0; | |
169 | ||
170 | info->slot = slot; | |
171 | info->banks = 1; | |
172 | info->registered = 0; | |
173 | info->drb_size = 4; | |
174 | info->tpar = 3; | |
175 | info->tras_clocks = 6; | |
176 | info->burst_len = 4; | |
177 | #ifdef CONFIG_ECC | |
178 | info->ecc = 2; | |
179 | #endif | |
180 | return 0; | |
181 | } | |
182 | ||
bf9e3b38 | 183 | #else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */ |
c609719b WD |
184 | |
185 | /* This code reads the SPD chip on the sdram and populates | |
186 | * the array which is passed in with the relevant information */ | |
bf9e3b38 | 187 | static int check_dimm (uchar slot, sdram_info_t * info) |
c609719b | 188 | { |
c609719b WD |
189 | uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; |
190 | int ret; | |
191 | uchar rows, cols, sdram_banks, supp_cal, width, cal_val; | |
192 | ulong tmemclk; | |
193 | uchar trp_clocks, trcd_clocks; | |
194 | uchar data[128]; | |
195 | ||
196 | get_clocks (); | |
197 | ||
bf9e3b38 | 198 | tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */ |
c609719b WD |
199 | |
200 | #ifdef CONFIG_EVB64260_750CX | |
201 | if (0 != slot) { | |
bf9e3b38 WD |
202 | printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,"); |
203 | printf (" called with slot=%d insetad!\n", slot); | |
c609719b WD |
204 | return 0; |
205 | } | |
206 | #endif | |
bf9e3b38 | 207 | DP (puts ("before i2c read\n")); |
c609719b | 208 | |
bf9e3b38 | 209 | ret = i2c_read (addr, 0, 128, data, 0); |
c609719b | 210 | |
bf9e3b38 | 211 | DP (puts ("after i2c read\n")); |
c609719b WD |
212 | |
213 | /* zero all the values */ | |
bf9e3b38 | 214 | memset (info, 0, sizeof (*info)); |
c609719b WD |
215 | |
216 | if (ret) { | |
bf9e3b38 | 217 | DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); |
c609719b WD |
218 | return 0; |
219 | } | |
220 | ||
221 | /* first, do some sanity checks */ | |
222 | if (data[2] != 0x4) { | |
bf9e3b38 | 223 | printf ("Not SDRAM in slot %d\n", slot); |
c609719b WD |
224 | return 0; |
225 | } | |
226 | ||
227 | /* get various information */ | |
228 | rows = data[3]; | |
229 | cols = data[4]; | |
230 | info->banks = data[5]; | |
231 | sdram_banks = data[17]; | |
232 | width = data[13] & 0x7f; | |
233 | ||
bf9e3b38 WD |
234 | DP (printf |
235 | ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); | |
c609719b WD |
236 | |
237 | /* check if the memory is registered */ | |
238 | if (data[21] & (BIT1 | BIT4)) | |
239 | info->registered = 1; | |
240 | ||
241 | #ifdef CONFIG_ECC | |
242 | /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ | |
243 | info->ecc = (data[11] & 2) >> 1; | |
244 | #endif | |
245 | ||
246 | /* bit 1 is CL2, bit 2 is CL3 */ | |
247 | supp_cal = (data[18] & 0x6) >> 1; | |
248 | ||
249 | /* compute the relevant clock values */ | |
bf9e3b38 WD |
250 | trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk; |
251 | trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk; | |
252 | info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk; | |
c609719b | 253 | |
bf9e3b38 WD |
254 | DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", |
255 | trp_clocks, trcd_clocks, info->tras_clocks)); | |
c609719b WD |
256 | |
257 | /* try a CAS latency of 3 first... */ | |
258 | cal_val = 0; | |
259 | if (supp_cal & 3) { | |
bf9e3b38 | 260 | if (NS10to10PS (data[9]) <= tmemclk) |
c609719b WD |
261 | cal_val = 3; |
262 | } | |
263 | ||
264 | /* then 2... */ | |
265 | if (supp_cal & 2) { | |
bf9e3b38 | 266 | if (NS10to10PS (data[23]) <= tmemclk) |
c609719b WD |
267 | cal_val = 2; |
268 | } | |
269 | ||
bf9e3b38 | 270 | DP (printf ("cal_val = %d\n", cal_val)); |
c609719b WD |
271 | |
272 | /* bummer, did't work... */ | |
273 | if (cal_val == 0) { | |
bf9e3b38 | 274 | DP (printf ("Couldn't find a good CAS latency\n")); |
c609719b WD |
275 | return 0; |
276 | } | |
277 | ||
278 | /* get the largest delay -- these values need to all be the same | |
279 | * see Res#6 */ | |
280 | info->tpar = cal_val; | |
281 | if (trp_clocks > info->tpar) | |
282 | info->tpar = trp_clocks; | |
283 | if (trcd_clocks > info->tpar) | |
284 | info->tpar = trcd_clocks; | |
285 | ||
bf9e3b38 | 286 | DP (printf ("tpar set to: %d\n", info->tpar)); |
c609719b | 287 | |
6d0f6bcf | 288 | #ifdef CONFIG_SYS_BROKEN_CL2 |
bf9e3b38 | 289 | if (info->tpar == 2) { |
c609719b | 290 | info->tpar = 3; |
bf9e3b38 | 291 | DP (printf ("tpar fixed-up to: %d\n", info->tpar)); |
c609719b WD |
292 | } |
293 | #endif | |
294 | /* compute the module DRB size */ | |
bf9e3b38 WD |
295 | info->drb_size = |
296 | (((1 << (rows + cols)) * sdram_banks) * width) / _16M; | |
c609719b | 297 | |
bf9e3b38 | 298 | DP (printf ("drb_size set to: %d\n", info->drb_size)); |
c609719b WD |
299 | |
300 | /* find the burst len */ | |
301 | info->burst_len = data[16] & 0xf; | |
302 | if ((info->burst_len & 8) == 8) { | |
303 | info->burst_len = 1; | |
304 | } else if ((info->burst_len & 4) == 4) { | |
305 | info->burst_len = 0; | |
306 | } else { | |
307 | return 0; | |
308 | } | |
309 | ||
310 | info->slot = slot; | |
311 | return 0; | |
312 | } | |
313 | #endif /* ! CONFIG_ZUMA_V2 */ | |
314 | ||
bf9e3b38 | 315 | static int setup_sdram_common (sdram_info_t info[2]) |
c609719b | 316 | { |
8bde7f77 | 317 | ulong tmp; |
b191c701 WD |
318 | int tpar = 2, tras_clocks = 5, registered = 1; |
319 | __maybe_unused int ecc = 2; | |
bf9e3b38 WD |
320 | |
321 | if (!info[0].banks && !info[1].banks) | |
322 | return 0; | |
323 | ||
324 | if (info[0].banks) { | |
325 | if (info[0].tpar > tpar) | |
326 | tpar = info[0].tpar; | |
327 | if (info[0].tras_clocks > tras_clocks) | |
328 | tras_clocks = info[0].tras_clocks; | |
329 | if (!info[0].registered) | |
330 | registered = 0; | |
3f85ce27 | 331 | if (info[0].ecc != 2) |
bf9e3b38 | 332 | ecc = 0; |
c609719b WD |
333 | } |
334 | ||
bf9e3b38 WD |
335 | if (info[1].banks) { |
336 | if (info[1].tpar > tpar) | |
337 | tpar = info[1].tpar; | |
338 | if (info[1].tras_clocks > tras_clocks) | |
339 | tras_clocks = info[1].tras_clocks; | |
340 | if (!info[1].registered) | |
341 | registered = 0; | |
342 | if (info[1].ecc != 2) | |
343 | ecc = 0; | |
c609719b WD |
344 | } |
345 | ||
346 | /* SDRAM configuration */ | |
bf9e3b38 | 347 | tmp = GTREGREAD (SDRAM_CONFIGURATION); |
c609719b WD |
348 | |
349 | /* Turn on physical interleave if both DIMMs | |
350 | * have even numbers of banks. */ | |
bf9e3b38 WD |
351 | if ((info[0].banks == 0 || info[0].banks == 2) && |
352 | (info[1].banks == 0 || info[1].banks == 2)) { | |
353 | /* physical interleave on */ | |
354 | tmp &= ~(1 << 15); | |
c609719b | 355 | } else { |
bf9e3b38 WD |
356 | /* physical interleave off */ |
357 | tmp |= (1 << 15); | |
c609719b WD |
358 | } |
359 | ||
360 | tmp |= (registered << 17); | |
361 | ||
362 | /* Use buffer 1 to return read data to the CPU | |
363 | * See Res #12 */ | |
364 | tmp |= (1 << 26); | |
365 | ||
bf9e3b38 WD |
366 | GT_REG_WRITE (SDRAM_CONFIGURATION, tmp); |
367 | DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION))); | |
c609719b WD |
368 | |
369 | /* SDRAM timing */ | |
370 | tmp = (((tpar == 3) ? 2 : 1) | | |
371 | (((tpar == 3) ? 2 : 1) << 2) | | |
bf9e3b38 | 372 | (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8)); |
c609719b WD |
373 | |
374 | #ifdef CONFIG_ECC | |
375 | /* Setup ECC */ | |
bf9e3b38 WD |
376 | if (ecc == 2) |
377 | tmp |= 1 << 13; | |
c609719b WD |
378 | #endif /* CONFIG_ECC */ |
379 | ||
bf9e3b38 WD |
380 | GT_REG_WRITE (SDRAM_TIMING, tmp); |
381 | DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n", | |
382 | GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks)); | |
c609719b WD |
383 | |
384 | /* SDRAM address decode register */ | |
385 | /* program this with the default value */ | |
bf9e3b38 WD |
386 | GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2); |
387 | DP (printf ("SDRAM decode: %08x\n", | |
388 | GTREGREAD (SDRAM_ADDRESS_DECODE))); | |
c609719b WD |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
393 | /* sets up the GT properly with information passed in */ | |
bf9e3b38 | 394 | static int setup_sdram (sdram_info_t * info) |
c609719b | 395 | { |
b191c701 | 396 | ulong tmp; |
c609719b | 397 | ulong *addr = 0; |
b191c701 | 398 | __maybe_unused ulong check; |
c609719b WD |
399 | int i; |
400 | ||
401 | /* sanity checking */ | |
bf9e3b38 WD |
402 | if (!info->banks) |
403 | return 0; | |
c609719b WD |
404 | |
405 | /* ---------------------------- */ | |
406 | /* Program the GT with the discovered data */ | |
407 | ||
408 | /* bank parameters */ | |
bf9e3b38 | 409 | tmp = (0xf << 16); /* leave all virt bank pages open */ |
c609719b | 410 | |
bf9e3b38 | 411 | DP (printf ("drb_size: %d\n", info->drb_size)); |
c609719b WD |
412 | switch (info->drb_size) { |
413 | case 1: | |
414 | tmp |= (1 << 14); | |
415 | break; | |
416 | case 4: | |
417 | case 8: | |
418 | tmp |= (2 << 14); | |
419 | break; | |
420 | case 16: | |
421 | case 32: | |
422 | tmp |= (3 << 14); | |
423 | break; | |
424 | default: | |
bf9e3b38 | 425 | printf ("Error in dram size calculation\n"); |
c609719b WD |
426 | return 1; |
427 | } | |
428 | ||
429 | /* SDRAM bank parameters */ | |
430 | /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ | |
bf9e3b38 WD |
431 | GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); |
432 | GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); | |
433 | DP (printf | |
434 | ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, | |
435 | info->slot * 2, (info->slot * 2) + 1, tmp)); | |
c609719b WD |
436 | |
437 | /* set the SDRAM configuration for each bank */ | |
438 | for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { | |
bf9e3b38 | 439 | DP (printf ("*** Running a MRS cycle for bank %d ***\n", i)); |
c609719b WD |
440 | |
441 | /* map the bank */ | |
bf9e3b38 | 442 | memory_map_bank (i, 0, GB / 4); |
c609719b WD |
443 | |
444 | /* set SDRAM mode */ | |
bf9e3b38 WD |
445 | GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3); |
446 | check = GTREGREAD (SDRAM_OPERATION_MODE); | |
c609719b WD |
447 | |
448 | /* dummy write */ | |
449 | *addr = 0; | |
450 | ||
451 | /* wait for the command to complete */ | |
bf9e3b38 | 452 | while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0); |
c609719b WD |
453 | |
454 | /* switch back to normal operation mode */ | |
bf9e3b38 WD |
455 | GT_REG_WRITE (SDRAM_OPERATION_MODE, 0); |
456 | check = GTREGREAD (SDRAM_OPERATION_MODE); | |
c609719b WD |
457 | |
458 | /* unmap the bank */ | |
bf9e3b38 WD |
459 | memory_map_bank (i, 0, 0); |
460 | DP (printf ("*** MRS cycle for bank %d done ***\n", i)); | |
c609719b WD |
461 | } |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | /* | |
467 | * Check memory range for valid RAM. A simple memory test determines | |
468 | * the actually available RAM size between addresses `base' and | |
469 | * `base + maxsize'. Some (not all) hardware errors are detected: | |
470 | * - short between address lines | |
471 | * - short between data lines | |
472 | */ | |
bf9e3b38 | 473 | static long int dram_size (long int *base, long int maxsize) |
c609719b | 474 | { |
bf9e3b38 WD |
475 | volatile long int *addr, *b = base; |
476 | long int cnt, val, save1, save2; | |
c609719b WD |
477 | |
478 | #define STARTVAL (1<<20) /* start test at 1M */ | |
bf9e3b38 WD |
479 | for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); |
480 | cnt <<= 1) { | |
481 | addr = base + cnt; /* pointer arith! */ | |
482 | ||
483 | save1 = *addr; /* save contents of addr */ | |
484 | save2 = *b; /* save contents of base */ | |
485 | ||
486 | *addr = cnt; /* write cnt to addr */ | |
487 | *b = 0; /* put null at base */ | |
488 | ||
489 | /* check at base address */ | |
490 | if ((*b) != 0) { | |
491 | *addr = save1; /* restore *addr */ | |
492 | *b = save2; /* restore *b */ | |
493 | return (0); | |
494 | } | |
495 | val = *addr; /* read *addr */ | |
496 | ||
497 | *addr = save1; | |
498 | *b = save2; | |
499 | ||
500 | if (val != cnt) { | |
501 | /* fix boundary condition.. STARTVAL means zero */ | |
502 | if (cnt == STARTVAL / sizeof (long)) | |
503 | cnt = 0; | |
504 | return (cnt * sizeof (long)); | |
505 | } | |
506 | } | |
507 | return maxsize; | |
c609719b WD |
508 | } |
509 | ||
510 | /* ------------------------------------------------------------------------- */ | |
511 | ||
512 | /* U-Boot interface function to SDRAM init - this is where all the | |
513 | * controlling logic happens */ | |
9973e3c6 | 514 | phys_size_t initdram (int board_type) |
c609719b | 515 | { |
bf9e3b38 | 516 | ulong checkbank[4] = {[0 ... 3] = 0 }; |
c609719b | 517 | int bank_no; |
8bde7f77 | 518 | ulong total; |
c609719b WD |
519 | int nhr; |
520 | sdram_info_t dimm_info[2]; | |
521 | ||
522 | ||
523 | /* first, use the SPD to get info about the SDRAM */ | |
524 | ||
525 | /* check the NHR bit and skip mem init if it's already done */ | |
bf9e3b38 | 526 | nhr = get_hid0 () & (1 << 16); |
c609719b WD |
527 | |
528 | if (nhr) { | |
bf9e3b38 | 529 | printf ("Skipping SDRAM setup due to NHR bit being set\n"); |
c609719b WD |
530 | } else { |
531 | /* DIMM0 */ | |
bf9e3b38 | 532 | check_dimm (0, &dimm_info[0]); |
c609719b WD |
533 | |
534 | /* DIMM1 */ | |
bf9e3b38 WD |
535 | #ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */ |
536 | check_dimm (1, &dimm_info[1]); | |
537 | #else /* CONFIG_EVB64260_750CX */ | |
538 | memset (&dimm_info[1], 0, sizeof (sdram_info_t)); | |
c609719b WD |
539 | #endif |
540 | ||
541 | /* unmap all banks */ | |
bf9e3b38 WD |
542 | memory_map_bank (0, 0, 0); |
543 | memory_map_bank (1, 0, 0); | |
544 | memory_map_bank (2, 0, 0); | |
545 | memory_map_bank (3, 0, 0); | |
c609719b WD |
546 | |
547 | /* Now, program the GT with the correct values */ | |
bf9e3b38 WD |
548 | if (setup_sdram_common (dimm_info)) { |
549 | printf ("Setup common failed.\n"); | |
c609719b WD |
550 | } |
551 | ||
bf9e3b38 WD |
552 | if (setup_sdram (&dimm_info[0])) { |
553 | printf ("Setup for DIMM1 failed.\n"); | |
c609719b WD |
554 | } |
555 | ||
bf9e3b38 WD |
556 | if (setup_sdram (&dimm_info[1])) { |
557 | printf ("Setup for DIMM2 failed.\n"); | |
c609719b WD |
558 | } |
559 | ||
560 | /* set the NHR bit */ | |
bf9e3b38 | 561 | set_hid0 (get_hid0 () | (1 << 16)); |
c609719b WD |
562 | } |
563 | /* next, size the SDRAM banks */ | |
564 | ||
565 | total = 0; | |
bf9e3b38 WD |
566 | if (dimm_info[0].banks > 0) |
567 | checkbank[0] = 1; | |
568 | if (dimm_info[0].banks > 1) | |
569 | checkbank[1] = 1; | |
c609719b | 570 | if (dimm_info[0].banks > 2) |
bf9e3b38 | 571 | printf ("Error, SPD claims DIMM1 has >2 banks\n"); |
c609719b | 572 | |
bf9e3b38 WD |
573 | if (dimm_info[1].banks > 0) |
574 | checkbank[2] = 1; | |
575 | if (dimm_info[1].banks > 1) | |
576 | checkbank[3] = 1; | |
c609719b | 577 | if (dimm_info[1].banks > 2) |
bf9e3b38 | 578 | printf ("Error, SPD claims DIMM2 has >2 banks\n"); |
c609719b WD |
579 | |
580 | /* Generic dram sizer: works even if we don't have i2c DIMMs, | |
581 | * as long as the timing settings are more or less correct */ | |
582 | ||
583 | /* | |
584 | * pass 1: size all the banks, using first bat (0-256M) | |
bf9e3b38 WD |
585 | * limitation: we only support 256M per bank due to |
586 | * us only having 1 BAT for all DRAM | |
c609719b | 587 | */ |
6d0f6bcf | 588 | for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { |
c609719b | 589 | /* skip over banks that are not populated */ |
bf9e3b38 | 590 | if (!checkbank[bank_no]) |
c609719b WD |
591 | continue; |
592 | ||
bf9e3b38 | 593 | DP (printf ("checking bank %d\n", bank_no)); |
c609719b | 594 | |
bf9e3b38 WD |
595 | memory_map_bank (bank_no, 0, GB / 4); |
596 | checkbank[bank_no] = dram_size (NULL, GB / 4); | |
597 | memory_map_bank (bank_no, 0, 0); | |
c609719b | 598 | |
bf9e3b38 | 599 | DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no])); |
c609719b WD |
600 | } |
601 | ||
602 | /* | |
603 | * pass 2: contiguously map each bank into physical address | |
bf9e3b38 | 604 | * space. |
c609719b | 605 | */ |
bf9e3b38 | 606 | dimm_info[0].banks = dimm_info[1].banks = 0; |
6d0f6bcf | 607 | for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { |
bf9e3b38 WD |
608 | if (!checkbank[bank_no]) |
609 | continue; | |
c609719b | 610 | |
bf9e3b38 WD |
611 | dimm_info[bank_no / 2].banks++; |
612 | dimm_info[bank_no / 2].size += checkbank[bank_no]; | |
c609719b | 613 | |
bf9e3b38 | 614 | memory_map_bank (bank_no, total, checkbank[bank_no]); |
c609719b | 615 | #ifdef MAP_PCI |
bf9e3b38 | 616 | memory_map_bank_pci (bank_no, total, checkbank[bank_no]); |
c609719b WD |
617 | #endif |
618 | total += checkbank[bank_no]; | |
619 | } | |
620 | ||
621 | #ifdef CONFIG_ECC | |
622 | #ifdef CONFIG_ZUMA_V2 | |
623 | /* | |
624 | * We always enable ECC when bank 2 and 3 are unpopulated | |
625 | * If we 2 or 3 are populated, we CAN'T support ECC. | |
626 | * (Zuma boards only support ECC in banks 0 and 1; assume that | |
627 | * in that configuration, ECC chips are mounted, even for stacked | |
628 | * chips) | |
629 | */ | |
bf9e3b38 WD |
630 | if (checkbank[2] == 0 && checkbank[3] == 0) { |
631 | dimm_info[0].ecc = 2; | |
632 | GT_REG_WRITE (SDRAM_TIMING, | |
633 | GTREGREAD (SDRAM_TIMING) | (1 << 13)); | |
c609719b WD |
634 | /* TODO: do we have to run MRS cycles again? */ |
635 | } | |
636 | #endif /* CONFIG_ZUMA_V2 */ | |
637 | ||
bf9e3b38 WD |
638 | if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) { |
639 | puts ("[ECC] "); | |
c609719b WD |
640 | } |
641 | #endif /* CONFIG_ECC */ | |
642 | ||
643 | #ifdef DEBUG | |
bf9e3b38 WD |
644 | dump_dimm_info (&dimm_info[0]); |
645 | dump_dimm_info (&dimm_info[1]); | |
c609719b WD |
646 | #endif |
647 | /* TODO: return at MOST 256M? */ | |
8bde7f77 | 648 | /* return total > GB/4 ? GB/4 : total; */ |
c609719b WD |
649 | return total; |
650 | } |