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b5b06fb7 YS |
1 | /* |
2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
b5b06fb7 YS |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/fsl_law.h> | |
9 | #include <asm/mmu.h> | |
10 | ||
11 | struct law_entry law_table[] = { | |
12 | SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), | |
13 | #ifdef CONFIG_SYS_BMAN_MEM_PHYS | |
14 | SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), | |
15 | #endif | |
16 | #ifdef CONFIG_SYS_QMAN_MEM_PHYS | |
17 | SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), | |
18 | #endif | |
19 | SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), | |
6eaeba23 SL |
20 | #ifdef CONFIG_SYS_MAPLE_MEM_PHYS |
21 | SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE), | |
22 | #endif | |
b5b06fb7 | 23 | #ifdef CONFIG_SYS_DCSRBAR_PHYS |
49e946cb SG |
24 | /* Limit DCSR to 32M to access NPC Trace Buffer */ |
25 | SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), | |
b5b06fb7 YS |
26 | #endif |
27 | #ifdef CONFIG_SYS_NAND_BASE_PHYS | |
28 | SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), | |
29 | #endif | |
30 | }; | |
31 | ||
32 | int num_law_entries = ARRAY_SIZE(law_table); |