[people/ms/u-boot.git] / board / freescale / b4860qds / spl.c

/* Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:    GPL-2.0+
 */

#include <common.h>
#include <console.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include "../common/qixis.h"
#include "b4860qds_qixis.h"

DECLARE_GLOBAL_DATA_PTR;

phys_size_t get_effective_memsize(void)
{
	return CONFIG_SYS_L3_SIZE;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch ((sysclk_conf & 0x0C) >> 2) {
	case QIXIS_CLK_100:
		return 100000000;
	case QIXIS_CLK_125:
		return 125000000;
	case QIXIS_CLK_133:
		return 133333333;
	}
	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	switch (ddrclk_conf & 0x03) {
	case QIXIS_CLK_100:
		return 100000000;
	case QIXIS_CLK_125:
		return 125000000;
	case QIXIS_CLK_133:
		return 133333333;
	}
	return 66666666;
}

void board_init_f(ulong bootflag)
{
	u32 plat_ratio, sys_clk, uart_clk;
	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;

	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));

	/* Update GD pointer */
	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);

	/* compiler optimization barrier needed for GCC >= 3.4 */
	__asm__ __volatile__("" : : : "memory");

	console_init_f();

	/* initialize selected port with appropriate baud rate */
	sys_clk = get_board_sys_clk();
	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	uart_clk = sys_clk * plat_ratio / 2;

	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
		     uart_clk / 16 / CONFIG_BAUDRATE);

	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}

void board_init_r(gd_t *gd, ulong dest_addr)
{
	bd_t *bd;

	bd = (bd_t *)(gd + sizeof(gd_t));
	memset(bd, 0, sizeof(bd_t));
	gd->bd = bd;
	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
	bd->bi_memsize = CONFIG_SYS_L3_SIZE;

	arch_cpu_init();
	get_clocks();
	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
			CONFIG_SPL_RELOC_MALLOC_SIZE);
	gd->flags |= GD_FLG_FULL_MALLOC_INIT;

#ifndef CONFIG_SPL_NAND_BOOT
	env_init();
	env_relocate();
#else
	/* relocate environment function pointers etc. */
	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
			    (uchar *)CONFIG_ENV_ADDR);
	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
	gd->env_valid = 1;
#endif

	i2c_init_all();

	puts("\n\n");

	dram_init();

#ifdef CONFIG_SPL_NAND_BOOT
	nand_boot();
#endif
}
Commit	Line	Data
c5dfe6ec PK	1	/* Copyright 2013 Freescale Semiconductor, Inc.
	2	*
	3	* SPDX-License-Identifier: GPL-2.0+
	4	*/
	5
	6	#include <common.h>
24b852a7	7	#include <console.h>
c5dfe6ec PK	8	#include <asm/spl.h>
	9	#include <malloc.h>
	10	#include <ns16550.h>
	11	#include <nand.h>
	12	#include <i2c.h>
	13	#include "../common/qixis.h"
	14	#include "b4860qds_qixis.h"
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	phys_size_t get_effective_memsize(void)
	19	{
	20	return CONFIG_SYS_L3_SIZE;
	21	}
	22
	23	unsigned long get_board_sys_clk(void)
	24	{
	25	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	26
	27	switch ((sysclk_conf & 0x0C) >> 2) {
	28	case QIXIS_CLK_100:
	29	return 100000000;
	30	case QIXIS_CLK_125:
	31	return 125000000;
	32	case QIXIS_CLK_133:
	33	return 133333333;
	34	}
	35	return 66666666;
	36	}
	37
	38	unsigned long get_board_ddr_clk(void)
	39	{
	40	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	41
	42	switch (ddrclk_conf & 0x03) {
	43	case QIXIS_CLK_100:
	44	return 100000000;
	45	case QIXIS_CLK_125:
	46	return 125000000;
	47	case QIXIS_CLK_133:
	48	return 133333333;
	49	}
	50	return 66666666;
	51	}
	52
	53	void board_init_f(ulong bootflag)
	54	{
	55	u32 plat_ratio, sys_clk, uart_clk;
	56	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	57
	58	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
	59	memcpy((void )CONFIG_SPL_GD_ADDR, (void )gd, sizeof(gd_t));
	60
	61	/* Update GD pointer */
	62	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
	63
	64	/* compiler optimization barrier needed for GCC >= 3.4 */
	65	__asm__ __volatile__("" : : : "memory");
	66
	67	console_init_f();
	68
	69	/* initialize selected port with appropriate baud rate */
	70	sys_clk = get_board_sys_clk();
	71	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
72	uart_clk = sys_clk * plat_ratio / 2;
73
74	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
75	uart_clk / 16 / CONFIG_BAUDRATE);
76
77	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
78	}
79
80	void board_init_r(gd_t *gd, ulong dest_addr)
81	{
82	bd_t *bd;
83
84	bd = (bd_t *)(gd + sizeof(gd_t));
85	memset(bd, 0, sizeof(bd_t));
86	gd->bd = bd;
87	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
88	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
89
cbcbf71b	90	arch_cpu_init();
c5dfe6ec PK	91	get_clocks();
	92	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
	93	CONFIG_SPL_RELOC_MALLOC_SIZE);
ed4708aa	94	gd->flags \|= GD_FLG_FULL_MALLOC_INIT;
c5dfe6ec PK	95
	96	#ifndef CONFIG_SPL_NAND_BOOT
	97	env_init();
	98	env_relocate();
	99	#else
	100	/* relocate environment function pointers etc. */
	101	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	102	(uchar *)CONFIG_ENV_ADDR);
	103	gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
	104	gd->env_valid = 1;
	105	#endif
	106
	107	i2c_init_all();
	108
	109	puts("\n\n");
	110
f1683aa7	111	dram_init();
c5dfe6ec PK	112
	113	#ifdef CONFIG_SPL_NAND_BOOT
	114	nand_boot();
	115	#endif
	116	}