[people/ms/u-boot.git] / board / freescale / bsc9132qds / bsc9132qds.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
#include <fsl_ddr_sdram.h>

#ifdef CONFIG_PCI
#include <pci.h>
#include <asm/fsl_pci.h>
#endif

#include "../common/qixis.h"
DECLARE_GLOBAL_DATA_PTR;


int board_early_init_f(void)
{
	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;

	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);

	return 0;
}

void board_config_serdes_mux(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
				MPC85xx_PORDEVSR_IO_SEL_SHIFT;

	switch (srds_cfg) {
	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
	case  1:
	case  2:
	case  3:
	case  4:
	case  5:
	case 22:
	case 23:
	case 24:
	case 25:
	case 26:
		QIXIS_WRITE_I2C(brdcfg[4], 0x03);
		break;

	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
	case  6:
	case  7:
	case  8:
	case  9:
	case 10:
	case 27:
	case 28:
	case 29:
	case 30:
	case 31:
		QIXIS_WRITE_I2C(brdcfg[4], 0x01);
		break;

	/* PEX(1) PEX(2) SGMII1 SGMII2 */
	case 11:
	case 32:
		QIXIS_WRITE_I2C(brdcfg[4], 0x00);
		break;

	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
	case 12:
	case 13:
	case 14:
	case 15:
	case 16:
	case 33:
	case 34:
	case 35:
	case 36:
	case 37:
		QIXIS_WRITE_I2C(brdcfg[4], 0x07);
		break;

	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
	case 17:
	case 18:
	case 19:
	case 20:
	case 21:
	case 38:
	case 39:
	case 40:
	case 41:
	case 42:
		QIXIS_WRITE_I2C(brdcfg[4], 0x05);
		break;

	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
	case 43:
	case 44:
	case 45:
	case 46:
	case 47:
		QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
		break;


	default:
		break;
	}
}

/* Configure DSP DDR controller */
void dsp_ddr_configure(void)
{
	/*
	 *There are separate DDR-controllers for DSP and PowerPC side DDR.
	 *copy the ddr controller settings from PowerPC side DDR controller
	 *to the DSP DDR controller as connected DDR memories are similar.
	 */
	struct ccsr_ddr __iomem *pa_ddr =
			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
	struct ccsr_ddr temp_ddr;
	struct ccsr_ddr __iomem *dsp_ddr =
			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;

	memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
	memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
	dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
}

int board_early_init_r(void)
{
#ifndef CONFIG_SYS_NO_FLASH
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_64M, 1);

	set_tlb(1, flashbase + 0x4000000,
			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
#endif
	board_config_serdes_mux();
	dsp_ddr_configure();
	return 0;
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */

int checkboard(void)
{
	struct cpu_type *cpu;
	u8 sw;

	cpu = gd->arch.cpu;
	printf("Board: %sQDS\n", cpu->name);

	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	printf("IFC chip select:");
	switch (sw) {
	case 0:
		printf("NOR\n");
		break;
	case 2:
		printf("Promjet\n");
		break;
	case 4:
		printf("NAND\n");
		break;
	default:
		printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
		break;
	}

	return 0;
}

#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;

#endif

#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;

	fsl_pq_mdio_init(bis, &mdio_info);
	tsec_eth_init(bis, tsec_info, num);

	#ifdef CONFIG_PCI
	pci_eth_init(bis);
	#endif

	return 0;
}
#endif

#define USBMUX_SEL_MASK		0xc0
#define USBMUX_SEL_UART2	0xc0
#define USBMUX_SEL_USB		0x40
#define SPIMUX_SEL_UART3	0x80
#define GPS_MUX_SEL_GPS		0x40

#define TSEC_1588_CLKIN_MASK	0x03
#define CON_XCVR_REF_CLK	0x00

int misc_init_r(void)
{
	u8 val;
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 porbmsr = in_be32(&gur->porbmsr);
	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;

	/*Configure 1588 clock-in source from RF Card*/
	val = QIXIS_READ_I2C(brdcfg[5]);
	QIXIS_WRITE_I2C(brdcfg[5],
		(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);

	if (hwconfig("uart2") && hwconfig("usb1")) {
		printf("UART2 and USB cannot work together on the board\n");
		printf("Remove one from hwconfig and reset\n");
	} else {
		if (hwconfig("uart2")) {
			val = QIXIS_READ_I2C(brdcfg[5]);
			QIXIS_WRITE_I2C(brdcfg[5],
				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
			clrbits_be32(&gur->pmuxcr3,
						MPC85xx_PMUXCR3_USB_SEL_MASK);
			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
		} else {
			/* By default USB should be selected.
			* Programming FPGA to select USB. */
			val = QIXIS_READ_I2C(brdcfg[5]);
			QIXIS_WRITE_I2C(brdcfg[5],
				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
		}

	}

	if (hwconfig("sim")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SPI) {

			val = QIXIS_READ_I2C(brdcfg[3]);
			QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
			clrbits_be32(&gur->pmuxcr,
				MPC85xx_PMUXCR0_SIM_SEL_MASK);
			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
		}
	}

	if (hwconfig("uart3")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SDHC) {

			/* UART3 and SPI1 (Flashes) are muxed together */
			val = QIXIS_READ_I2C(brdcfg[3]);
			QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
			clrbits_be32(&gur->pmuxcr3,
						MPC85xx_PMUXCR3_UART3_SEL_MASK);
			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);

			/* MUX to select UART3 connection to J24 header
			 * or to GPS */
			val = QIXIS_READ_I2C(brdcfg[6]);
			if (hwconfig("gps"))
				QIXIS_WRITE_I2C(brdcfg[6],
						(val | GPS_MUX_SEL_GPS));
			else
				QIXIS_WRITE_I2C(brdcfg[6],
						(val & ~(GPS_MUX_SEL_GPS)));
		}
	}
	return 0;
}

void fdt_del_node_compat(void *blob, const char *compatible)
{
	int err;
	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
	if (off < 0) {
		printf("WARNING: could not find compatible node %s: %s.\n",
			compatible, fdt_strerror(off));
		return;
	}
	err = fdt_del_node(blob, off);
	if (err < 0) {
		printf("WARNING: could not remove %s: %s.\n",
			compatible, fdt_strerror(err));
	}
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	#if defined(CONFIG_PCI)
	FT_FSL_PCI_SETUP;
	#endif

	fdt_fixup_memory(blob, (u64)base, (u64)size);

	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 porbmsr = in_be32(&gur->porbmsr);
	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;

	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
		/* If uart2 is there in hwconfig remove usb node from
		 *  device tree */

		if (hwconfig("uart2")) {
			/* remove dts usb node */
			fdt_del_node_compat(blob, "fsl-usb2-dr");
		} else {
			fdt_fixup_dr_usb(blob, bd);
			fdt_del_node_and_alias(blob, "serial2");
		}
	}

	if (hwconfig("uart3")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SDHC)
			/* Delete SPI node from the device tree */
				fdt_del_node_and_alias(blob, "spi1");
	} else
		fdt_del_node_and_alias(blob, "serial3");

	if (hwconfig("sim")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SPI) {

			/* remove dts sdhc node */
			fdt_del_node_compat(blob, "fsl,esdhc");
		} else if (romloc == PORBMSR_ROMLOC_SDHC) {

			/* remove dts sim node */
			fdt_del_node_compat(blob, "fsl,sim-v1.0");
			printf("SIM & SDHC can't work together on the board");
			printf("\nRemove sim from hwconfig and reset\n");
		}
	}
}
#endif
Commit	Line	Data
41d91011 PK	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
41d91011 PK	5	*/
	6
	7	#include <common.h>
	8	#include <asm/processor.h>
	9	#include <asm/mmu.h>
	10	#include <asm/cache.h>
	11	#include <asm/immap_85xx.h>
	12	#include <asm/io.h>
	13	#include <miiphy.h>
	14	#include <libfdt.h>
	15	#include <fdt_support.h>
	16	#include <fsl_mdio.h>
	17	#include <tsec.h>
	18	#include <mmc.h>
	19	#include <netdev.h>
0b66513b	20	#include <fsl_ifc.h>
41d91011 PK	21	#include <hwconfig.h>
41d91011 PK	22	#include <i2c.h>
5614e71b	23	#include <fsl_ddr_sdram.h>
41d91011 PK	24
	25	#ifdef CONFIG_PCI
	26	#include <pci.h>
	27	#include <asm/fsl_pci.h>
	28	#endif
	29
	30	#include "../common/qixis.h"
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33
	34	int board_early_init_f(void)
	35	{
	36	struct fsl_ifc ifc = (void )CONFIG_SYS_IFC_ADDR;
	37
	38	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
	39
	40	return 0;
	41	}
	42
	43	void board_config_serdes_mux(void)
	44	{
	45	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	46	u32 pordevsr = in_be32(&gur->pordevsr);
	47	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
	48	MPC85xx_PORDEVSR_IO_SEL_SHIFT;
	49
	50	switch (srds_cfg) {
	51	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
	52	case 1:
	53	case 2:
	54	case 3:
	55	case 4:
	56	case 5:
	57	case 22:
	58	case 23:
	59	case 24:
	60	case 25:
	61	case 26:
	62	QIXIS_WRITE_I2C(brdcfg[4], 0x03);
	63	break;
	64
	65	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
	66	case 6:
	67	case 7:
	68	case 8:
	69	case 9:
	70	case 10:
	71	case 27:
	72	case 28:
	73	case 29:
	74	case 30:
	75	case 31:
	76	QIXIS_WRITE_I2C(brdcfg[4], 0x01);
	77	break;
	78
	79	/* PEX(1) PEX(2) SGMII1 SGMII2 */
	80	case 11:
	81	case 32:
	82	QIXIS_WRITE_I2C(brdcfg[4], 0x00);
	83	break;
	84
	85	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
	86	case 12:
	87	case 13:
88	case 14:
89	case 15:
90	case 16:
91	case 33:
92	case 34:
93	case 35:
94	case 36:
95	case 37:
96	QIXIS_WRITE_I2C(brdcfg[4], 0x07);
97	break;
98
99	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
100	case 17:
101	case 18:
102	case 19:
103	case 20:
104	case 21:
105	case 38:
106	case 39:
107	case 40:
108	case 41:
109	case 42:
110	QIXIS_WRITE_I2C(brdcfg[4], 0x05);
111	break;
112
113	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
114	case 43:
115	case 44:
116	case 45:
117	case 46:
118	case 47:
119	QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
120	break;
121
122
123	default:
124	break;
125	}
126	}
127
f9d379a7 PJ	128	/* Configure DSP DDR controller */
	129	void dsp_ddr_configure(void)
	130	{
	131	/*
	132	*There are separate DDR-controllers for DSP and PowerPC side DDR.
	133	*copy the ddr controller settings from PowerPC side DDR controller
	134	*to the DSP DDR controller as connected DDR memories are similar.
	135	*/
9a17eb5b YS	136	struct ccsr_ddr __iomem *pa_ddr =
	137	(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
	138	struct ccsr_ddr temp_ddr;
	139	struct ccsr_ddr __iomem *dsp_ddr =
	140	(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
f9d379a7	141
9a17eb5b	142	memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
f9d379a7 PJ	143	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
f9d379a7 PJ	144	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
9a17eb5b	145	memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
f9d379a7 PJ	146	dsp_ddr->sdram_cfg \|= SDRAM_CFG_MEM_EN;
	147	}
	148
41d91011 PK	149	int board_early_init_r(void)
	150	{
	151	#ifndef CONFIG_SYS_NO_FLASH
	152	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	153	int flash_esel = find_tlb_idx((void *)flashbase, 1);
41d91011 PK	154
	155	/*
	156	* Remap Boot flash region to caching-inhibited
	157	* so that flash can be erased properly.
	158	*/
	159
	160	/* Flush d-cache and invalidate i-cache of any FLASH data */
	161	flush_dcache();
	162	invalidate_icache();
	163
9d045682 YS	164	if (flash_esel == -1) {
	165	/* very unlikely unless something is messed up */
	166	puts("Error: Could not find TLB for FLASH BASE\n");
	167	flash_esel = 2; /* give our best effort to continue */
	168	} else {
	169	/* invalidate existing TLB entry for flash */
	170	disable_tlb(flash_esel);
	171	}
41d91011 PK	172
	173	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	174	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	175	0, flash_esel, BOOKE_PAGESZ_64M, 1);
	176
	177	set_tlb(1, flashbase + 0x4000000,
	178	CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
	179	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	180	0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
	181	#endif
	182	board_config_serdes_mux();
f9d379a7	183	dsp_ddr_configure();
41d91011 PK	184	return 0;
	185	}
	186
	187	#ifdef CONFIG_PCI
	188	void pci_init_board(void)
	189	{
	190	fsl_pcie_init_board(0);
	191	}
	192	#endif /* ifdef CONFIG_PCI */
	193
	194	int checkboard(void)
	195	{
	196	struct cpu_type *cpu;
	197	u8 sw;
	198
67ac13b1	199	cpu = gd->arch.cpu;
41d91011 PK	200	printf("Board: %sQDS\n", cpu->name);
	201
	202	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
	203	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
	204
	205	sw = QIXIS_READ(brdcfg[0]);
	206	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	207
	208	printf("IFC chip select:");
	209	switch (sw) {
	210	case 0:
	211	printf("NOR\n");
	212	break;
	213	case 2:
	214	printf("Promjet\n");
	215	break;
	216	case 4:
	217	printf("NAND\n");
	218	break;
	219	default:
	220	printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	221	break;
	222	}
	223
	224	return 0;
	225	}
	226
	227	#ifdef CONFIG_TSEC_ENET
	228	int board_eth_init(bd_t *bis)
	229	{
	230	struct fsl_pq_mdio_info mdio_info;
	231	struct tsec_info_struct tsec_info[4];
	232	int num = 0;
	233
	234	#ifdef CONFIG_TSEC1
	235	SET_STD_TSEC_INFO(tsec_info[num], 1);
	236	num++;
	237
	238	#endif
	239
	240	#ifdef CONFIG_TSEC2
	241	SET_STD_TSEC_INFO(tsec_info[num], 2);
	242	num++;
	243	#endif
	244
	245	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	246	mdio_info.name = DEFAULT_MII_NAME;
	247
	248	fsl_pq_mdio_init(bis, &mdio_info);
	249	tsec_eth_init(bis, tsec_info, num);
	250
	251	#ifdef CONFIG_PCI
	252	pci_eth_init(bis);
	253	#endif
	254
	255	return 0;
	256	}
	257	#endif
	258
	259	#define USBMUX_SEL_MASK 0xc0
	260	#define USBMUX_SEL_UART2 0xc0
	261	#define USBMUX_SEL_USB 0x40
	262	#define SPIMUX_SEL_UART3 0x80
	263	#define GPS_MUX_SEL_GPS 0x40
264
265	#define TSEC_1588_CLKIN_MASK 0x03
266	#define CON_XCVR_REF_CLK 0x00
267
268	int misc_init_r(void)
269	{
270	u8 val;
271	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
272	u32 porbmsr = in_be32(&gur->porbmsr);
8bd00c94	273	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
41d91011 PK	274
	275	/Configure 1588 clock-in source from RF Card/
	276	val = QIXIS_READ_I2C(brdcfg[5]);
	277	QIXIS_WRITE_I2C(brdcfg[5],
	278	(val & ~(TSEC_1588_CLKIN_MASK)) \| CON_XCVR_REF_CLK);
	279
	280	if (hwconfig("uart2") && hwconfig("usb1")) {
	281	printf("UART2 and USB cannot work together on the board\n");
	282	printf("Remove one from hwconfig and reset\n");
	283	} else {
	284	if (hwconfig("uart2")) {
	285	val = QIXIS_READ_I2C(brdcfg[5]);
	286	QIXIS_WRITE_I2C(brdcfg[5],
	287	(val & ~(USBMUX_SEL_MASK)) \| USBMUX_SEL_UART2);
	288	clrbits_be32(&gur->pmuxcr3,
	289	MPC85xx_PMUXCR3_USB_SEL_MASK);
	290	setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
	291	} else {
	292	/* By default USB should be selected.
	293	* Programming FPGA to select USB. */
	294	val = QIXIS_READ_I2C(brdcfg[5]);
	295	QIXIS_WRITE_I2C(brdcfg[5],
	296	(val & ~(USBMUX_SEL_MASK)) \| USBMUX_SEL_USB);
	297	}
	298
	299	}
	300
	301	if (hwconfig("sim")) {
	302	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	303	romloc == PORBMSR_ROMLOC_NOR \|\|
	304	romloc == PORBMSR_ROMLOC_SPI) {
	305
	306	val = QIXIS_READ_I2C(brdcfg[3]);
	307	QIXIS_WRITE_I2C(brdcfg[3], val\|0x10);
	308	clrbits_be32(&gur->pmuxcr,
	309	MPC85xx_PMUXCR0_SIM_SEL_MASK);
	310	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
	311	}
	312	}
	313
	314	if (hwconfig("uart3")) {
	315	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	316	romloc == PORBMSR_ROMLOC_NOR \|\|
	317	romloc == PORBMSR_ROMLOC_SDHC) {
	318
	319	/* UART3 and SPI1 (Flashes) are muxed together */
	320	val = QIXIS_READ_I2C(brdcfg[3]);
	321	QIXIS_WRITE_I2C(brdcfg[3], (val \| SPIMUX_SEL_UART3));
	322	clrbits_be32(&gur->pmuxcr3,
	323	MPC85xx_PMUXCR3_UART3_SEL_MASK);
	324	setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
	325
	326	/* MUX to select UART3 connection to J24 header
	327	* or to GPS */
	328	val = QIXIS_READ_I2C(brdcfg[6]);
	329	if (hwconfig("gps"))
	330	QIXIS_WRITE_I2C(brdcfg[6],
	331	(val \| GPS_MUX_SEL_GPS));
	332	else
	333	QIXIS_WRITE_I2C(brdcfg[6],
	334	(val & ~(GPS_MUX_SEL_GPS)));
	335	}
	336	}
	337	return 0;
338	}
339
340	void fdt_del_node_compat(void blob, const char compatible)
341	{
342	int err;
343	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
344	if (off < 0) {
345	printf("WARNING: could not find compatible node %s: %s.\n",
346	compatible, fdt_strerror(off));
347	return;
348	}
349	err = fdt_del_node(blob, off);
350	if (err < 0) {
351	printf("WARNING: could not remove %s: %s.\n",
352	compatible, fdt_strerror(err));
353	}
354	}
355
356	#if defined(CONFIG_OF_BOARD_SETUP)
357	void ft_board_setup(void blob, bd_t bd)
358	{
359	phys_addr_t base;
360	phys_size_t size;
361
362	ft_cpu_setup(blob, bd);
363
364	base = getenv_bootm_low();
365	size = getenv_bootm_size();
366
367	#if defined(CONFIG_PCI)
368	FT_FSL_PCI_SETUP;
369	#endif
370
371	fdt_fixup_memory(blob, (u64)base, (u64)size);
372
373	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
374	u32 porbmsr = in_be32(&gur->porbmsr);
8bd00c94	375	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
41d91011 PK	376
	377	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
	378	/* If uart2 is there in hwconfig remove usb node from
	379	* device tree */
	380
	381	if (hwconfig("uart2")) {
	382	/* remove dts usb node */
	383	fdt_del_node_compat(blob, "fsl-usb2-dr");
	384	} else {
	385	fdt_fixup_dr_usb(blob, bd);
	386	fdt_del_node_and_alias(blob, "serial2");
	387	}
	388	}
	389
	390	if (hwconfig("uart3")) {
	391	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	392	romloc == PORBMSR_ROMLOC_NOR \|\|
	393	romloc == PORBMSR_ROMLOC_SDHC)
	394	/* Delete SPI node from the device tree */
	395	fdt_del_node_and_alias(blob, "spi1");
	396	} else
	397	fdt_del_node_and_alias(blob, "serial3");
	398
	399	if (hwconfig("sim")) {
	400	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	401	romloc == PORBMSR_ROMLOC_NOR \|\|
	402	romloc == PORBMSR_ROMLOC_SPI) {
	403
	404	/* remove dts sdhc node */
	405	fdt_del_node_compat(blob, "fsl,esdhc");
	406	} else if (romloc == PORBMSR_ROMLOC_SDHC) {
	407
	408	/* remove dts sim node */
	409	fdt_del_node_compat(blob, "fsl,sim-v1.0");
	410	printf("SIM & SDHC can't work together on the board");
	411	printf("\nRemove sim from hwconfig and reset\n");
	412	}
	413	}
	414	}
	415	#endif