[people/ms/u-boot.git] / board / freescale / bsc9132qds / bsc9132qds.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
#include <fsl_ddr_sdram.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <flash.h>

#ifdef CONFIG_PCI
#include <pci.h>
#include <asm/fsl_pci.h>
#endif

#include "../common/qixis.h"
DECLARE_GLOBAL_DATA_PTR;


int board_early_init_f(void)
{
	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};

	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);

	return 0;
}

void board_config_serdes_mux(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
				MPC85xx_PORDEVSR_IO_SEL_SHIFT;

	switch (srds_cfg) {
	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
	case  1:
	case  2:
	case  3:
	case  4:
	case  5:
	case 22:
	case 23:
	case 24:
	case 25:
	case 26:
		QIXIS_WRITE_I2C(brdcfg[4], 0x03);
		break;

	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
	case  6:
	case  7:
	case  8:
	case  9:
	case 10:
	case 27:
	case 28:
	case 29:
	case 30:
	case 31:
		QIXIS_WRITE_I2C(brdcfg[4], 0x01);
		break;

	/* PEX(1) PEX(2) SGMII1 SGMII2 */
	case 11:
	case 32:
		QIXIS_WRITE_I2C(brdcfg[4], 0x00);
		break;

	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
	case 12:
	case 13:
	case 14:
	case 15:
	case 16:
	case 33:
	case 34:
	case 35:
	case 36:
	case 37:
		QIXIS_WRITE_I2C(brdcfg[4], 0x07);
		break;

	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
	case 17:
	case 18:
	case 19:
	case 20:
	case 21:
	case 38:
	case 39:
	case 40:
	case 41:
	case 42:
		QIXIS_WRITE_I2C(brdcfg[4], 0x05);
		break;

	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
	case 43:
	case 44:
	case 45:
	case 46:
	case 47:
		QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
		break;


	default:
		break;
	}
}

/* Configure DSP DDR controller */
void dsp_ddr_configure(void)
{
	/*
	 *There are separate DDR-controllers for DSP and PowerPC side DDR.
	 *copy the ddr controller settings from PowerPC side DDR controller
	 *to the DSP DDR controller as connected DDR memories are similar.
	 */
	struct ccsr_ddr __iomem *pa_ddr =
			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
	struct ccsr_ddr temp_ddr;
	struct ccsr_ddr __iomem *dsp_ddr =
			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;

	memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
	memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
	dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
}

int board_early_init_r(void)
{
#ifdef CONFIG_MTD_NOR_FLASH
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_64M, 1);

	set_tlb(1, flashbase + 0x4000000,
			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
#endif
	board_config_serdes_mux();
	dsp_ddr_configure();
	return 0;
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */

int checkboard(void)
{
	struct cpu_type *cpu;
	u8 sw;

	cpu = gd->arch.cpu;
	printf("Board: %sQDS\n", cpu->name);

	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	printf("IFC chip select:");
	switch (sw) {
	case 0:
		printf("NOR\n");
		break;
	case 2:
		printf("Promjet\n");
		break;
	case 4:
		printf("NAND\n");
		break;
	default:
		printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
		break;
	}

	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;

#endif

#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;

	fsl_pq_mdio_init(bis, &mdio_info);
	tsec_eth_init(bis, tsec_info, num);
#endif

	#ifdef CONFIG_PCI
	pci_eth_init(bis);
	#endif

	return 0;
}

#define USBMUX_SEL_MASK		0xc0
#define USBMUX_SEL_UART2	0xc0
#define USBMUX_SEL_USB		0x40
#define SPIMUX_SEL_UART3	0x80
#define GPS_MUX_SEL_GPS		0x40

#define TSEC_1588_CLKIN_MASK	0x03
#define CON_XCVR_REF_CLK	0x00

int misc_init_r(void)
{
	u8 val;
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 porbmsr = in_be32(&gur->porbmsr);
	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;

	/*Configure 1588 clock-in source from RF Card*/
	val = QIXIS_READ_I2C(brdcfg[5]);
	QIXIS_WRITE_I2C(brdcfg[5],
		(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);

	if (hwconfig("uart2") && hwconfig("usb1")) {
		printf("UART2 and USB cannot work together on the board\n");
		printf("Remove one from hwconfig and reset\n");
	} else {
		if (hwconfig("uart2")) {
			val = QIXIS_READ_I2C(brdcfg[5]);
			QIXIS_WRITE_I2C(brdcfg[5],
				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
			clrbits_be32(&gur->pmuxcr3,
						MPC85xx_PMUXCR3_USB_SEL_MASK);
			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
		} else {
			/* By default USB should be selected.
			* Programming FPGA to select USB. */
			val = QIXIS_READ_I2C(brdcfg[5]);
			QIXIS_WRITE_I2C(brdcfg[5],
				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
		}

	}

	if (hwconfig("sim")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SPI) {

			val = QIXIS_READ_I2C(brdcfg[3]);
			QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
			clrbits_be32(&gur->pmuxcr,
				MPC85xx_PMUXCR0_SIM_SEL_MASK);
			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
		}
	}

	if (hwconfig("uart3")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SDHC) {

			/* UART3 and SPI1 (Flashes) are muxed together */
			val = QIXIS_READ_I2C(brdcfg[3]);
			QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
			clrbits_be32(&gur->pmuxcr3,
						MPC85xx_PMUXCR3_UART3_SEL_MASK);
			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);

			/* MUX to select UART3 connection to J24 header
			 * or to GPS */
			val = QIXIS_READ_I2C(brdcfg[6]);
			if (hwconfig("gps"))
				QIXIS_WRITE_I2C(brdcfg[6],
						(val | GPS_MUX_SEL_GPS));
			else
				QIXIS_WRITE_I2C(brdcfg[6],
						(val & ~(GPS_MUX_SEL_GPS)));
		}
	}
	return 0;
}

void fdt_del_node_compat(void *blob, const char *compatible)
{
	int err;
	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
	if (off < 0) {
		printf("WARNING: could not find compatible node %s: %s.\n",
			compatible, fdt_strerror(off));
		return;
	}
	err = fdt_del_node(blob, off);
	if (err < 0) {
		printf("WARNING: could not remove %s: %s.\n",
			compatible, fdt_strerror(err));
	}
}

#if defined(CONFIG_OF_BOARD_SETUP)
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
struct node_info nodes[] = {
	{ "cfi-flash",			MTD_DEV_TYPE_NOR,  },
	{ "fsl,ifc-nand",		MTD_DEV_TYPE_NAND, },
};
#endif
int ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	#if defined(CONFIG_PCI)
	FT_FSL_PCI_SETUP;
	#endif

	fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif

	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 porbmsr = in_be32(&gur->porbmsr);
	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;

	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
		/* If uart2 is there in hwconfig remove usb node from
		 *  device tree */

		if (hwconfig("uart2")) {
			/* remove dts usb node */
			fdt_del_node_compat(blob, "fsl-usb2-dr");
		} else {
			fsl_fdt_fixup_dr_usb(blob, bd);
			fdt_del_node_and_alias(blob, "serial2");
		}
	}

	if (hwconfig("uart3")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SDHC)
			/* Delete SPI node from the device tree */
				fdt_del_node_and_alias(blob, "spi1");
	} else
		fdt_del_node_and_alias(blob, "serial3");

	if (hwconfig("sim")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SPI) {

			/* remove dts sdhc node */
			fdt_del_node_compat(blob, "fsl,esdhc");
		} else if (romloc == PORBMSR_ROMLOC_SDHC) {

			/* remove dts sim node */
			fdt_del_node_compat(blob, "fsl,sim-v1.0");
			printf("SIM & SDHC can't work together on the board");
			printf("\nRemove sim from hwconfig and reset\n");
		}
	}

	return 0;
}
#endif
Commit	Line	Data
41d91011 PK	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
41d91011 PK	5	*/
	6
	7	#include <common.h>
	8	#include <asm/processor.h>
	9	#include <asm/mmu.h>
	10	#include <asm/cache.h>
	11	#include <asm/immap_85xx.h>
	12	#include <asm/io.h>
	13	#include <miiphy.h>
	14	#include <libfdt.h>
	15	#include <fdt_support.h>
	16	#include <fsl_mdio.h>
	17	#include <tsec.h>
	18	#include <mmc.h>
	19	#include <netdev.h>
0b66513b	20	#include <fsl_ifc.h>
41d91011 PK	21	#include <hwconfig.h>
41d91011 PK	22	#include <i2c.h>
5614e71b	23	#include <fsl_ddr_sdram.h>
42a9e2fe AK	24	#include <jffs2/load_kernel.h>
	25	#include <mtd_node.h>
	26	#include <flash.h>
41d91011 PK	27
	28	#ifdef CONFIG_PCI
	29	#include <pci.h>
	30	#include <asm/fsl_pci.h>
	31	#endif
	32
	33	#include "../common/qixis.h"
	34	DECLARE_GLOBAL_DATA_PTR;
	35
	36
	37	int board_early_init_f(void)
	38	{
39b0bbbb	39	struct fsl_ifc ifc = {(void )CONFIG_SYS_IFC_ADDR, (void )NULL};
41d91011	40
39b0bbbb	41	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
41d91011 PK	42
	43	return 0;
	44	}
	45
	46	void board_config_serdes_mux(void)
	47	{
	48	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	49	u32 pordevsr = in_be32(&gur->pordevsr);
	50	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
	51	MPC85xx_PORDEVSR_IO_SEL_SHIFT;
	52
	53	switch (srds_cfg) {
	54	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
	55	case 1:
	56	case 2:
	57	case 3:
	58	case 4:
	59	case 5:
	60	case 22:
	61	case 23:
	62	case 24:
	63	case 25:
	64	case 26:
	65	QIXIS_WRITE_I2C(brdcfg[4], 0x03);
	66	break;
	67
	68	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
	69	case 6:
	70	case 7:
	71	case 8:
	72	case 9:
	73	case 10:
	74	case 27:
	75	case 28:
	76	case 29:
	77	case 30:
	78	case 31:
	79	QIXIS_WRITE_I2C(brdcfg[4], 0x01);
	80	break;
	81
	82	/* PEX(1) PEX(2) SGMII1 SGMII2 */
	83	case 11:
	84	case 32:
	85	QIXIS_WRITE_I2C(brdcfg[4], 0x00);
	86	break;
	87
	88	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
	89	case 12:
	90	case 13:
	91	case 14:
	92	case 15:
	93	case 16:
	94	case 33:
	95	case 34:
	96	case 35:
	97	case 36:
	98	case 37:
	99	QIXIS_WRITE_I2C(brdcfg[4], 0x07);
	100	break;
	101
	102	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
	103	case 17:
	104	case 18:
	105	case 19:
106	case 20:
107	case 21:
108	case 38:
109	case 39:
110	case 40:
111	case 41:
112	case 42:
113	QIXIS_WRITE_I2C(brdcfg[4], 0x05);
114	break;
115
116	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
117	case 43:
118	case 44:
119	case 45:
120	case 46:
121	case 47:
122	QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
123	break;
124
125
126	default:
127	break;
128	}
129	}
130
f9d379a7 PJ	131	/* Configure DSP DDR controller */
	132	void dsp_ddr_configure(void)
	133	{
	134	/*
	135	*There are separate DDR-controllers for DSP and PowerPC side DDR.
	136	*copy the ddr controller settings from PowerPC side DDR controller
	137	*to the DSP DDR controller as connected DDR memories are similar.
	138	*/
9a17eb5b YS	139	struct ccsr_ddr __iomem *pa_ddr =
	140	(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
	141	struct ccsr_ddr temp_ddr;
	142	struct ccsr_ddr __iomem *dsp_ddr =
	143	(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
f9d379a7	144
9a17eb5b	145	memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
f9d379a7 PJ	146	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
f9d379a7 PJ	147	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
9a17eb5b	148	memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
f9d379a7 PJ	149	dsp_ddr->sdram_cfg \|= SDRAM_CFG_MEM_EN;
	150	}
	151
41d91011 PK	152	int board_early_init_r(void)
41d91011 PK	153	{
e856bdcf	154	#ifdef CONFIG_MTD_NOR_FLASH
41d91011	155	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	156	int flash_esel = find_tlb_idx((void *)flashbase, 1);
41d91011 PK	157
	158	/*
	159	* Remap Boot flash region to caching-inhibited
	160	* so that flash can be erased properly.
	161	*/
	162
	163	/* Flush d-cache and invalidate i-cache of any FLASH data */
	164	flush_dcache();
	165	invalidate_icache();
	166
9d045682 YS	167	if (flash_esel == -1) {
	168	/* very unlikely unless something is messed up */
	169	puts("Error: Could not find TLB for FLASH BASE\n");
	170	flash_esel = 2; /* give our best effort to continue */
	171	} else {
	172	/* invalidate existing TLB entry for flash */
	173	disable_tlb(flash_esel);
	174	}
41d91011 PK	175
	176	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	177	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	178	0, flash_esel, BOOKE_PAGESZ_64M, 1);
	179
	180	set_tlb(1, flashbase + 0x4000000,
	181	CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
	182	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	183	0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
	184	#endif
	185	board_config_serdes_mux();
f9d379a7	186	dsp_ddr_configure();
41d91011 PK	187	return 0;
	188	}
	189
	190	#ifdef CONFIG_PCI
	191	void pci_init_board(void)
	192	{
	193	fsl_pcie_init_board(0);
	194	}
	195	#endif /* ifdef CONFIG_PCI */
	196
	197	int checkboard(void)
	198	{
	199	struct cpu_type *cpu;
	200	u8 sw;
	201
67ac13b1	202	cpu = gd->arch.cpu;
41d91011 PK	203	printf("Board: %sQDS\n", cpu->name);
	204
	205	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
	206	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
	207
	208	sw = QIXIS_READ(brdcfg[0]);
	209	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	210
	211	printf("IFC chip select:");
	212	switch (sw) {
	213	case 0:
	214	printf("NOR\n");
	215	break;
	216	case 2:
	217	printf("Promjet\n");
	218	break;
	219	case 4:
	220	printf("NAND\n");
	221	break;
	222	default:
	223	printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	224	break;
	225	}
	226
	227	return 0;
	228	}
	229
41d91011 PK	230	int board_eth_init(bd_t *bis)
41d91011 PK	231	{
89c97842	232	#ifdef CONFIG_TSEC_ENET
41d91011 PK	233	struct fsl_pq_mdio_info mdio_info;
	234	struct tsec_info_struct tsec_info[4];
	235	int num = 0;
	236
	237	#ifdef CONFIG_TSEC1
	238	SET_STD_TSEC_INFO(tsec_info[num], 1);
	239	num++;
	240
	241	#endif
	242
	243	#ifdef CONFIG_TSEC2
	244	SET_STD_TSEC_INFO(tsec_info[num], 2);
	245	num++;
	246	#endif
	247
	248	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	249	mdio_info.name = DEFAULT_MII_NAME;
	250
	251	fsl_pq_mdio_init(bis, &mdio_info);
	252	tsec_eth_init(bis, tsec_info, num);
89c97842	253	#endif
41d91011 PK	254
	255	#ifdef CONFIG_PCI
	256	pci_eth_init(bis);
	257	#endif
	258
	259	return 0;
	260	}
41d91011 PK	261
	262	#define USBMUX_SEL_MASK 0xc0
	263	#define USBMUX_SEL_UART2 0xc0
	264	#define USBMUX_SEL_USB 0x40
	265	#define SPIMUX_SEL_UART3 0x80
	266	#define GPS_MUX_SEL_GPS 0x40
	267
	268	#define TSEC_1588_CLKIN_MASK 0x03
	269	#define CON_XCVR_REF_CLK 0x00
	270
	271	int misc_init_r(void)
	272	{
	273	u8 val;
	274	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	275	u32 porbmsr = in_be32(&gur->porbmsr);
8bd00c94	276	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
41d91011 PK	277
	278	/Configure 1588 clock-in source from RF Card/
	279	val = QIXIS_READ_I2C(brdcfg[5]);
	280	QIXIS_WRITE_I2C(brdcfg[5],
	281	(val & ~(TSEC_1588_CLKIN_MASK)) \| CON_XCVR_REF_CLK);
	282
	283	if (hwconfig("uart2") && hwconfig("usb1")) {
	284	printf("UART2 and USB cannot work together on the board\n");
	285	printf("Remove one from hwconfig and reset\n");
	286	} else {
	287	if (hwconfig("uart2")) {
	288	val = QIXIS_READ_I2C(brdcfg[5]);
	289	QIXIS_WRITE_I2C(brdcfg[5],
	290	(val & ~(USBMUX_SEL_MASK)) \| USBMUX_SEL_UART2);
	291	clrbits_be32(&gur->pmuxcr3,
	292	MPC85xx_PMUXCR3_USB_SEL_MASK);
	293	setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
	294	} else {
	295	/* By default USB should be selected.
	296	* Programming FPGA to select USB. */
	297	val = QIXIS_READ_I2C(brdcfg[5]);
	298	QIXIS_WRITE_I2C(brdcfg[5],
	299	(val & ~(USBMUX_SEL_MASK)) \| USBMUX_SEL_USB);
	300	}
	301
	302	}
	303
	304	if (hwconfig("sim")) {
	305	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	306	romloc == PORBMSR_ROMLOC_NOR \|\|
	307	romloc == PORBMSR_ROMLOC_SPI) {
	308
	309	val = QIXIS_READ_I2C(brdcfg[3]);
	310	QIXIS_WRITE_I2C(brdcfg[3], val\|0x10);
	311	clrbits_be32(&gur->pmuxcr,
	312	MPC85xx_PMUXCR0_SIM_SEL_MASK);
	313	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
	314	}
	315	}
	316
	317	if (hwconfig("uart3")) {
	318	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	319	romloc == PORBMSR_ROMLOC_NOR \|\|
	320	romloc == PORBMSR_ROMLOC_SDHC) {
	321
	322	/* UART3 and SPI1 (Flashes) are muxed together */
	323	val = QIXIS_READ_I2C(brdcfg[3]);
	324	QIXIS_WRITE_I2C(brdcfg[3], (val \| SPIMUX_SEL_UART3));
	325	clrbits_be32(&gur->pmuxcr3,
	326	MPC85xx_PMUXCR3_UART3_SEL_MASK);
	327	setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
	328
	329	/* MUX to select UART3 connection to J24 header
	330	* or to GPS */
	331	val = QIXIS_READ_I2C(brdcfg[6]);
	332	if (hwconfig("gps"))
	333	QIXIS_WRITE_I2C(brdcfg[6],
	334	(val \| GPS_MUX_SEL_GPS));
	335	else
	336	QIXIS_WRITE_I2C(brdcfg[6],
	337	(val & ~(GPS_MUX_SEL_GPS)));
	338	}
	339	}
	340	return 0;
341	}
342
343	void fdt_del_node_compat(void blob, const char compatible)
344	{
345	int err;
346	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
347	if (off < 0) {
348	printf("WARNING: could not find compatible node %s: %s.\n",
349	compatible, fdt_strerror(off));
350	return;
351	}
352	err = fdt_del_node(blob, off);
353	if (err < 0) {
354	printf("WARNING: could not remove %s: %s.\n",
355	compatible, fdt_strerror(err));
356	}
357	}
358
359	#if defined(CONFIG_OF_BOARD_SETUP)
42a9e2fe AK	360	#ifdef CONFIG_FDT_FIXUP_PARTITIONS
	361	struct node_info nodes[] = {
	362	{ "cfi-flash", MTD_DEV_TYPE_NOR, },
	363	{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
	364	};
	365	#endif
e895a4b0	366	int ft_board_setup(void blob, bd_t bd)
41d91011 PK	367	{
	368	phys_addr_t base;
	369	phys_size_t size;
	370
	371	ft_cpu_setup(blob, bd);
	372
	373	base = getenv_bootm_low();
	374	size = getenv_bootm_size();
	375
	376	#if defined(CONFIG_PCI)
	377	FT_FSL_PCI_SETUP;
	378	#endif
	379
	380	fdt_fixup_memory(blob, (u64)base, (u64)size);
42a9e2fe AK	381	#ifdef CONFIG_FDT_FIXUP_PARTITIONS
	382	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
	383	#endif
41d91011 PK	384
	385	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	386	u32 porbmsr = in_be32(&gur->porbmsr);
8bd00c94	387	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
41d91011 PK	388
	389	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
	390	/* If uart2 is there in hwconfig remove usb node from
	391	* device tree */
	392
	393	if (hwconfig("uart2")) {
	394	/* remove dts usb node */
	395	fdt_del_node_compat(blob, "fsl-usb2-dr");
	396	} else {
a5c289b9	397	fsl_fdt_fixup_dr_usb(blob, bd);
41d91011 PK	398	fdt_del_node_and_alias(blob, "serial2");
	399	}
	400	}
	401
	402	if (hwconfig("uart3")) {
	403	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	404	romloc == PORBMSR_ROMLOC_NOR \|\|
	405	romloc == PORBMSR_ROMLOC_SDHC)
	406	/* Delete SPI node from the device tree */
	407	fdt_del_node_and_alias(blob, "spi1");
	408	} else
	409	fdt_del_node_and_alias(blob, "serial3");
	410
	411	if (hwconfig("sim")) {
	412	if (romloc == PORBMSR_ROMLOC_NAND_2K \|\|
	413	romloc == PORBMSR_ROMLOC_NOR \|\|
	414	romloc == PORBMSR_ROMLOC_SPI) {
	415
	416	/* remove dts sdhc node */
	417	fdt_del_node_compat(blob, "fsl,esdhc");
	418	} else if (romloc == PORBMSR_ROMLOC_SDHC) {
	419
	420	/* remove dts sim node */
	421	fdt_del_node_compat(blob, "fsl,sim-v1.0");
	422	printf("SIM & SDHC can't work together on the board");
	423	printf("\nRemove sim from hwconfig and reset\n");
	424	}
	425	}
e895a4b0 SG	426
e895a4b0 SG	427	return 0;
41d91011 PK	428	}
41d91011 PK	429	#endif