[people/ms/u-boot.git] / board / freescale / common / pixis.c

/*
 * Copyright 2006 Freescale Semiconductor
 * Jeff Brown
 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>

#include "pixis.h"


static ulong strfractoint(uchar *strptr);


/*
 * Simple board reset.
 */
void pixis_reset(void)
{
    out8(PIXIS_BASE + PIXIS_RST, 0);
}


/*
 * Per table 27, page 58 of MPC8641HPCN spec.
 */
int set_px_sysclk(ulong sysclk)
{
	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;

	switch (sysclk) {
	case 33:
		sysclk_s = 0x04;
		sysclk_r = 0x04;
		sysclk_v = 0x07;
		sysclk_aux = 0x00;
		break;
	case 40:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x20;
		sysclk_aux = 0x01;
		break;
	case 50:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x2A;
		sysclk_aux = 0x02;
		break;
	case 66:
		sysclk_s = 0x01;
		sysclk_r = 0x04;
		sysclk_v = 0x04;
		sysclk_aux = 0x03;
		break;
	case 83:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x04;
		break;
	case 100:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x5C;
		sysclk_aux = 0x05;
		break;
	case 134:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x3B;
		sysclk_aux = 0x06;
		break;
	case 166:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x07;
		break;
	default:
		printf("Unsupported SYSCLK frequency.\n");
		return 0;
	}

	vclkh = (sysclk_s << 5) | sysclk_r;
	vclkl = sysclk_v;

	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);

	out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);

	return 1;
}


int set_px_mpxpll(ulong mpxpll)
{
	u8 tmp;
	u8 val;

	switch (mpxpll) {
	case 2:
	case 4:
	case 6:
	case 8:
	case 10:
	case 12:
	case 14:
	case 16:
		val = (u8) mpxpll;
		break;
	default:
		printf("Unsupported MPXPLL ratio.\n");
		return 0;
	}

	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
	tmp = (tmp & 0xF0) | (val & 0x0F);
	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);

	return 1;
}


int set_px_corepll(ulong corepll)
{
	u8 tmp;
	u8 val;

	switch ((int)corepll) {
	case 20:
		val = 0x08;
		break;
	case 25:
		val = 0x0C;
		break;
	case 30:
		val = 0x10;
		break;
	case 35:
		val = 0x1C;
		break;
	case 40:
		val = 0x14;
		break;
	case 45:
		val = 0x0E;
		break;
	default:
		printf("Unsupported COREPLL ratio.\n");
		return 0;
	}

	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
	tmp = (tmp & 0xE0) | (val & 0x1F);
	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);

	return 1;
}


void read_from_px_regs(int set)
{
	u8 mask = 0x1C;	/* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);

	if (set)
		tmp = tmp | mask;
	else
		tmp = tmp & ~mask;
	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
}


void read_from_px_regs_altbank(int set)
{
	u8 mask = 0x04;	/* FLASHBANK and FLASHMAP controlled by PIXIS */
	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);

	if (set)
		tmp = tmp | mask;
	else
		tmp = tmp & ~mask;
	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}

#ifndef CFG_PIXIS_VBOOT_MASK
#define CFG_PIXIS_VBOOT_MASK	(0x40)
#endif

void clear_altbank(void)
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
	tmp &= ~CFG_PIXIS_VBOOT_MASK;

	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}


void set_altbank(void)
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
	tmp |= CFG_PIXIS_VBOOT_MASK;

	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}


void set_px_go(void)
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp & 0x1E;			/* clear GO bit */
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp | 0x01;	/* set GO bit - start reset sequencer */
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
}


void set_px_go_with_watchdog(void)
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp & 0x1E;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp | 0x09;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
}


int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
			       int flag, int argc, char *argv[])
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp & 0x1E;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	/* setting VCTL[WDEN] to 0 to disable watch dog */
	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp &= ~0x08;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	return 0;
}

U_BOOT_CMD(
	   diswd, 1, 0, pixis_disable_watchdog_cmd,
	   "diswd	- Disable watchdog timer \n",
	   NULL);

/*
 * This function takes the non-integral cpu:mpx pll ratio
 * and converts it to an integer that can be used to assign
 * FPGA register values.
 * input: strptr i.e. argv[2]
 */

static ulong strfractoint(uchar *strptr)
{
	int i, j, retval;
	int mulconst;
	int intarr_len = 0, decarr_len = 0, no_dec = 0;
	ulong intval = 0, decval = 0;
	uchar intarr[3], decarr[3];

	/* Assign the integer part to intarr[]
	 * If there is no decimal point i.e.
	 * if the ratio is an integral value
	 * simply create the intarr.
	 */
	i = 0;
	while (strptr[i] != '.') {
		if (strptr[i] == 0) {
			no_dec = 1;
			break;
		}
		intarr[i] = strptr[i];
		i++;
	}

	/* Assign length of integer part to intarr_len. */
	intarr_len = i;
	intarr[i] = '\0';

	if (no_dec) {
		/* Currently needed only for single digit corepll ratios */
		mulconst = 10;
		decval = 0;
	} else {
		j = 0;
		i++;		/* Skipping the decimal point */
		while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
			decarr[j] = strptr[i];
			i++;
			j++;
		}

		decarr_len = j;
		decarr[j] = '\0';

		mulconst = 1;
		for (i = 0; i < decarr_len; i++)
			mulconst *= 10;
		decval = simple_strtoul((char *)decarr, NULL, 10);
	}

	intval = simple_strtoul((char *)intarr, NULL, 10);
	intval = intval * mulconst;

	retval = intval + decval;

	return retval;
}


int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned int i;
	char *p_cf = NULL;
	char *p_cf_sysclk = NULL;
	char *p_cf_corepll = NULL;
	char *p_cf_mpxpll = NULL;
	char *p_altbank = NULL;
	char *p_wd = NULL;
	unsigned int unknown_param = 0;

	/*
	 * No args is a simple reset request.
	 */
	if (argc <= 1) {
		pixis_reset();
		/* not reached */
	}

	for (i = 1; i < argc; i++) {
		if (strcmp(argv[i], "cf") == 0) {
			p_cf = argv[i];
			if (i + 3 >= argc) {
				break;
			}
			p_cf_sysclk = argv[i+1];
			p_cf_corepll = argv[i+2];
			p_cf_mpxpll = argv[i+3];
			i += 3;
			continue;
		}

		if (strcmp(argv[i], "altbank") == 0) {
			p_altbank = argv[i];
			continue;
		}

		if (strcmp(argv[i], "wd") == 0) {
			p_wd = argv[i];
			continue;
		}

		unknown_param = 1;
	}

	/*
	 * Check that cf has all required parms
	 */
	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
	    ||	unknown_param) {
		puts(cmdtp->help);
		return 1;
	}

	/*
	 * PIXIS seems to be sensitive to the ordering of
	 * the registers that are touched.
	 */
	read_from_px_regs(0);

	if (p_altbank) {
		read_from_px_regs_altbank(0);
	}
	clear_altbank();

	/*
	 * Clock configuration specified.
	 */
	if (p_cf) {
		unsigned long sysclk;
		unsigned long corepll;
		unsigned long mpxpll;

		sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
		corepll = strfractoint((uchar *) p_cf_corepll);
		mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);

		if (!(set_px_sysclk(sysclk)
		      && set_px_corepll(corepll)
		      && set_px_mpxpll(mpxpll))) {
			puts(cmdtp->help);
			return 1;
		}
		read_from_px_regs(1);
	}

	/*
	 * Altbank specified
	 *
	 * NOTE CHANGE IN BEHAVIOR: previous code would default
	 * to enabling watchdog if altbank is specified.
	 * Now the watchdog must be enabled explicitly using 'wd'.
	 */
	if (p_altbank) {
		set_altbank();
		read_from_px_regs_altbank(1);
	}

	/*
	 * Reset with watchdog specified.
	 */
	if (p_wd) {
		set_px_go_with_watchdog();
	} else {
		set_px_go();
	}

	/*
	 * Shouldn't be reached.
	 */
	return 0;
}


U_BOOT_CMD(
	pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
	"pixis_reset - Reset the board using the FPGA sequencer\n",
	"    pixis_reset\n"
	"    pixis_reset [altbank]\n"
	"    pixis_reset altbank wd\n"
	"    pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	"    pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	);
Commit	Line	Data
126aa70f JL	1	/*
	2	* Copyright 2006 Freescale Semiconductor
	3	* Jeff Brown
	4	* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
126aa70f	26	#include <command.h>
3d98b858	27	#include <watchdog.h>
314d5b6c	28	#include <asm/cache.h>
ad8f8687	29
126aa70f JL	30	#include "pixis.h"
	31
	32
3d98b858 HW	33	static ulong strfractoint(uchar *strptr);
	34
	35
	36	/*
	37	* Simple board reset.
	38	*/
	39	void pixis_reset(void)
	40	{
	41	out8(PIXIS_BASE + PIXIS_RST, 0);
	42	}
	43
	44
126aa70f JL	45	/*
	46	* Per table 27, page 58 of MPC8641HPCN spec.
	47	*/
	48	int set_px_sysclk(ulong sysclk)
	49	{
	50	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
	51
	52	switch (sysclk) {
	53	case 33:
	54	sysclk_s = 0x04;
	55	sysclk_r = 0x04;
	56	sysclk_v = 0x07;
	57	sysclk_aux = 0x00;
	58	break;
	59	case 40:
	60	sysclk_s = 0x01;
	61	sysclk_r = 0x1F;
	62	sysclk_v = 0x20;
	63	sysclk_aux = 0x01;
	64	break;
	65	case 50:
	66	sysclk_s = 0x01;
	67	sysclk_r = 0x1F;
	68	sysclk_v = 0x2A;
	69	sysclk_aux = 0x02;
	70	break;
	71	case 66:
	72	sysclk_s = 0x01;
	73	sysclk_r = 0x04;
	74	sysclk_v = 0x04;
	75	sysclk_aux = 0x03;
	76	break;
	77	case 83:
	78	sysclk_s = 0x01;
	79	sysclk_r = 0x1F;
	80	sysclk_v = 0x4B;
	81	sysclk_aux = 0x04;
	82	break;
	83	case 100:
	84	sysclk_s = 0x01;
	85	sysclk_r = 0x1F;
	86	sysclk_v = 0x5C;
	87	sysclk_aux = 0x05;
	88	break;
	89	case 134:
	90	sysclk_s = 0x06;
	91	sysclk_r = 0x1F;
	92	sysclk_v = 0x3B;
	93	sysclk_aux = 0x06;
	94	break;
	95	case 166:
	96	sysclk_s = 0x06;
	97	sysclk_r = 0x1F;
	98	sysclk_v = 0x4B;
	99	sysclk_aux = 0x07;
	100	break;
	101	default:
	102	printf("Unsupported SYSCLK frequency.\n");
	103	return 0;
	104	}
	105
80e955c7	106	vclkh = (sysclk_s << 5) \| sysclk_r;
126aa70f JL	107	vclkl = sysclk_v;
	108
	109	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
	110	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
	111
80e955c7	112	out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
126aa70f JL	113
	114	return 1;
	115	}
	116
	117
	118	int set_px_mpxpll(ulong mpxpll)
	119	{
	120	u8 tmp;
	121	u8 val;
	122
	123	switch (mpxpll) {
	124	case 2:
	125	case 4:
	126	case 6:
	127	case 8:
	128	case 10:
	129	case 12:
	130	case 14:
	131	case 16:
80e955c7	132	val = (u8) mpxpll;
126aa70f JL	133	break;
	134	default:
	135	printf("Unsupported MPXPLL ratio.\n");
	136	return 0;
	137	}
	138
	139	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
	140	tmp = (tmp & 0xF0) \| (val & 0x0F);
	141	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
	142
	143	return 1;
	144	}
	145
	146
	147	int set_px_corepll(ulong corepll)
	148	{
	149	u8 tmp;
	150	u8 val;
	151
	152	switch ((int)corepll) {
	153	case 20:
	154	val = 0x08;
	155	break;
	156	case 25:
	157	val = 0x0C;
	158	break;
	159	case 30:
	160	val = 0x10;
	161	break;
	162	case 35:
	163	val = 0x1C;
	164	break;
	165	case 40:
	166	val = 0x14;
	167	break;
	168	case 45:
	169	val = 0x0E;
	170	break;
	171	default:
	172	printf("Unsupported COREPLL ratio.\n");
	173	return 0;
	174	}
	175
	176	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
	177	tmp = (tmp & 0xE0) \| (val & 0x1F);
	178	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
	179
	180	return 1;
	181	}
	182
	183
	184	void read_from_px_regs(int set)
	185	{
16c3cde0	186	u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
126aa70f JL	187	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	188
	189	if (set)
	190	tmp = tmp \| mask;
	191	else
	192	tmp = tmp & ~mask;
	193	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
	194	}
	195
	196
	197	void read_from_px_regs_altbank(int set)
	198	{
16c3cde0	199	u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
126aa70f JL	200	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
	201
	202	if (set)
	203	tmp = tmp \| mask;
	204	else
	205	tmp = tmp & ~mask;
	206	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
	207	}
	208
db74b3c1	209	#ifndef CFG_PIXIS_VBOOT_MASK
16c3cde0	210	#define CFG_PIXIS_VBOOT_MASK (0x40)
db74b3c1	211	#endif
126aa70f	212
16c3cde0 JY	213	void clear_altbank(void)
	214	{
	215	u8 tmp;
	216
	217	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
	218	tmp &= ~CFG_PIXIS_VBOOT_MASK;
	219
	220	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
	221	}
	222
	223
126aa70f JL	224	void set_altbank(void)
	225	{
	226	u8 tmp;
	227
	228	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
16c3cde0	229	tmp \|= CFG_PIXIS_VBOOT_MASK;
126aa70f JL	230
	231	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
	232	}
	233
	234
	235	void set_px_go(void)
	236	{
	237	u8 tmp;
	238
	239	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
16c3cde0	240	tmp = tmp & 0x1E; /* clear GO bit */
126aa70f JL	241	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	242
	243	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
16c3cde0	244	tmp = tmp \| 0x01; /* set GO bit - start reset sequencer */
126aa70f JL	245	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	246	}
	247
	248
	249	void set_px_go_with_watchdog(void)
	250	{
	251	u8 tmp;
	252
	253	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	254	tmp = tmp & 0x1E;
	255	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	256
	257	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	258	tmp = tmp \| 0x09;
	259	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	260	}
	261
	262
3d98b858 HW	263	int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
3d98b858 HW	264	int flag, int argc, char *argv[])
126aa70f JL	265	{
	266	u8 tmp;
	267
	268	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	269	tmp = tmp & 0x1E;
	270	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	271
	272	/* setting VCTL[WDEN] to 0 to disable watch dog */
	273	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
80e955c7	274	tmp &= ~0x08;
126aa70f JL	275	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	276
	277	return 0;
	278	}
	279
126aa70f	280	U_BOOT_CMD(
3d98b858	281	diswd, 1, 0, pixis_disable_watchdog_cmd,
80e955c7 JL	282	"diswd - Disable watchdog timer \n",
80e955c7 JL	283	NULL);
126aa70f JL	284
	285	/*
	286	* This function takes the non-integral cpu:mpx pll ratio
	287	* and converts it to an integer that can be used to assign
	288	* FPGA register values.
	289	* input: strptr i.e. argv[2]
	290	*/
	291
3d98b858	292	static ulong strfractoint(uchar *strptr)
126aa70f JL	293	{
	294	int i, j, retval;
	295	int mulconst;
	296	int intarr_len = 0, decarr_len = 0, no_dec = 0;
	297	ulong intval = 0, decval = 0;
	298	uchar intarr[3], decarr[3];
	299
	300	/* Assign the integer part to intarr[]
	301	* If there is no decimal point i.e.
	302	* if the ratio is an integral value
	303	* simply create the intarr.
	304	*/
	305	i = 0;
16c3cde0	306	while (strptr[i] != '.') {
126aa70f JL	307	if (strptr[i] == 0) {
	308	no_dec = 1;
	309	break;
	310	}
	311	intarr[i] = strptr[i];
	312	i++;
	313	}
	314
	315	/* Assign length of integer part to intarr_len. */
	316	intarr_len = i;
	317	intarr[i] = '\0';
	318
	319	if (no_dec) {
	320	/* Currently needed only for single digit corepll ratios */
80e955c7	321	mulconst = 10;
126aa70f JL	322	decval = 0;
	323	} else {
	324	j = 0;
80e955c7	325	i++; /* Skipping the decimal point */
16c3cde0	326	while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
126aa70f JL	327	decarr[j] = strptr[i];
	328	i++;
	329	j++;
	330	}
	331
	332	decarr_len = j;
	333	decarr[j] = '\0';
	334
	335	mulconst = 1;
	336	for (i = 0; i < decarr_len; i++)
	337	mulconst *= 10;
cdd917a4	338	decval = simple_strtoul((char *)decarr, NULL, 10);
126aa70f JL	339	}
126aa70f JL	340
cdd917a4	341	intval = simple_strtoul((char *)intarr, NULL, 10);
126aa70f JL	342	intval = intval * mulconst;
	343
	344	retval = intval + decval;
	345
	346	return retval;
	347	}
3d98b858 HW	348
	349
	350	int
	351	pixis_reset_cmd(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	352	{
16c3cde0 JY	353	unsigned int i;
	354	char *p_cf = NULL;
	355	char *p_cf_sysclk = NULL;
	356	char *p_cf_corepll = NULL;
	357	char *p_cf_mpxpll = NULL;
	358	char *p_altbank = NULL;
	359	char *p_wd = NULL;
	360	unsigned int unknown_param = 0;
3d98b858 HW	361
	362	/*
	363	* No args is a simple reset request.
	364	*/
	365	if (argc <= 1) {
	366	pixis_reset();
	367	/* not reached */
	368	}
	369
16c3cde0 JY	370	for (i = 1; i < argc; i++) {
	371	if (strcmp(argv[i], "cf") == 0) {
	372	p_cf = argv[i];
	373	if (i + 3 >= argc) {
	374	break;
	375	}
	376	p_cf_sysclk = argv[i+1];
	377	p_cf_corepll = argv[i+2];
	378	p_cf_mpxpll = argv[i+3];
	379	i += 3;
	380	continue;
	381	}
3d98b858	382
16c3cde0 JY	383	if (strcmp(argv[i], "altbank") == 0) {
	384	p_altbank = argv[i];
	385	continue;
3d98b858 HW	386	}
3d98b858 HW	387
16c3cde0 JY	388	if (strcmp(argv[i], "wd") == 0) {
	389	p_wd = argv[i];
	390	continue;
3d98b858 HW	391	}
3d98b858 HW	392
16c3cde0 JY	393	unknown_param = 1;
16c3cde0 JY	394	}
3d98b858	395
16c3cde0 JY	396	/*
	397	* Check that cf has all required parms
	398	*/
	399	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
53677ef1	400	\|\| unknown_param) {
16c3cde0 JY	401	puts(cmdtp->help);
	402	return 1;
	403	}
	404
	405	/*
	406	* PIXIS seems to be sensitive to the ordering of
	407	* the registers that are touched.
	408	*/
	409	read_from_px_regs(0);
	410
	411	if (p_altbank) {
	412	read_from_px_regs_altbank(0);
	413	}
	414	clear_altbank();
	415
	416	/*
	417	* Clock configuration specified.
	418	*/
	419	if (p_cf) {
	420	unsigned long sysclk;
	421	unsigned long corepll;
	422	unsigned long mpxpll;
	423
	424	sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
	425	corepll = strfractoint((uchar *) p_cf_corepll);
	426	mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
	427
	428	if (!(set_px_sysclk(sysclk)
	429	&& set_px_corepll(corepll)
	430	&& set_px_mpxpll(mpxpll))) {
	431	puts(cmdtp->help);
3d98b858 HW	432	return 1;
3d98b858 HW	433	}
16c3cde0 JY	434	read_from_px_regs(1);
16c3cde0 JY	435	}
3d98b858	436
16c3cde0 JY	437	/*
	438	* Altbank specified
	439	*
	440	* NOTE CHANGE IN BEHAVIOR: previous code would default
	441	* to enabling watchdog if altbank is specified.
	442	* Now the watchdog must be enabled explicitly using 'wd'.
	443	*/
	444	if (p_altbank) {
	445	set_altbank();
	446	read_from_px_regs_altbank(1);
	447	}
	448
	449	/*
	450	* Reset with watchdog specified.
	451	*/
	452	if (p_wd) {
	453	set_px_go_with_watchdog();
3d98b858	454	} else {
16c3cde0	455	set_px_go();
3d98b858 HW	456	}
3d98b858 HW	457
16c3cde0 JY	458	/*
	459	* Shouldn't be reached.
	460	*/
3d98b858 HW	461	return 0;
	462	}
	463
	464
	465	U_BOOT_CMD(
	466	pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
	467	"pixis_reset - Reset the board using the FPGA sequencer\n",
	468	" pixis_reset\n"
	469	" pixis_reset [altbank]\n"
	470	" pixis_reset altbank wd\n"
	471	" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	472	" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	473	);