[people/ms/u-boot.git] / board / freescale / ls1043ardb / ls1043ardb.c

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
#include <scsi.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include "cpld.h"

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
	u8 cfg_rcw_src1, cfg_rcw_src2;
	u32 cfg_rcw_src;
	u32 sd1refclk_sel;

	printf("Board: LS1043ARDB, boot from ");

	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
	cpld_rev_bit(&cfg_rcw_src1);
	cfg_rcw_src = cfg_rcw_src1;
	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;

	if (cfg_rcw_src == 0x25)
		printf("vBank %d\n", CPLD_READ(vbank));
	else if (cfg_rcw_src == 0x106)
		puts("NAND\n");
	else
		printf("Invalid setting of SW4\n");

	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));

	puts("SERDES Reference Clocks:\n");
	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);

	return 0;
}

int dram_init(void)
{
	gd->ram_size = initdram(0);

	return 0;
}

int board_early_init_f(void)
{
	fsl_lsch2_early_init_f();
	return 0;
}

int board_init(void)
{
	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;

	/*
	 * Set CCI-400 control override register to enable barrier
	 * transaction
	 */
	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);

#ifdef CONFIG_FSL_IFC
	init_final_memctl_regs();
#endif

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif

#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	enable_layerscape_ns_access();
#endif

	return 0;
}

int config_board_mux(void)
{
	return 0;
}

#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
	config_board_mux();

	return 0;
}
#endif

int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	return 0;
}

u8 flash_read8(void *addr)
{
	return __raw_readb(addr + 1);
}

void flash_write16(u16 val, void *addr)
{
	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));

	__raw_writew(shftval, addr);
}

u16 flash_read16(void *addr)
{
	u16 val = __raw_readw(addr);

	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/clock.h>
	11	#include <asm/arch/fsl_serdes.h>
	12	#include <asm/arch/soc.h>
	13	#include <hwconfig.h>
	14	#include <ahci.h>
	15	#include <scsi.h>
	16	#include <fsl_csu.h>
	17	#include <fsl_esdhc.h>
	18	#include <fsl_ifc.h>
	19	#include "cpld.h"
	20
	21	DECLARE_GLOBAL_DATA_PTR;
	22
	23	int checkboard(void)
	24	{
	25	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
	26	u8 cfg_rcw_src1, cfg_rcw_src2;
	27	u32 cfg_rcw_src;
	28	u32 sd1refclk_sel;
	29
	30	printf("Board: LS1043ARDB, boot from ");
	31
	32	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
	33	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
	34	cpld_rev_bit(&cfg_rcw_src1);
	35	cfg_rcw_src = cfg_rcw_src1;
	36	cfg_rcw_src = (cfg_rcw_src << 1) \| cfg_rcw_src2;
	37
	38	if (cfg_rcw_src == 0x25)
	39	printf("vBank %d\n", CPLD_READ(vbank));
	40	else if (cfg_rcw_src == 0x106)
	41	puts("NAND\n");
	42	else
	43	printf("Invalid setting of SW4\n");
	44
	45	printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
	46	CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
	47
	48	puts("SERDES Reference Clocks:\n");
	49	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
	50	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
	51
	52	return 0;
	53	}
	54
	55	int dram_init(void)
	56	{
	57	gd->ram_size = initdram(0);
	58
	59	return 0;
	60	}
	61
	62	int board_early_init_f(void)
	63	{
	64	fsl_lsch2_early_init_f();
65	return 0;
66	}
67
68	int board_init(void)
69	{
70	struct ccsr_cci400 cci = (struct ccsr_cci400 )CONFIG_SYS_CCI400_ADDR;
71
72	/*
73	* Set CCI-400 control override register to enable barrier
74	* transaction
75	*/
76	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
77
78	#ifdef CONFIG_FSL_IFC
79	init_final_memctl_regs();
80	#endif
81
82	#ifdef CONFIG_ENV_IS_NOWHERE
83	gd->env_addr = (ulong)&default_environment[0];
84	#endif
85
86	#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
87	enable_layerscape_ns_access();
88	#endif
89
90	return 0;
91	}
92
93	int config_board_mux(void)
94	{
95	return 0;
96	}
97
98	#if defined(CONFIG_MISC_INIT_R)
99	int misc_init_r(void)
100	{
101	config_board_mux();
102
103	return 0;
104	}
105	#endif
106
107	int ft_board_setup(void blob, bd_t bd)
108	{
109	ft_cpu_setup(blob, bd);
110
111	return 0;
112	}
113
114	u8 flash_read8(void *addr)
115	{
116	return __raw_readb(addr + 1);
117	}
118
119	void flash_write16(u16 val, void *addr)
120	{
121	u16 shftval = (((val >> 8) & 0xff) \| ((val << 8) & 0xff00));
122
123	__raw_writew(shftval, addr);
124	}
125
126	u16 flash_read16(void *addr)
127	{
128	u16 val = __raw_readw(addr);
129
130	return (((val) >> 8) & 0x00ff) \| (((val) << 8) & 0xff00);
131	}