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f3a8e2b7 MH |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <i2c.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/arch/clock.h> | |
11 | #include <asm/arch/fsl_serdes.h> | |
12 | #include <asm/arch/soc.h> | |
73223f0e | 13 | #include <fdt_support.h> |
f3a8e2b7 MH |
14 | #include <hwconfig.h> |
15 | #include <ahci.h> | |
8ef0d5c4 | 16 | #include <mmc.h> |
f3a8e2b7 | 17 | #include <scsi.h> |
e8297341 | 18 | #include <fm_eth.h> |
f3a8e2b7 MH |
19 | #include <fsl_csu.h> |
20 | #include <fsl_esdhc.h> | |
21 | #include <fsl_ifc.h> | |
9711f528 AB |
22 | #include <environment.h> |
23 | #include <fsl_sec.h> | |
f3a8e2b7 | 24 | #include "cpld.h" |
d3e6d30c ZQ |
25 | #ifdef CONFIG_U_QE |
26 | #include <fsl_qe.h> | |
27 | #endif | |
28 | ||
f3a8e2b7 MH |
29 | |
30 | DECLARE_GLOBAL_DATA_PTR; | |
31 | ||
32 | int checkboard(void) | |
33 | { | |
34 | static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; | |
c7ca8b07 | 35 | #ifndef CONFIG_SD_BOOT |
f3a8e2b7 MH |
36 | u8 cfg_rcw_src1, cfg_rcw_src2; |
37 | u32 cfg_rcw_src; | |
c7ca8b07 | 38 | #endif |
f3a8e2b7 MH |
39 | u32 sd1refclk_sel; |
40 | ||
41 | printf("Board: LS1043ARDB, boot from "); | |
42 | ||
c7ca8b07 GQ |
43 | #ifdef CONFIG_SD_BOOT |
44 | puts("SD\n"); | |
45 | #else | |
f3a8e2b7 MH |
46 | cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); |
47 | cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); | |
48 | cpld_rev_bit(&cfg_rcw_src1); | |
49 | cfg_rcw_src = cfg_rcw_src1; | |
50 | cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; | |
51 | ||
52 | if (cfg_rcw_src == 0x25) | |
53 | printf("vBank %d\n", CPLD_READ(vbank)); | |
54 | else if (cfg_rcw_src == 0x106) | |
55 | puts("NAND\n"); | |
56 | else | |
57 | printf("Invalid setting of SW4\n"); | |
c7ca8b07 | 58 | #endif |
f3a8e2b7 MH |
59 | |
60 | printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), | |
61 | CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); | |
62 | ||
63 | puts("SERDES Reference Clocks:\n"); | |
64 | sd1refclk_sel = CPLD_READ(sd1refclk_sel); | |
65 | printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | int dram_init(void) | |
71 | { | |
72 | gd->ram_size = initdram(0); | |
73 | ||
74 | return 0; | |
75 | } | |
76 | ||
77 | int board_early_init_f(void) | |
78 | { | |
79 | fsl_lsch2_early_init_f(); | |
70231009 | 80 | |
f3a8e2b7 MH |
81 | return 0; |
82 | } | |
83 | ||
84 | int board_init(void) | |
85 | { | |
86 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; | |
87 | ||
88 | /* | |
89 | * Set CCI-400 control override register to enable barrier | |
90 | * transaction | |
91 | */ | |
92 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); | |
93 | ||
94 | #ifdef CONFIG_FSL_IFC | |
95 | init_final_memctl_regs(); | |
96 | #endif | |
97 | ||
98 | #ifdef CONFIG_ENV_IS_NOWHERE | |
99 | gd->env_addr = (ulong)&default_environment[0]; | |
100 | #endif | |
101 | ||
102 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS | |
103 | enable_layerscape_ns_access(); | |
104 | #endif | |
105 | ||
d3e6d30c ZQ |
106 | #ifdef CONFIG_U_QE |
107 | u_qe_init(); | |
108 | #endif | |
109 | ||
f3a8e2b7 MH |
110 | return 0; |
111 | } | |
112 | ||
113 | int config_board_mux(void) | |
114 | { | |
110171dc ZQ |
115 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
116 | u32 usb_pwrfault; | |
117 | ||
a12a0ef8 ZQ |
118 | if (hwconfig("qe-hdlc")) { |
119 | out_be32(&scfg->rcwpmuxcr0, | |
120 | (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); | |
121 | printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", | |
122 | in_be32(&scfg->rcwpmuxcr0)); | |
123 | } else { | |
110171dc | 124 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
a12a0ef8 ZQ |
125 | out_be32(&scfg->rcwpmuxcr0, 0x3333); |
126 | out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); | |
127 | usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << | |
128 | SCFG_USBPWRFAULT_USB3_SHIFT) | | |
129 | (SCFG_USBPWRFAULT_DEDICATED << | |
130 | SCFG_USBPWRFAULT_USB2_SHIFT) | | |
131 | (SCFG_USBPWRFAULT_SHARED << | |
132 | SCFG_USBPWRFAULT_USB1_SHIFT); | |
133 | out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); | |
110171dc | 134 | #endif |
a12a0ef8 | 135 | } |
f3a8e2b7 MH |
136 | return 0; |
137 | } | |
138 | ||
139 | #if defined(CONFIG_MISC_INIT_R) | |
140 | int misc_init_r(void) | |
141 | { | |
142 | config_board_mux(); | |
9711f528 AB |
143 | #ifdef CONFIG_SECURE_BOOT |
144 | /* In case of Secure Boot, the IBR configures the SMMU | |
145 | * to allow only Secure transactions. | |
146 | * SMMU must be reset in bypass mode. | |
147 | * Set the ClientPD bit and Clear the USFCFG Bit | |
148 | */ | |
149 | u32 val; | |
150 | val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); | |
151 | out_le32(SMMU_SCR0, val); | |
152 | val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); | |
153 | out_le32(SMMU_NSCR0, val); | |
154 | #endif | |
155 | #ifdef CONFIG_FSL_CAAM | |
156 | return sec_init(); | |
157 | #endif | |
f3a8e2b7 MH |
158 | return 0; |
159 | } | |
160 | #endif | |
161 | ||
a12a0ef8 ZQ |
162 | void fdt_del_qe(void *blob) |
163 | { | |
164 | int nodeoff = 0; | |
165 | ||
166 | while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, | |
167 | "fsl,qe")) >= 0) { | |
168 | fdt_del_node(blob, nodeoff); | |
169 | } | |
170 | } | |
171 | ||
f3a8e2b7 MH |
172 | int ft_board_setup(void *blob, bd_t *bd) |
173 | { | |
e994dddb SX |
174 | u64 base[CONFIG_NR_DRAM_BANKS]; |
175 | u64 size[CONFIG_NR_DRAM_BANKS]; | |
176 | ||
177 | /* fixup DT for the two DDR banks */ | |
178 | base[0] = gd->bd->bi_dram[0].start; | |
179 | size[0] = gd->bd->bi_dram[0].size; | |
180 | base[1] = gd->bd->bi_dram[1].start; | |
181 | size[1] = gd->bd->bi_dram[1].size; | |
182 | ||
183 | fdt_fixup_memory_banks(blob, base, size, 2); | |
f3a8e2b7 MH |
184 | ft_cpu_setup(blob, bd); |
185 | ||
e8297341 SX |
186 | #ifdef CONFIG_SYS_DPAA_FMAN |
187 | fdt_fixup_fman_ethernet(blob); | |
188 | #endif | |
a12a0ef8 ZQ |
189 | |
190 | /* | |
191 | * qe-hdlc and usb multi-use the pins, | |
192 | * when set hwconfig to qe-hdlc, delete usb node. | |
193 | */ | |
194 | if (hwconfig("qe-hdlc")) | |
195 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
196 | fdt_del_node_and_alias(blob, "usb1"); | |
197 | #endif | |
198 | /* | |
199 | * qe just support qe-uart and qe-hdlc, | |
200 | * if qe-uart and qe-hdlc are not set in hwconfig, | |
201 | * delete qe node. | |
202 | */ | |
203 | if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) | |
204 | fdt_del_qe(blob); | |
205 | ||
f3a8e2b7 MH |
206 | return 0; |
207 | } | |
208 | ||
209 | u8 flash_read8(void *addr) | |
210 | { | |
211 | return __raw_readb(addr + 1); | |
212 | } | |
213 | ||
214 | void flash_write16(u16 val, void *addr) | |
215 | { | |
216 | u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); | |
217 | ||
218 | __raw_writew(shftval, addr); | |
219 | } | |
220 | ||
221 | u16 flash_read16(void *addr) | |
222 | { | |
223 | u16 val = __raw_readw(addr); | |
224 | ||
225 | return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); | |
226 | } |