[people/ms/u-boot.git] / board / freescale / ls1088a / ls1088a.c

/*
 * Copyright 2017 NXP
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <i2c.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
#include <hwconfig.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>

#include "../common/qixis.h"
#include "ls1088a_qixis.h"
#include "../common/vid.h"
#include <fsl_immap.h>

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	fsl_lsch3_early_init_f();
	return 0;
}

#ifdef CONFIG_FSL_QIXIS
unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}
#endif

#if defined(CONFIG_VID)
int init_func_vid(void)
{
	if (adjust_vdd(0) < 0)
		printf("core voltage not adjusted\n");

	return 0;
}
#endif

#if !defined(CONFIG_SPL_BUILD)
int checkboard(void)
{
	char buf[64];
	u8 sw;
	static const char *const freq[] = {"100", "125", "156.25",
					    "100 separate SSCG"};
	int clock;

#ifdef CONFIG_TARGET_LS1088AQDS
	printf("Board: LS1088A-QDS, ");
#else
	printf("Board: LS1088A-RDB, ");
#endif

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);

#ifdef CONFIG_TARGET_LS1088AQDS
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
#else
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
#endif

	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

#ifdef CONFIG_SD_BOOT
	puts("SD card\n");
#endif
	switch (sw) {
#ifdef CONFIG_TARGET_LS1088AQDS
	case 0:
	case 1:
	case 2:
	case 3:
	case 4:
	case 5:
	case 6:
	case 7:
		printf("vBank: %d\n", sw);
		break;
	case 8:
		puts("PromJet\n");
		break;
	case 15:
		puts("IFCCard\n");
		break;
	case 14:
#else
	case 0:
#endif
		puts("QSPI:");
		sw = QIXIS_READ(brdcfg[0]);
		sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
		if (sw == 0 || sw == 4)
			puts("0\n");
		else if (sw == 1)
			puts("1\n");
		else
			puts("EMU\n");
		break;

	default:
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
		break;
	}

#ifdef CONFIG_TARGET_LS1088AQDS
	printf("FPGA: v%d (%s), build %d",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());
	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));
#else
	printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
#endif

	/*
	 * Display the actual SERDES reference clocks as configured by the
	 * dip switches on the board.  Note that the SWx registers could
	 * technically be set to force the reference clocks to match the
	 * values that the SERDES expects (or vice versa).  For now, however,
	 * we just display both values and hope the user notices when they
	 * don't match.
	 */
	puts("SERDES1 Reference : ");
	sw = QIXIS_READ(brdcfg[2]);
	clock = (sw >> 6) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 4) & 3;
	printf("Clock2 = %sMHz", freq[clock]);

	puts("\nSERDES2 Reference : ");
	clock = (sw >> 2) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 0) & 3;
	printf("Clock2 = %sMHz\n", freq[clock]);

	return 0;
}

bool if_board_diff_clk(void)
{
#ifdef CONFIG_TARGET_LS1088AQDS
	u8 diff_conf = QIXIS_READ(brdcfg[11]);
	return diff_conf & 0x40;
#else
	u8 diff_conf = QIXIS_READ(dutcfg[11]);
	return diff_conf & 0x80;
#endif
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0f) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}

	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	if (if_board_diff_clk())
		return get_board_sys_clk();
	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}

	return 66666666;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

void board_retimer_init(void)
{
	u8 reg;

	/* Retimer is connected to I2C1_CH5 */
	select_i2c_ch_pca9547(I2C_MUX_CH5);

	/* Access to Control/Shared register */
	reg = 0x0;
	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);

	/* Read device revision and ID */
	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
	debug("Retimer version id = 0x%x\n", reg);

	/* Enable Broadcast. All writes target all channel register sets */
	reg = 0x0c;
	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);

	/* Reset Channel Registers */
	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
	reg |= 0x4;
	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);

	/* Set data rate as 10.3125 Gbps */
	reg = 0x90;
	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
	reg = 0xb3;
	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
	reg = 0x90;
	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
	reg = 0xb3;
	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
	reg = 0xcd;
	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);

	/* Select VCO Divider to full rate (000) */
	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
	reg &= 0x0f;
	reg |= 0x70;
	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);

#ifdef	CONFIG_TARGET_LS1088AQDS
	/* Retimer is connected to I2C1_CH5 */
	select_i2c_ch_pca9547(I2C_MUX_CH5);

	/* Access to Control/Shared register */
	reg = 0x0;
	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);

	/* Read device revision and ID */
	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
	debug("Retimer version id = 0x%x\n", reg);

	/* Enable Broadcast. All writes target all channel register sets */
	reg = 0x0c;
	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);

	/* Reset Channel Registers */
	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
	reg |= 0x4;
	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);

	/* Set data rate as 10.3125 Gbps */
	reg = 0x90;
	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
	reg = 0xb3;
	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
	reg = 0x90;
	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
	reg = 0xb3;
	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
	reg = 0xcd;
	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);

	/* Select VCO Divider to full rate (000) */
	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
	reg &= 0x0f;
	reg |= 0x70;
	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
#endif
	/*return the default channel*/
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}

#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
#ifdef CONFIG_TARGET_LS1088ARDB
	u8 brdcfg5;

	if (hwconfig("esdhc-force-sd")) {
		brdcfg5 = QIXIS_READ(brdcfg[5]);
		brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
		brdcfg5 |= BRDCFG5_FORCE_SD;
		QIXIS_WRITE(brdcfg[5], brdcfg5);
	}
#endif
	return 0;
}
#endif

int i2c_multiplexer_select_vid_channel(u8 channel)
{
	return select_i2c_ch_pca9547(channel);
}

#ifdef CONFIG_TARGET_LS1088AQDS
/* read the current value(SVDD) of the LTM Regulator Voltage */
int get_serdes_volt(void)
{
	int  ret, vcode = 0;
	u8 chan = PWM_CHANNEL0;

	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
			PMBUS_CMD_PAGE, 1, &chan, 1);
	if (ret) {
		printf("VID: failed to select VDD Page 0\n");
		return ret;
	}

	/* Read the output voltage using PMBus command READ_VOUT */
	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
	if (ret) {
		printf("VID: failed to read the volatge\n");
		return ret;
	}

	return vcode;
}

int set_serdes_volt(int svdd)
{
	int ret, vdd_last;
	u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
			svdd & 0xFF, (svdd & 0xFF00) >> 8};

	/* Write the desired voltage code to the SVDD regulator */
	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
	if (ret) {
		printf("VID: I2C failed to write to the volatge regulator\n");
		return -1;
	}

	/* Wait for the volatge to get to the desired value */
	do {
		vdd_last = get_serdes_volt();
		if (vdd_last < 0) {
			printf("VID: Couldn't read sensor abort VID adjust\n");
			return -1;
		}
	} while (vdd_last != svdd);

	return 1;
}
#else
int get_serdes_volt(void)
{
	return 0;
}

int set_serdes_volt(int svdd)
{
	int ret;
	u8 brdcfg4;

	printf("SVDD changing of RDB\n");

	/* Read the BRDCFG54 via CLPD */
	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
	if (ret) {
		printf("VID: I2C failed to read the CPLD BRDCFG4\n");
		return -1;
	}

	brdcfg4 = brdcfg4 | 0x08;

	/* Write to the BRDCFG4 */
	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
	if (ret) {
		debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
		return -1;
	}

	/* Wait for the volatge to get to the desired value */
	udelay(10000);

	return 1;
}
#endif

/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
int board_adjust_vdd(int vdd)
{
	int ret = 0;

	debug("%s: vdd = %d\n", __func__, vdd);

	/* Special settings to be performed when voltage is 900mV */
	if (vdd == 900) {
		ret = setup_serdes_volt(vdd);
		if (ret < 0) {
			ret = -1;
			goto exit;
		}
	}
exit:
	return ret;
}

int board_init(void)
{
	init_final_memctl_regs();
#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif

	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	board_retimer_init();

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif

#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
	/* invert AQR105 IRQ pins polarity */
	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif
	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
}

#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl,dprc@0");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
void fsl_fdt_fixup_flash(void *fdt)
{
	int offset;

/*
 * IFC-NOR and QSPI are muxed on SoC.
 * So disable IFC node in dts if QSPI is enabled or
 * disable QSPI node in dts in case QSPI is not enabled.
 */

#ifdef CONFIG_FSL_QSPI
	offset = fdt_path_offset(fdt, "/soc/ifc/nor");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/ifc/nor");
#else
	offset = fdt_path_offset(fdt, "/soc/quadspi");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/quadspi");
#endif
	if (offset < 0)
		return;

	fdt_status_disabled(fdt, offset);
}

int ft_board_setup(void *blob, bd_t *bd)
{
	int err, i;
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		base[i] = gd->bd->bi_dram[i].start;
		size[i] = gd->bd->bi_dram[i].size;
	}

#ifdef CONFIG_RESV_RAM
	/* reduce size if reserved memory is within this bank */
	if (gd->arch.resv_ram >= base[0] &&
	    gd->arch.resv_ram < base[0] + size[0])
		size[0] = gd->arch.resv_ram - base[0];
	else if (gd->arch.resv_ram >= base[1] &&
		 gd->arch.resv_ram < base[1] + size[1])
		size[1] = gd->arch.resv_ram - base[1];
#endif

	fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);

	fsl_fdt_fixup_flash(blob);

#ifdef CONFIG_FSL_MC_ENET
	fdt_fixup_board_enet(blob);
	err = fsl_mc_ldpaa_exit(bd);
	if (err)
		return err;
#endif

	return 0;
}
#endif
#endif /* defined(CONFIG_SPL_BUILD) */
Commit	Line	Data
e84a324b AK	1	/*
	2	* Copyright 2017 NXP
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#include <common.h>
	7	#include <i2c.h>
	8	#include <malloc.h>
	9	#include <errno.h>
	10	#include <netdev.h>
	11	#include <fsl_ifc.h>
	12	#include <fsl_ddr.h>
	13	#include <fsl_sec.h>
	14	#include <asm/io.h>
	15	#include <fdt_support.h>
	16	#include <libfdt.h>
	17	#include <fsl-mc/fsl_mc.h>
	18	#include <environment.h>
	19	#include <asm/arch-fsl-layerscape/soc.h>
	20	#include <asm/arch/ppa.h>
44cdb5b6	21	#include <hwconfig.h>
ef0789b7 RB	22	#include <asm/arch/fsl_serdes.h>
ef0789b7 RB	23	#include <asm/arch/soc.h>
e84a324b AK	24
	25	#include "../common/qixis.h"
	26	#include "ls1088a_qixis.h"
ef0789b7 RB	27	#include "../common/vid.h"
ef0789b7 RB	28	#include <fsl_immap.h>
e84a324b AK	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
10e7eaf0 SG	32	int board_early_init_f(void)
	33	{
	34	fsl_lsch3_early_init_f();
	35	return 0;
	36	}
	37
	38	#ifdef CONFIG_FSL_QIXIS
e84a324b AK	39	unsigned long long get_qixis_addr(void)
	40	{
	41	unsigned long long addr;
	42
	43	if (gd->flags & GD_FLG_RELOC)
	44	addr = QIXIS_BASE_PHYS;
	45	else
	46	addr = QIXIS_BASE_PHYS_EARLY;
	47
	48	/*
	49	* IFC address under 256MB is mapped to 0x30000000, any address above
	50	* is mapped to 0x5_10000000 up to 4GB.
	51	*/
	52	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	53
	54	return addr;
	55	}
10e7eaf0	56	#endif
e84a324b	57
ef0789b7 RB	58	#if defined(CONFIG_VID)
	59	int init_func_vid(void)
	60	{
	61	if (adjust_vdd(0) < 0)
	62	printf("core voltage not adjusted\n");
	63
	64	return 0;
	65	}
	66	#endif
	67
10e7eaf0	68	#if !defined(CONFIG_SPL_BUILD)
e84a324b AK	69	int checkboard(void)
	70	{
	71	char buf[64];
	72	u8 sw;
	73	static const char *const freq[] = {"100", "125", "156.25",
	74	"100 separate SSCG"};
	75	int clock;
	76
7769776a AK	77	#ifdef CONFIG_TARGET_LS1088AQDS
	78	printf("Board: LS1088A-QDS, ");
	79	#else
e84a324b	80	printf("Board: LS1088A-RDB, ");
7769776a	81	#endif
e84a324b AK	82
	83	sw = QIXIS_READ(arch);
	84	printf("Board Arch: V%d, ", sw >> 4);
	85
7769776a AK	86	#ifdef CONFIG_TARGET_LS1088AQDS
	87	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	88	#else
e84a324b	89	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
7769776a	90	#endif
e84a324b AK	91
	92	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
	93
	94	sw = QIXIS_READ(brdcfg[0]);
	95	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	96
	97	#ifdef CONFIG_SD_BOOT
	98	puts("SD card\n");
	99	#endif
	100	switch (sw) {
7769776a	101	#ifdef CONFIG_TARGET_LS1088AQDS
e84a324b	102	case 0:
7769776a AK	103	case 1:
	104	case 2:
	105	case 3:
	106	case 4:
	107	case 5:
	108	case 6:
	109	case 7:
	110	printf("vBank: %d\n", sw);
	111	break;
	112	case 8:
	113	puts("PromJet\n");
	114	break;
	115	case 15:
	116	puts("IFCCard\n");
	117	break;
	118	case 14:
	119	#else
	120	case 0:
	121	#endif
e84a324b AK	122	puts("QSPI:");
	123	sw = QIXIS_READ(brdcfg[0]);
	124	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
	125	if (sw == 0 \|\| sw == 4)
	126	puts("0\n");
	127	else if (sw == 1)
	128	puts("1\n");
	129	else
	130	puts("EMU\n");
	131	break;
	132
	133	default:
	134	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	135	break;
	136	}
	137
7769776a AK	138	#ifdef CONFIG_TARGET_LS1088AQDS
	139	printf("FPGA: v%d (%s), build %d",
	140	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	141	(int)qixis_read_minor());
	142	/* the timestamp string contains "\n" at the end */
	143	printf(" on %s", qixis_read_time(buf));
	144	#else
e84a324b	145	printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
7769776a	146	#endif
e84a324b AK	147
	148	/*
	149	* Display the actual SERDES reference clocks as configured by the
	150	* dip switches on the board. Note that the SWx registers could
	151	* technically be set to force the reference clocks to match the
	152	* values that the SERDES expects (or vice versa). For now, however,
	153	* we just display both values and hope the user notices when they
	154	* don't match.
	155	*/
	156	puts("SERDES1 Reference : ");
	157	sw = QIXIS_READ(brdcfg[2]);
	158	clock = (sw >> 6) & 3;
	159	printf("Clock1 = %sMHz ", freq[clock]);
	160	clock = (sw >> 4) & 3;
	161	printf("Clock2 = %sMHz", freq[clock]);
	162
	163	puts("\nSERDES2 Reference : ");
	164	clock = (sw >> 2) & 3;
	165	printf("Clock1 = %sMHz ", freq[clock]);
	166	clock = (sw >> 0) & 3;
	167	printf("Clock2 = %sMHz\n", freq[clock]);
	168
	169	return 0;
	170	}
	171
	172	bool if_board_diff_clk(void)
	173	{
7769776a AK	174	#ifdef CONFIG_TARGET_LS1088AQDS
	175	u8 diff_conf = QIXIS_READ(brdcfg[11]);
	176	return diff_conf & 0x40;
	177	#else
e84a324b AK	178	u8 diff_conf = QIXIS_READ(dutcfg[11]);
e84a324b AK	179	return diff_conf & 0x80;
7769776a	180	#endif
e84a324b AK	181	}
	182
	183	unsigned long get_board_sys_clk(void)
	184	{
	185	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	186
	187	switch (sysclk_conf & 0x0f) {
	188	case QIXIS_SYSCLK_83:
	189	return 83333333;
	190	case QIXIS_SYSCLK_100:
	191	return 100000000;
	192	case QIXIS_SYSCLK_125:
	193	return 125000000;
	194	case QIXIS_SYSCLK_133:
	195	return 133333333;
	196	case QIXIS_SYSCLK_150:
	197	return 150000000;
	198	case QIXIS_SYSCLK_160:
	199	return 160000000;
	200	case QIXIS_SYSCLK_166:
	201	return 166666666;
	202	}
	203
	204	return 66666666;
	205	}
	206
	207	unsigned long get_board_ddr_clk(void)
	208	{
	209	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	210
	211	if (if_board_diff_clk())
	212	return get_board_sys_clk();
	213	switch ((ddrclk_conf & 0x30) >> 4) {
	214	case QIXIS_DDRCLK_100:
	215	return 100000000;
	216	case QIXIS_DDRCLK_125:
	217	return 125000000;
	218	case QIXIS_DDRCLK_133:
	219	return 133333333;
	220	}
	221
	222	return 66666666;
	223	}
	224
	225	int select_i2c_ch_pca9547(u8 ch)
	226	{
	227	int ret;
	228
	229	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	230	if (ret) {
	231	puts("PCA: failed to select proper channel\n");
	232	return ret;
	233	}
	234
	235	return 0;
	236	}
	237
	238	void board_retimer_init(void)
	239	{
	240	u8 reg;
	241
	242	/* Retimer is connected to I2C1_CH5 */
	243	select_i2c_ch_pca9547(I2C_MUX_CH5);
	244
245	/* Access to Control/Shared register */
246	reg = 0x0;
247	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
248
249	/* Read device revision and ID */
250	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
251	debug("Retimer version id = 0x%x\n", reg);
252
253	/* Enable Broadcast. All writes target all channel register sets */
254	reg = 0x0c;
255	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
256
257	/* Reset Channel Registers */
258	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
259	reg \|= 0x4;
260	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
261
262	/* Set data rate as 10.3125 Gbps */
263	reg = 0x90;
264	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
265	reg = 0xb3;
266	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
267	reg = 0x90;
268	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
269	reg = 0xb3;
270	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
271	reg = 0xcd;
272	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
273
274	/* Select VCO Divider to full rate (000) */
275	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
276	reg &= 0x0f;
277	reg \|= 0x70;
278	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
279
7769776a AK	280	#ifdef CONFIG_TARGET_LS1088AQDS
	281	/* Retimer is connected to I2C1_CH5 */
	282	select_i2c_ch_pca9547(I2C_MUX_CH5);
	283
	284	/* Access to Control/Shared register */
	285	reg = 0x0;
	286	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
e84a324b	287
7769776a AK	288	/* Read device revision and ID */
	289	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
	290	debug("Retimer version id = 0x%x\n", reg);
	291
	292	/* Enable Broadcast. All writes target all channel register sets */
	293	reg = 0x0c;
	294	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
	295
	296	/* Reset Channel Registers */
	297	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
	298	reg \|= 0x4;
	299	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
	300
	301	/* Set data rate as 10.3125 Gbps */
	302	reg = 0x90;
	303	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
	304	reg = 0xb3;
	305	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
	306	reg = 0x90;
	307	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
	308	reg = 0xb3;
	309	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
	310	reg = 0xcd;
	311	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
	312
	313	/* Select VCO Divider to full rate (000) */
	314	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
	315	reg &= 0x0f;
	316	reg \|= 0x70;
	317	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
	318	#endif
e84a324b AK	319	/return the default channel/
	320	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	321	}
	322
44cdb5b6 YL	323	#ifdef CONFIG_MISC_INIT_R
	324	int misc_init_r(void)
	325	{
	326	#ifdef CONFIG_TARGET_LS1088ARDB
	327	u8 brdcfg5;
	328
	329	if (hwconfig("esdhc-force-sd")) {
	330	brdcfg5 = QIXIS_READ(brdcfg[5]);
	331	brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
	332	brdcfg5 \|= BRDCFG5_FORCE_SD;
	333	QIXIS_WRITE(brdcfg[5], brdcfg5);
	334	}
	335	#endif
	336	return 0;
	337	}
	338	#endif
	339
ef0789b7 RB	340	int i2c_multiplexer_select_vid_channel(u8 channel)
	341	{
	342	return select_i2c_ch_pca9547(channel);
	343	}
	344
	345	#ifdef CONFIG_TARGET_LS1088AQDS
	346	/* read the current value(SVDD) of the LTM Regulator Voltage */
	347	int get_serdes_volt(void)
	348	{
	349	int ret, vcode = 0;
	350	u8 chan = PWM_CHANNEL0;
	351
	352	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
	353	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
	354	PMBUS_CMD_PAGE, 1, &chan, 1);
	355	if (ret) {
	356	printf("VID: failed to select VDD Page 0\n");
	357	return ret;
	358	}
	359
	360	/* Read the output voltage using PMBus command READ_VOUT */
	361	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
	362	PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
	363	if (ret) {
	364	printf("VID: failed to read the volatge\n");
	365	return ret;
	366	}
	367
	368	return vcode;
	369	}
	370
	371	int set_serdes_volt(int svdd)
	372	{
	373	int ret, vdd_last;
	374	u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
	375	svdd & 0xFF, (svdd & 0xFF00) >> 8};
	376
	377	/* Write the desired voltage code to the SVDD regulator */
	378	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
	379	PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
	380	if (ret) {
	381	printf("VID: I2C failed to write to the volatge regulator\n");
	382	return -1;
	383	}
	384
	385	/* Wait for the volatge to get to the desired value */
	386	do {
	387	vdd_last = get_serdes_volt();
	388	if (vdd_last < 0) {
	389	printf("VID: Couldn't read sensor abort VID adjust\n");
	390	return -1;
	391	}
	392	} while (vdd_last != svdd);
	393
	394	return 1;
	395	}
	396	#else
	397	int get_serdes_volt(void)
	398	{
	399	return 0;
	400	}
	401
	402	int set_serdes_volt(int svdd)
	403	{
404	int ret;
405	u8 brdcfg4;
406
407	printf("SVDD changing of RDB\n");
408
409	/* Read the BRDCFG54 via CLPD */
410	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
411	QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
412	if (ret) {
413	printf("VID: I2C failed to read the CPLD BRDCFG4\n");
414	return -1;
415	}
416
417	brdcfg4 = brdcfg4 \| 0x08;
418
419	/* Write to the BRDCFG4 */
420	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
421	QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
422	if (ret) {
423	debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
424	return -1;
425	}
426
427	/* Wait for the volatge to get to the desired value */
428	udelay(10000);
429
430	return 1;
431	}
432	#endif
433
434	/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
435	int board_adjust_vdd(int vdd)
436	{
437	int ret = 0;
438
439	debug("%s: vdd = %d\n", __func__, vdd);
440
441	/* Special settings to be performed when voltage is 900mV */
442	if (vdd == 900) {
443	ret = setup_serdes_volt(vdd);
444	if (ret < 0) {
445	ret = -1;
446	goto exit;
447	}
448	}
449	exit:
450	return ret;
451	}
452
e84a324b AK	453	int board_init(void)
	454	{
	455	init_final_memctl_regs();
	456	#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
	457	u32 __iomem irq_ccsr = (u32 __iomem )ISC_BASE;
	458	#endif
	459
	460	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	461	board_retimer_init();
	462
	463	#ifdef CONFIG_ENV_IS_NOWHERE
	464	gd->env_addr = (ulong)&default_environment[0];
	465	#endif
	466
	467	#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
	468	/* invert AQR105 IRQ pins polarity */
	469	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
	470	#endif
	471
30c41d21 UA	472	#ifdef CONFIG_FSL_CAAM
	473	sec_init();
	474	#endif
e84a324b AK	475	#ifdef CONFIG_FSL_LS_PPA
	476	ppa_init();
	477	#endif
	478	return 0;
	479	}
	480
e84a324b AK	481	void detail_board_ddr_info(void)
	482	{
	483	puts("\nDDR ");
	484	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	485	print_ddr_info(0);
	486	}
	487
	488	#if defined(CONFIG_ARCH_MISC_INIT)
	489	int arch_misc_init(void)
	490	{
e84a324b AK	491	return 0;
	492	}
	493	#endif
	494
	495	#ifdef CONFIG_FSL_MC_ENET
	496	void fdt_fixup_board_enet(void *fdt)
	497	{
	498	int offset;
	499
	500	offset = fdt_path_offset(fdt, "/fsl-mc");
	501
	502	if (offset < 0)
	503	offset = fdt_path_offset(fdt, "/fsl,dprc@0");
	504
	505	if (offset < 0) {
	506	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	507	__func__, offset);
	508	return;
	509	}
	510
70a131eb	511	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
e84a324b AK	512	fdt_status_okay(fdt, offset);
	513	else
	514	fdt_status_fail(fdt, offset);
	515	}
	516	#endif
	517
	518	#ifdef CONFIG_OF_BOARD_SETUP
6b6b7e8a AK	519	void fsl_fdt_fixup_flash(void *fdt)
	520	{
	521	int offset;
	522
	523	/*
	524	* IFC-NOR and QSPI are muxed on SoC.
	525	* So disable IFC node in dts if QSPI is enabled or
	526	* disable QSPI node in dts in case QSPI is not enabled.
	527	*/
	528
	529	#ifdef CONFIG_FSL_QSPI
	530	offset = fdt_path_offset(fdt, "/soc/ifc/nor");
	531
	532	if (offset < 0)
	533	offset = fdt_path_offset(fdt, "/ifc/nor");
	534	#else
	535	offset = fdt_path_offset(fdt, "/soc/quadspi");
	536
	537	if (offset < 0)
	538	offset = fdt_path_offset(fdt, "/quadspi");
	539	#endif
	540	if (offset < 0)
	541	return;
	542
	543	fdt_status_disabled(fdt, offset);
	544	}
	545
e84a324b AK	546	int ft_board_setup(void blob, bd_t bd)
	547	{
	548	int err, i;
	549	u64 base[CONFIG_NR_DRAM_BANKS];
	550	u64 size[CONFIG_NR_DRAM_BANKS];
	551
	552	ft_cpu_setup(blob, bd);
	553
	554	/* fixup DT for the two GPP DDR banks */
	555	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	556	base[i] = gd->bd->bi_dram[i].start;
	557	size[i] = gd->bd->bi_dram[i].size;
	558	}
	559
	560	#ifdef CONFIG_RESV_RAM
	561	/* reduce size if reserved memory is within this bank */
	562	if (gd->arch.resv_ram >= base[0] &&
	563	gd->arch.resv_ram < base[0] + size[0])
	564	size[0] = gd->arch.resv_ram - base[0];
	565	else if (gd->arch.resv_ram >= base[1] &&
	566	gd->arch.resv_ram < base[1] + size[1])
	567	size[1] = gd->arch.resv_ram - base[1];
	568	#endif
	569
	570	fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
	571
6b6b7e8a AK	572	fsl_fdt_fixup_flash(blob);
6b6b7e8a AK	573
e84a324b AK	574	#ifdef CONFIG_FSL_MC_ENET
	575	fdt_fixup_board_enet(blob);
	576	err = fsl_mc_ldpaa_exit(bd);
	577	if (err)
	578	return err;
	579	#endif
	580
	581	return 0;
	582	}
	583	#endif
10e7eaf0	584	#endif /* defined(CONFIG_SPL_BUILD) */