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Commit | Line | Data |
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1 | Overview |
2 | -------- | |
44937214 PK |
3 | The LS2080A Development System (QDS) is a high-performance computing, |
4 | evaluation, and development platform that supports the QorIQ LS2080A | |
5 | Layerscape Architecture processor. The LS2080AQDS provides validation and | |
6 | SW development platform for the Freescale LS2080A processor series, with | |
7288c2c2 YS |
7 | a complete debugging environment. |
8 | ||
44937214 | 9 | LS2080A SoC Overview |
7288c2c2 | 10 | ------------------ |
44937214 | 11 | The LS2080A integrated multicore processor combines eight ARM Cortex-A57 |
7288c2c2 YS |
12 | processor cores with high-performance data path acceleration logic and network |
13 | and peripheral bus interfaces required for networking, telecom/datacom, | |
14 | wireless infrastructure, and mil/aerospace applications. | |
15 | ||
44937214 | 16 | The LS2080A SoC includes the following function and features: |
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17 | |
18 | - Eight 64-bit ARM Cortex-A57 CPUs | |
19 | - 1 MB platform cache with ECC | |
20 | - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support | |
21 | - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by | |
22 | the AIOP | |
23 | - Data path acceleration architecture (DPAA2) incorporating acceleration for | |
24 | the following functions: | |
25 | - Packet parsing, classification, and distribution (WRIOP) | |
26 | - Queue and Hardware buffer management for scheduling, packet sequencing, and | |
27 | congestion management, buffer allocation and de-allocation (QBMan) | |
28 | - Cryptography acceleration (SEC) at up to 10 Gbps | |
29 | - RegEx pattern matching acceleration (PME) at up to 10 Gbps | |
30 | - Decompression/compression acceleration (DCE) at up to 20 Gbps | |
31 | - Accelerated I/O processing (AIOP) at up to 20 Gbps | |
32 | - QDMA engine | |
33 | - 16 SerDes lanes at up to 10.3125 GHz | |
34 | - Ethernet interfaces | |
35 | - Up to eight 10 Gbps Ethernet MACs | |
36 | - Up to eight 1 / 2.5 Gbps Ethernet MACs | |
37 | - High-speed peripheral interfaces | |
38 | - Four PCIe 3.0 controllers, one supporting SR-IOV | |
39 | - Additional peripheral interfaces | |
40 | - Two serial ATA (SATA 3.0) controllers | |
41 | - Two high-speed USB 3.0 controllers with integrated PHY | |
42 | - Enhanced secure digital host controller (eSDXC/eMMC) | |
43 | - Serial peripheral interface (SPI) controller | |
44 | - Quad Serial Peripheral Interface (QSPI) Controller | |
45 | - Four I2C controllers | |
46 | - Two DUARTs | |
47 | - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash | |
48 | - Support for hardware virtualization and partitioning enforcement | |
49 | - QorIQ platform's trust architecture 3.0 | |
50 | - Service processor (SP) provides pre-boot initialization and secure-boot | |
51 | capabilities | |
52 | ||
44937214 | 53 | LS2080AQDS board Overview |
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54 | ----------------------- |
55 | - SERDES Connections, 16 lanes supporting: | |
56 | - PCI Express - 3.0 | |
57 | - SGMII, SGMII 2.5 | |
58 | - QSGMII | |
59 | - SATA 3.0 | |
60 | - XAUI | |
61 | - XFI | |
62 | - DDR Controller | |
63 | - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four | |
64 | chip-selects and two DIMM connectors. Support is up to 2133MT/s. | |
65 | - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects | |
66 | and two DIMM connectors. Support is up to 1600MT/s. | |
67 | -IFC/Local Bus | |
68 | - IFC rev. 2.0 implementation supporting Little Endian connection scheme. | |
69 | - One in-socket 128 MB NOR flash 16-bit data bus | |
70 | - One 512 MB NAND flash with ECC support | |
71 | - IFC Test Port | |
72 | - PromJet Port | |
73 | - FPGA connection | |
74 | - USB 3.0 | |
75 | - Two high speed USB 3.0 ports | |
76 | - First USB 3.0 port configured as Host with Type-A connector | |
77 | - Second USB 3.0 port configured as OTG with micro-AB connector | |
78 | - SDHC: PCIe x1 Right Angle connector for supporting following cards | |
79 | - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only | |
80 | - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only | |
81 | - 4-bit eMMC Card Rev 4.4 (1.8V only) | |
82 | - 8-bit eMMC Card Rev 4.5 (1.8V only) | |
83 | - SD Card Rev 2.0 and Rev 3.0 | |
84 | - DSPI: 3 high-speed flash Memory for storage | |
85 | - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) | |
86 | - 8 MB high-speed flash Memory (up to 104 MHz) | |
87 | - 512 MB low-speed flash Memory (up to 40 MHz) | |
88 | - QSPI: via NAND/QSPI Card | |
89 | - 4 I2C controllers | |
90 | - Two SATA onboard connectors | |
91 | - UART | |
92 | - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s | |
93 | - Two DB9 D-Type connectors supporting one Serial port each | |
94 | - ARM JTAG support | |
95 | ||
96 | Memory map from core's view | |
97 | ---------------------------- | |
98 | 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom | |
99 | 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR | |
100 | 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM | |
101 | 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 | |
102 | 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 | |
103 | 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 | |
104 | 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 | |
105 | ||
106 | Other addresses are either reserved, or not used directly by u-boot. | |
107 | This list should be updated when more addresses are used. | |
108 | ||
109 | IFC region map from core's view | |
110 | ------------------------------- | |
111 | During boot i.e. IFC Region #1:- | |
112 | 0x30000000 - 0x37ffffff : 128MB : NOR flash | |
113 | 0x38000000 - 0x3BFFFFFF : 64MB : Promjet | |
114 | 0x3C000000 - 0x40000000 : 64MB : FPGA etc | |
115 | ||
116 | After relocate to DDR i.e. IFC Region #2:- | |
117 | 0x5_1000_0000..0x5_1fff_ffff Memory Hole | |
118 | 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) | |
119 | 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB | |
120 | 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) | |
121 | 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) | |
122 | ||
123 | Booting Options | |
124 | --------------- | |
125 | a) Promjet Boot | |
126 | b) NOR boot | |
127 | c) NAND boot | |
128 | d) SD boot | |
129 | e) QSPI boot | |
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130 | |
131 | Environment Variables | |
132 | --------------------- | |
133 | - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined | |
134 | the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. | |
135 | ||
136 | - mcmemsize: MC DRAM block size. If this variable is not defined | |
137 | the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. | |
138 | ||
139 | Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) | |
140 | ------------------------------------------------------------------- | |
141 | One needs to use appropriate bootargs to boot Linux flavors which do | |
142 | not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown | |
143 | below: | |
144 | ||
145 | => setenv bootargs 'console=ttyS1,115200 root=/dev/ram | |
146 | earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m | |
147 | hugepages=16 mem=2048M' | |
148 | ||
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149 | |
150 | X-QSGMII-16PORT riser card | |
151 | ---------------------------- | |
152 | The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes | |
153 | interfaces implemented in PCIe form factor board. | |
154 | It supports followings | |
155 | - Card can operate with up to 4 QSGMII lane simultaneously | |
156 | - Card can operate with up to 8 SGMII lane simultaneously | |
157 | ||
158 | Supported card configuration | |
159 | - CSEL : ON ON ON ON | |
160 | - MSEL1 : ON ON ON ON OFF OFF OFF OFF | |
161 | - MSEL2 : OFF OFF OFF OFF ON ON ON ON | |
162 | ||
163 | To enable this card: modify hwconfig to add "xqsgmii" variable. | |
164 | ||
165 | Supported PHY addresses during SGMII: | |
166 | #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 | |
167 | #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 | |
168 | #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 | |
169 | #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 | |
170 | #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 | |
171 | #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa | |
172 | #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc | |
173 | #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe | |
174 | ||
175 | Mapping DPMACx to PHY during QSGMII | |
176 | DPMAC1 -> PHY1-P0 | |
177 | DPMAC2 -> PHY2-P0 | |
178 | DPMAC3 -> PHY3-P0 | |
179 | DPMAC4 -> PHY4-P0 | |
180 | DPMAC5 -> PHY3-P2 | |
181 | DPMAC6 -> PHY1-P2 | |
182 | DPMAC7 -> PHY4-P1 | |
183 | DPMAC8 -> PHY2-P2 | |
184 | DPMAC9 -> PHY1-P0 | |
185 | DPMAC10 -> PHY2-P0 | |
186 | DPMAC11 -> PHY3-P0 | |
187 | DPMAC12 -> PHY4-P0 | |
188 | DPMAC13 -> PHY3-P2 | |
189 | DPMAC14 -> PHY1-P2 | |
190 | DPMAC15 -> PHY4-P1 | |
191 | DPMAC16 -> PHY2-P2 | |
192 | ||
193 | ||
194 | Supported PHY address during QSGMII | |
195 | #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 | |
196 | #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 | |
197 | #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 | |
198 | #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 | |
199 | #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 | |
200 | #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 | |
201 | #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 | |
202 | #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 | |
203 | #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 | |
204 | #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 | |
205 | #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa | |
206 | #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb | |
207 | #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc | |
208 | #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd | |
209 | #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe | |
210 | #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf | |
211 | ||
212 | Mapping DPMACx to PHY during QSGMII | |
213 | DPMAC1 -> PHY1-P3 | |
214 | DPMAC2 -> PHY1-P2 | |
215 | DPMAC3 -> PHY1-P1 | |
216 | DPMAC4 -> PHY1-P0 | |
217 | DPMAC5 -> PHY2-P3 | |
218 | DPMAC6 -> PHY2-P2 | |
219 | DPMAC7 -> PHY2-P1 | |
220 | DPMAC8 -> PHY2-P0 | |
221 | DPMAC9 -> PHY3-P0 | |
222 | DPMAC10 -> PHY3-P1 | |
223 | DPMAC11 -> PHY3-P2 | |
224 | DPMAC12 -> PHY3-P3 | |
225 | DPMAC13 -> PHY4-P0 | |
226 | DPMAC14 -> PHY4-P1 | |
227 | DPMAC15 -> PHY4-P2 | |
228 | DPMAC16 -> PHY4-P3 | |
229 |