[people/ms/u-boot.git] / board / freescale / ls2080ardb / ddr.c

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/arch/soc.h>
#include <asm/arch/clock.h>
#include "ddr.h"

DECLARE_GLOBAL_DATA_PTR;

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
#endif
	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
	ulong ddr_freq;
	int slot;

	if (ctrl_num > 2) {
		printf("Not supported controller number %d\n", ctrl_num);
		return;
	}

	for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
		if (pdimm[slot].n_ranks)
			break;
	}

	if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
		return;

	/*
	 * we use identical timing for all slots. If needed, change the code
	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
	 */
	if (popts->registered_dimm_en)
		pbsp = rdimms[ctrl_num];
	else
		pbsp = udimms[ctrl_num];


	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
	 * freqency and n_banks specified in board_specific_parameters table.
	 */
	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
	while (pbsp->datarate_mhz_high) {
		if (pbsp->n_ranks == pdimm[slot].n_ranks &&
		    (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
			if (ddr_freq <= pbsp->datarate_mhz_high) {
				popts->clk_adjust = pbsp->clk_adjust;
				popts->wrlvl_start = pbsp->wrlvl_start;
				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
				goto found;
			}
			pbsp_highest = pbsp;
		}
		pbsp++;
	}

	if (pbsp_highest) {
		printf("Error: board specific timing not found for data rate %lu MT/s\n"
			"Trying to use the highest speed (%u) parameters\n",
			ddr_freq, pbsp_highest->datarate_mhz_high);
		popts->clk_adjust = pbsp_highest->clk_adjust;
		popts->wrlvl_start = pbsp_highest->wrlvl_start;
		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	} else {
		panic("DIMM is not supported by this board");
	}
found:
	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
		pbsp->wrlvl_ctl_3);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
		/* force DDR bus width to 32 bits */
		popts->data_bus_width = 1;
		popts->otf_burst_chop_en = 0;
		popts->burst_length = DDR_BL8;
		popts->bstopre = 0;	/* enable auto precharge */
		/*
		 * Layout optimization results byte mapping
		 * Byte 0 -> Byte ECC
		 * Byte 1 -> Byte 3
		 * Byte 2 -> Byte 2
		 * Byte 3 -> Byte 1
		 * Byte ECC -> Byte 0
		 */
		dq_mapping_0 = pdimm[slot].dq_mapping[0];
		dq_mapping_2 = pdimm[slot].dq_mapping[2];
		dq_mapping_3 = pdimm[slot].dq_mapping[3];
		pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
		pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
		pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
		pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
		pdimm[slot].dq_mapping[6] = dq_mapping_2;
		pdimm[slot].dq_mapping[7] = dq_mapping_3;
		pdimm[slot].dq_mapping[8] = dq_mapping_0;
		pdimm[slot].dq_mapping[9] = 0;
		pdimm[slot].dq_mapping[10] = 0;
		pdimm[slot].dq_mapping[11] = 0;
		pdimm[slot].dq_mapping[12] = 0;
		pdimm[slot].dq_mapping[13] = 0;
		pdimm[slot].dq_mapping[14] = 0;
		pdimm[slot].dq_mapping[15] = 0;
		pdimm[slot].dq_mapping[16] = 0;
		pdimm[slot].dq_mapping[17] = 0;
	}
#endif
	/* To work at higher than 1333MT/s */
	popts->half_strength_driver_enable = 0;
	/*
	 * Write leveling override
	 */
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0x0;	/* 32 clocks */

	/*
	 * Rtt and Rtt_WR override
	 */
	popts->rtt_override = 0;

	/* Enable ZQ calibration */
	popts->zq_en = 1;

	/* optimize cpo for erratum A-009942 */
	popts->cpo_sample = 0x6e;

	if (ddr_freq < 2350) {
		if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
			/* four chip-selects */
			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
					  DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
			popts->twot_en = 1;	/* enable 2T timing */
		} else {
			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
					  DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
					  DDR_CDR2_VREF_RANGE_2;
		}
	} else {
		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
				  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
				  DDR_CDR2_VREF_RANGE_2;
	}
}

int fsl_initdram(void)
{
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
	gd->ram_size = fsl_ddr_sdram_size();
#else
	puts("Initializing DDR....using SPD\n");

	gd->ram_size = fsl_ddr_sdram();
#endif

	return 0;
}
Commit	Line	Data
e2b65ea9 YS	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <fsl_ddr_sdram.h>
	9	#include <fsl_ddr_dimm_params.h>
3c1d218a	10	#include <asm/arch/soc.h>
6e2941d7	11	#include <asm/arch/clock.h>
e2b65ea9 YS	12	#include "ddr.h"
	13
	14	DECLARE_GLOBAL_DATA_PTR;
	15
	16	void fsl_ddr_board_options(memctl_options_t *popts,
	17	dimm_params_t *pdimm,
	18	unsigned int ctrl_num)
	19	{
44937214	20	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
e2b65ea9	21	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
44937214	22	#endif
e2b65ea9 YS	23	const struct board_specific_parameters pbsp, pbsp_highest = NULL;
	24	ulong ddr_freq;
	25	int slot;
	26
	27	if (ctrl_num > 2) {
	28	printf("Not supported controller number %d\n", ctrl_num);
	29	return;
	30	}
	31
	32	for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
	33	if (pdimm[slot].n_ranks)
	34	break;
	35	}
	36
	37	if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
	38	return;
	39
	40	/*
	41	* we use identical timing for all slots. If needed, change the code
	42	* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
	43	*/
	44	if (popts->registered_dimm_en)
	45	pbsp = rdimms[ctrl_num];
	46	else
	47	pbsp = udimms[ctrl_num];
	48
	49
	50	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
	51	* freqency and n_banks specified in board_specific_parameters table.
	52	*/
	53	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
	54	while (pbsp->datarate_mhz_high) {
	55	if (pbsp->n_ranks == pdimm[slot].n_ranks &&
	56	(pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
	57	if (ddr_freq <= pbsp->datarate_mhz_high) {
	58	popts->clk_adjust = pbsp->clk_adjust;
	59	popts->wrlvl_start = pbsp->wrlvl_start;
	60	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	61	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	62	goto found;
	63	}
	64	pbsp_highest = pbsp;
	65	}
	66	pbsp++;
	67	}
	68
	69	if (pbsp_highest) {
	70	printf("Error: board specific timing not found for data rate %lu MT/s\n"
	71	"Trying to use the highest speed (%u) parameters\n",
	72	ddr_freq, pbsp_highest->datarate_mhz_high);
	73	popts->clk_adjust = pbsp_highest->clk_adjust;
	74	popts->wrlvl_start = pbsp_highest->wrlvl_start;
	75	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	76	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	77	} else {
	78	panic("DIMM is not supported by this board");
	79	}
	80	found:
	81	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
	82	"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
	83	pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
	84	pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
	85	pbsp->wrlvl_ctl_3);
44937214	86	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
e2b65ea9 YS	87	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
	88	/* force DDR bus width to 32 bits */
	89	popts->data_bus_width = 1;
	90	popts->otf_burst_chop_en = 0;
	91	popts->burst_length = DDR_BL8;
	92	popts->bstopre = 0; /* enable auto precharge */
	93	/*
	94	* Layout optimization results byte mapping
	95	* Byte 0 -> Byte ECC
	96	* Byte 1 -> Byte 3
	97	* Byte 2 -> Byte 2
	98	* Byte 3 -> Byte 1
	99	* Byte ECC -> Byte 0
	100	*/
	101	dq_mapping_0 = pdimm[slot].dq_mapping[0];
	102	dq_mapping_2 = pdimm[slot].dq_mapping[2];
	103	dq_mapping_3 = pdimm[slot].dq_mapping[3];
	104	pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
	105	pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
	106	pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
	107	pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
	108	pdimm[slot].dq_mapping[6] = dq_mapping_2;
	109	pdimm[slot].dq_mapping[7] = dq_mapping_3;
	110	pdimm[slot].dq_mapping[8] = dq_mapping_0;
	111	pdimm[slot].dq_mapping[9] = 0;
	112	pdimm[slot].dq_mapping[10] = 0;
	113	pdimm[slot].dq_mapping[11] = 0;
	114	pdimm[slot].dq_mapping[12] = 0;
	115	pdimm[slot].dq_mapping[13] = 0;
	116	pdimm[slot].dq_mapping[14] = 0;
	117	pdimm[slot].dq_mapping[15] = 0;
	118	pdimm[slot].dq_mapping[16] = 0;
	119	pdimm[slot].dq_mapping[17] = 0;
	120	}
44937214	121	#endif
e2b65ea9 YS	122	/* To work at higher than 1333MT/s */
	123	popts->half_strength_driver_enable = 0;
	124	/*
	125	* Write leveling override
	126	*/
	127	popts->wrlvl_override = 1;
	128	popts->wrlvl_sample = 0x0; /* 32 clocks */
	129
	130	/*
	131	* Rtt and Rtt_WR override
	132	*/
	133	popts->rtt_override = 0;
	134
	135	/* Enable ZQ calibration */
	136	popts->zq_en = 1;
	137
90101386 SL	138	/* optimize cpo for erratum A-009942 */
	139	popts->cpo_sample = 0x6e;
	140
e2b65ea9	141	if (ddr_freq < 2350) {
3901978d YS	142	if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
	143	/* four chip-selects */
	144	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \|
	145	DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
	146	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
	147	popts->twot_en = 1; /* enable 2T timing */
	148	} else {
	149	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \|
	150	DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
	151	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) \|
	152	DDR_CDR2_VREF_RANGE_2;
	153	}
e2b65ea9 YS	154	} else {
	155	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \|
	156	DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
	157	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) \|
	158	DDR_CDR2_VREF_RANGE_2;
	159	}
	160	}
	161
3eace37e	162	int fsl_initdram(void)
e2b65ea9	163	{
32eda7cc	164	#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
088454cd	165	gd->ram_size = fsl_ddr_sdram_size();
32eda7cc	166	#else
e2b65ea9 YS	167	puts("Initializing DDR....using SPD\n");
e2b65ea9 YS	168
088454cd	169	gd->ram_size = fsl_ddr_sdram();
32eda7cc	170	#endif
e2b65ea9	171
088454cd	172	return 0;
e2b65ea9	173	}