[people/ms/u-boot.git] / board / freescale / ls2080ardb / ls2080ardb.c

/*
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
#include <hwconfig.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <efi_loader.h>
#include <i2c.h>
#include <asm/arch/soc.h>
#include <fsl_sec.h>

#include "../common/qixis.h"
#include "ls2080ardb_qixis.h"
#include "../common/vid.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
	u8 sw;
	char buf[15];

	cpu_name(buf);
	printf("Board: %s-RDB, ", buf);

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x9)
		puts("NAND\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));

	puts("SERDES1 Reference : ");
	printf("Clock1 = 156.25MHz ");
	printf("Clock2 = 156.25MHz");

	puts("\nSERDES2 Reference : ");
	printf("Clock1 = 100MHz ");
	printf("Clock2 = 100MHz\n");

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int i2c_multiplexer_select_vid_channel(u8 channel)
{
	return select_i2c_ch_pca9547(channel);
}

int config_board_mux(int ctrl_type)
{
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);

	return 0;
}

int board_init(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#ifdef CONFIG_FSL_MC_ENET
	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
	u32 val;

	init_final_memctl_regs();

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = getenv("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);

#ifdef CONFIG_FSL_MC_ENET
	/* invert AQR405 IRQ pins polarity */
	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif

	return 0;
}

int board_early_init_f(void)
{
	fsl_lsch3_early_init_f();
	return 0;
}

int misc_init_r(void)
{
	if (hwconfig("sdhc"))
		config_board_mux(MUX_TYPE_SDHC);

	if (adjust_vdd(0))
		printf("Warning: Adjusting core voltage failed.\n");

#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
		efi_add_memory_map(gd->bd->bi_dram[2].start,
				   gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
				   EFI_RESERVED_MEMORY_TYPE, false);
	}
#endif

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
#endif
}

int dram_init(void)
{
	gd->ram_size = initdram(0);

	return 0;
}

#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif
	return 0;
}
#endif

#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/soc/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if (get_mc_boot_status() == 0)
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}

void board_quiesce_devices(void)
{
	fsl_mc_ldpaa_exit(gd->bd);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

	fdt_fixup_memory_banks(blob, base, size, 2);

	fsl_fdt_fixup_dr_usb(blob, bd);

#ifdef CONFIG_FSL_MC_ENET
	fdt_fixup_board_enet(blob);
#endif

	return 0;
}
#endif

void qixis_dump_switch(void)
{
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
}

/*
 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 * Both slots has 0x54, resulting 2nd slot unusable.
 */
void update_spd_address(unsigned int ctrl_num,
			unsigned int slot,
			unsigned int *addr)
{
	u8 sw;

	sw = QIXIS_READ(arch);
	if ((sw & 0xf) < 0x3) {
		if (ctrl_num == 1 && slot == 0)
			*addr = SPD_EEPROM_ADDRESS4;
		else if (ctrl_num == 1 && slot == 1)
			*addr = SPD_EEPROM_ADDRESS3;
	}
}
Commit	Line	Data
e2b65ea9 YS	1	/*
	2	* Copyright 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#include <common.h>
	7	#include <malloc.h>
	8	#include <errno.h>
	9	#include <netdev.h>
	10	#include <fsl_ifc.h>
	11	#include <fsl_ddr.h>
	12	#include <asm/io.h>
5a4d744c	13	#include <hwconfig.h>
e2b65ea9 YS	14	#include <fdt_support.h>
e2b65ea9 YS	15	#include <libfdt.h>
e2b65ea9 YS	16	#include <fsl-mc/fsl_mc.h>
e2b65ea9 YS	17	#include <environment.h>
215b1fb9	18	#include <efi_loader.h>
e2b65ea9	19	#include <i2c.h>
9f3183d2	20	#include <asm/arch/soc.h>
fcfdb6d5	21	#include <fsl_sec.h>
e2b65ea9 YS	22
e2b65ea9 YS	23	#include "../common/qixis.h"
44937214	24	#include "ls2080ardb_qixis.h"
ed2530d0	25	#include "../common/vid.h"
e2b65ea9	26
5a4d744c	27	#define PIN_MUX_SEL_SDHC 0x00
5989df7e	28	#define PIN_MUX_SEL_DSPI 0x0a
5a4d744c YL	29
5a4d744c YL	30	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
e2b65ea9 YS	31	DECLARE_GLOBAL_DATA_PTR;
e2b65ea9 YS	32
5a4d744c YL	33	enum {
5a4d744c YL	34	MUX_TYPE_SDHC,
5989df7e	35	MUX_TYPE_DSPI,
5a4d744c YL	36	};
5a4d744c YL	37
e2b65ea9 YS	38	unsigned long long get_qixis_addr(void)
	39	{
	40	unsigned long long addr;
	41
	42	if (gd->flags & GD_FLG_RELOC)
	43	addr = QIXIS_BASE_PHYS;
	44	else
	45	addr = QIXIS_BASE_PHYS_EARLY;
	46
	47	/*
	48	* IFC address under 256MB is mapped to 0x30000000, any address above
	49	* is mapped to 0x5_10000000 up to 4GB.
	50	*/
	51	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	52
	53	return addr;
	54	}
	55
	56	int checkboard(void)
	57	{
	58	u8 sw;
ff1b8e3f PK	59	char buf[15];
	60
	61	cpu_name(buf);
	62	printf("Board: %s-RDB, ", buf);
e2b65ea9 YS	63
e2b65ea9 YS	64	sw = QIXIS_READ(arch);
e2b65ea9	65	printf("Board Arch: V%d, ", sw >> 4);
27df54b1	66	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
e2b65ea9 YS	67
	68	sw = QIXIS_READ(brdcfg[0]);
	69	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	70
	71	if (sw < 0x8)
	72	printf("vBank: %d\n", sw);
	73	else if (sw == 0x9)
	74	puts("NAND\n");
	75	else
	76	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	77
	78	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
	79
	80	puts("SERDES1 Reference : ");
	81	printf("Clock1 = 156.25MHz ");
	82	printf("Clock2 = 156.25MHz");
	83
	84	puts("\nSERDES2 Reference : ");
	85	printf("Clock1 = 100MHz ");
	86	printf("Clock2 = 100MHz\n");
	87
	88	return 0;
	89	}
	90
	91	unsigned long get_board_sys_clk(void)
	92	{
	93	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	94
	95	switch (sysclk_conf & 0x0F) {
	96	case QIXIS_SYSCLK_83:
	97	return 83333333;
	98	case QIXIS_SYSCLK_100:
	99	return 100000000;
	100	case QIXIS_SYSCLK_125:
	101	return 125000000;
	102	case QIXIS_SYSCLK_133:
	103	return 133333333;
	104	case QIXIS_SYSCLK_150:
	105	return 150000000;
	106	case QIXIS_SYSCLK_160:
	107	return 160000000;
	108	case QIXIS_SYSCLK_166:
	109	return 166666666;
	110	}
	111	return 66666666;
	112	}
	113
	114	int select_i2c_ch_pca9547(u8 ch)
	115	{
	116	int ret;
	117
	118	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	119	if (ret) {
	120	puts("PCA: failed to select proper channel\n");
	121	return ret;
	122	}
	123
	124	return 0;
	125	}
	126
ed2530d0 RH	127	int i2c_multiplexer_select_vid_channel(u8 channel)
	128	{
	129	return select_i2c_ch_pca9547(channel);
	130	}
	131
5a4d744c YL	132	int config_board_mux(int ctrl_type)
	133	{
	134	u8 reg5;
	135
	136	reg5 = QIXIS_READ(brdcfg[5]);
	137
	138	switch (ctrl_type) {
	139	case MUX_TYPE_SDHC:
	140	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	141	break;
5989df7e HW	142	case MUX_TYPE_DSPI:
	143	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	144	break;
5a4d744c YL	145	default:
	146	printf("Wrong mux interface type\n");
	147	return -1;
	148	}
	149
	150	QIXIS_WRITE(brdcfg[5], reg5);
	151
	152	return 0;
	153	}
	154
5989df7e HW	155	int board_init(void)
	156	{
	157	char *env_hwconfig;
	158	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
931e8751	159	#ifdef CONFIG_FSL_MC_ENET
abc7d0f7	160	u32 __iomem irq_ccsr = (u32 __iomem )ISC_BASE;
931e8751	161	#endif
5989df7e HW	162	u32 val;
	163
	164	init_final_memctl_regs();
	165
	166	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
	167
	168	env_hwconfig = getenv("hwconfig");
	169
	170	if (hwconfig_f("dspi", env_hwconfig) &&
	171	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	172	config_board_mux(MUX_TYPE_DSPI);
	173	else
	174	config_board_mux(MUX_TYPE_SDHC);
	175
	176	#ifdef CONFIG_ENV_IS_NOWHERE
	177	gd->env_addr = (ulong)&default_environment[0];
	178	#endif
	179	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	180
	181	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
	182
931e8751	183	#ifdef CONFIG_FSL_MC_ENET
abc7d0f7 SX	184	/* invert AQR405 IRQ pins polarity */
abc7d0f7 SX	185	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
931e8751	186	#endif
abc7d0f7	187
5989df7e HW	188	return 0;
	189	}
	190
	191	int board_early_init_f(void)
	192	{
	193	fsl_lsch3_early_init_f();
	194	return 0;
	195	}
	196
5a4d744c YL	197	int misc_init_r(void)
	198	{
	199	if (hwconfig("sdhc"))
	200	config_board_mux(MUX_TYPE_SDHC);
	201
ed2530d0 RH	202	if (adjust_vdd(0))
	203	printf("Warning: Adjusting core voltage failed.\n");
	204
215b1fb9 AG	205	#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
	206	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
	207	efi_add_memory_map(gd->bd->bi_dram[2].start,
	208	gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
	209	EFI_RESERVED_MEMORY_TYPE, false);
	210	}
	211	#endif
	212
5a4d744c YL	213	return 0;
	214	}
	215
e2b65ea9 YS	216	void detail_board_ddr_info(void)
	217	{
	218	puts("\nDDR ");
	219	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	220	print_ddr_info(0);
44937214	221	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a	222	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
e2b65ea9 YS	223	puts("\nDP-DDR ");
	224	print_size(gd->bd->bi_dram[2].size, "");
	225	print_ddr_info(CONFIG_DP_DDR_CTRL);
	226	}
44937214	227	#endif
e2b65ea9 YS	228	}
	229
	230	int dram_init(void)
	231	{
	232	gd->ram_size = initdram(0);
	233
	234	return 0;
	235	}
	236
	237	#if defined(CONFIG_ARCH_MISC_INIT)
	238	int arch_misc_init(void)
	239	{
fcfdb6d5 SJ	240	#ifdef CONFIG_FSL_CAAM
	241	sec_init();
	242	#endif
e2b65ea9 YS	243	return 0;
	244	}
	245	#endif
	246
e2b65ea9 YS	247	#ifdef CONFIG_FSL_MC_ENET
	248	void fdt_fixup_board_enet(void *fdt)
	249	{
	250	int offset;
	251
e91f1dec	252	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
e2b65ea9 YS	253
e2b65ea9 YS	254	if (offset < 0)
e91f1dec	255	offset = fdt_path_offset(fdt, "/fsl-mc");
e2b65ea9 YS	256
	257	if (offset < 0) {
	258	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	259	__func__, offset);
	260	return;
	261	}
	262
	263	if (get_mc_boot_status() == 0)
	264	fdt_status_okay(fdt, offset);
	265	else
	266	fdt_status_fail(fdt, offset);
	267	}
b7b8410a AG	268
	269	void board_quiesce_devices(void)
	270	{
	271	fsl_mc_ldpaa_exit(gd->bd);
	272	}
e2b65ea9 YS	273	#endif
	274
	275	#ifdef CONFIG_OF_BOARD_SETUP
	276	int ft_board_setup(void blob, bd_t bd)
	277	{
a2dc818f BS	278	u64 base[CONFIG_NR_DRAM_BANKS];
a2dc818f BS	279	u64 size[CONFIG_NR_DRAM_BANKS];
e2b65ea9 YS	280
	281	ft_cpu_setup(blob, bd);
	282
a2dc818f BS	283	/* fixup DT for the two GPP DDR banks */
	284	base[0] = gd->bd->bi_dram[0].start;
	285	size[0] = gd->bd->bi_dram[0].size;
	286	base[1] = gd->bd->bi_dram[1].start;
	287	size[1] = gd->bd->bi_dram[1].size;
	288
	289	fdt_fixup_memory_banks(blob, base, size, 2);
e2b65ea9	290
a5c289b9	291	fsl_fdt_fixup_dr_usb(blob, bd);
ef53b8c4	292
e2b65ea9 YS	293	#ifdef CONFIG_FSL_MC_ENET
e2b65ea9 YS	294	fdt_fixup_board_enet(blob);
e2b65ea9 YS	295	#endif
	296
	297	return 0;
	298	}
	299	#endif
	300
	301	void qixis_dump_switch(void)
	302	{
	303	int i, nr_of_cfgsw;
	304
	305	QIXIS_WRITE(cms[0], 0x00);
	306	nr_of_cfgsw = QIXIS_READ(cms[1]);
	307
	308	puts("DIP switch settings dump:\n");
	309	for (i = 1; i <= nr_of_cfgsw; i++) {
	310	QIXIS_WRITE(cms[0], i);
	311	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	312	}
	313	}
fc7b3855 YS	314
	315	/*
	316	* Board rev C and earlier has duplicated I2C addresses for 2nd controller.
	317	* Both slots has 0x54, resulting 2nd slot unusable.
	318	*/
	319	void update_spd_address(unsigned int ctrl_num,
	320	unsigned int slot,
	321	unsigned int *addr)
	322	{
	323	u8 sw;
	324
	325	sw = QIXIS_READ(arch);
	326	if ((sw & 0xf) < 0x3) {
	327	if (ctrl_num == 1 && slot == 0)
	328	*addr = SPD_EEPROM_ADDRESS4;
	329	else if (ctrl_num == 1 && slot == 1)
	330	*addr = SPD_EEPROM_ADDRESS3;
	331	}
	332	}