[people/ms/u-boot.git] / board / freescale / ls2080ardb / ls2080ardb.c

/*
 * Copyright (C) 2017 NXP Semiconductors
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
#include <hwconfig.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <efi_loader.h>
#include <i2c.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
#include <fsl_sec.h>

#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
#include "ls2080ardb_qixis.h"
#endif
#include "../common/vid.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
#ifdef CONFIG_FSL_QIXIS
	u8 sw;
#endif
	char buf[15];

	cpu_name(buf);
	printf("Board: %s-RDB, ", buf);

#ifdef CONFIG_TARGET_LS2081ARDB
#ifdef CONFIG_FSL_QIXIS
	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, ", (sw & 0xf) + 'A');

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
	switch (sw) {
	case 0:
		puts("boot from QSPI DEV#0\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
		break;
	case 1:
		puts("boot from QSPI DEV#1\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
		break;
	case 2:
		puts("boot from QSPI EMU\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
		break;
	case 3:
		puts("boot from QSPI EMU\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
		break;
	case 4:
		puts("boot from QSPI DEV#0\n");
		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
		break;
	default:
		printf("invalid setting of SW%u\n", sw);
		break;
	}
#endif
	puts("SERDES1 Reference : ");
	printf("Clock1 = 100MHz ");
	printf("Clock2 = 161.13MHz");
#else
#ifdef CONFIG_FSL_QIXIS
	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x9)
		puts("NAND\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
#endif
	puts("SERDES1 Reference : ");
	printf("Clock1 = 156.25MHz ");
	printf("Clock2 = 156.25MHz");
#endif

	puts("\nSERDES2 Reference : ");
	printf("Clock1 = 100MHz ");
	printf("Clock2 = 100MHz\n");

	return 0;
}

unsigned long get_board_sys_clk(void)
{
#ifdef CONFIG_FSL_QIXIS
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
#endif
	return 100000000;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int i2c_multiplexer_select_vid_channel(u8 channel)
{
	return select_i2c_ch_pca9547(channel);
}

int config_board_mux(int ctrl_type)
{
#ifdef CONFIG_FSL_QIXIS
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);
#endif
	return 0;
}

int board_init(void)
{
#ifdef CONFIG_FSL_MC_ENET
	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif

	init_final_memctl_regs();

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

#ifdef CONFIG_FSL_QIXIS
	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif

#ifdef CONFIG_FSL_MC_ENET
	/* invert AQR405 IRQ pins polarity */
	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif

	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_SYS_I2C_EARLY_INIT
	i2c_early_init_f();
#endif
	fsl_lsch3_early_init_f();
	return 0;
}

int misc_init_r(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 svr = gur_in32(&gur->svr);

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = env_get("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

	/*
	 * LS2081ARDB RevF board has smart voltage translator
	 * which needs to be programmed to enable high speed SD interface
	 * by setting GPIO4_10 output to zero
	 */
#ifdef CONFIG_TARGET_LS2081ARDB
		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
					    in_le32(GPIO4_GPDIR_ADDR)));
		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
					    in_le32(GPIO4_GPDAT_ADDR)));
#endif
	if (hwconfig("sdhc"))
		config_board_mux(MUX_TYPE_SDHC);

	if (adjust_vdd(0))
		printf("Warning: Adjusting core voltage failed.\n");
	/*
	 * Default value of board env is based on filename which is
	 * ls2080ardb. Modify board env for other supported SoCs
	 */
	if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
	    (SVR_SOC_VER(svr) == SVR_LS2048A))
		env_set("board", "ls2088ardb");
	else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
	    (SVR_SOC_VER(svr) == SVR_LS2041A))
		env_set("board", "ls2081ardb");

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
#endif
}

#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/soc/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}

void board_quiesce_devices(void)
{
	fsl_mc_ldpaa_exit(gd->bd);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
void fsl_fdt_fixup_flash(void *fdt)
{
	int offset;

/*
 * IFC and QSPI are muxed on board.
 * So disable IFC node in dts if QSPI is enabled or
 * disable QSPI node in dts in case QSPI is not enabled.
 */
#ifdef CONFIG_FSL_QSPI
	offset = fdt_path_offset(fdt, "/soc/ifc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/ifc");
#else
	offset = fdt_path_offset(fdt, "/soc/quadspi");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/quadspi");
#endif
	if (offset < 0)
		return;

	fdt_status_disabled(fdt, offset);
}

int ft_board_setup(void *blob, bd_t *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

#ifdef CONFIG_RESV_RAM
	/* reduce size if reserved memory is within this bank */
	if (gd->arch.resv_ram >= base[0] &&
	    gd->arch.resv_ram < base[0] + size[0])
		size[0] = gd->arch.resv_ram - base[0];
	else if (gd->arch.resv_ram >= base[1] &&
		 gd->arch.resv_ram < base[1] + size[1])
		size[1] = gd->arch.resv_ram - base[1];
#endif

	fdt_fixup_memory_banks(blob, base, size, 2);

	fsl_fdt_fixup_dr_usb(blob, bd);

	fsl_fdt_fixup_flash(blob);

#ifdef CONFIG_FSL_MC_ENET
	fdt_fixup_board_enet(blob);
#endif

	return 0;
}
#endif

void qixis_dump_switch(void)
{
#ifdef CONFIG_FSL_QIXIS
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
#endif
}

/*
 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 * Both slots has 0x54, resulting 2nd slot unusable.
 */
void update_spd_address(unsigned int ctrl_num,
			unsigned int slot,
			unsigned int *addr)
{
#ifndef CONFIG_TARGET_LS2081ARDB
#ifdef CONFIG_FSL_QIXIS
	u8 sw;

	sw = QIXIS_READ(arch);
	if ((sw & 0xf) < 0x3) {
		if (ctrl_num == 1 && slot == 0)
			*addr = SPD_EEPROM_ADDRESS4;
		else if (ctrl_num == 1 && slot == 1)
			*addr = SPD_EEPROM_ADDRESS3;
	}
#endif
#endif
}
Commit	Line	Data
e2b65ea9	1	/*
5193405a	2	* Copyright (C) 2017 NXP Semiconductors
e2b65ea9 YS	3	* Copyright 2015 Freescale Semiconductor
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7	#include <common.h>
	8	#include <malloc.h>
	9	#include <errno.h>
	10	#include <netdev.h>
	11	#include <fsl_ifc.h>
	12	#include <fsl_ddr.h>
	13	#include <asm/io.h>
5a4d744c	14	#include <hwconfig.h>
e2b65ea9 YS	15	#include <fdt_support.h>
e2b65ea9 YS	16	#include <libfdt.h>
e2b65ea9 YS	17	#include <fsl-mc/fsl_mc.h>
e2b65ea9 YS	18	#include <environment.h>
215b1fb9	19	#include <efi_loader.h>
e2b65ea9	20	#include <i2c.h>
4961eafc	21	#include <asm/arch/mmu.h>
9f3183d2	22	#include <asm/arch/soc.h>
54ad7b5a	23	#include <asm/arch/ppa.h>
fcfdb6d5	24	#include <fsl_sec.h>
e2b65ea9	25
d1418c15	26	#ifdef CONFIG_FSL_QIXIS
e2b65ea9	27	#include "../common/qixis.h"
44937214	28	#include "ls2080ardb_qixis.h"
d1418c15	29	#endif
ed2530d0	30	#include "../common/vid.h"
e2b65ea9	31
5a4d744c	32	#define PIN_MUX_SEL_SDHC 0x00
5989df7e	33	#define PIN_MUX_SEL_DSPI 0x0a
5a4d744c YL	34
5a4d744c YL	35	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
e2b65ea9 YS	36	DECLARE_GLOBAL_DATA_PTR;
e2b65ea9 YS	37
5a4d744c YL	38	enum {
5a4d744c YL	39	MUX_TYPE_SDHC,
5989df7e	40	MUX_TYPE_DSPI,
5a4d744c YL	41	};
5a4d744c YL	42
e2b65ea9 YS	43	unsigned long long get_qixis_addr(void)
	44	{
	45	unsigned long long addr;
	46
	47	if (gd->flags & GD_FLG_RELOC)
	48	addr = QIXIS_BASE_PHYS;
	49	else
	50	addr = QIXIS_BASE_PHYS_EARLY;
	51
	52	/*
	53	* IFC address under 256MB is mapped to 0x30000000, any address above
	54	* is mapped to 0x5_10000000 up to 4GB.
	55	*/
	56	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	57
	58	return addr;
	59	}
	60
	61	int checkboard(void)
	62	{
d1418c15	63	#ifdef CONFIG_FSL_QIXIS
e2b65ea9	64	u8 sw;
d1418c15	65	#endif
ff1b8e3f PK	66	char buf[15];
	67
	68	cpu_name(buf);
	69	printf("Board: %s-RDB, ", buf);
e2b65ea9	70
3049a583 PJ	71	#ifdef CONFIG_TARGET_LS2081ARDB
	72	#ifdef CONFIG_FSL_QIXIS
	73	sw = QIXIS_READ(arch);
	74	printf("Board Arch: V%d, ", sw >> 4);
	75	printf("Board version: %c, ", (sw & 0xf) + 'A');
	76
	77	sw = QIXIS_READ(brdcfg[0]);
	78	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
	79	switch (sw) {
	80	case 0:
	81	puts("boot from QSPI DEV#0\n");
	82	puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
	83	break;
	84	case 1:
	85	puts("boot from QSPI DEV#1\n");
	86	puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
	87	break;
	88	case 2:
	89	puts("boot from QSPI EMU\n");
	90	puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
	91	break;
	92	case 3:
	93	puts("boot from QSPI EMU\n");
	94	puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
	95	break;
	96	case 4:
	97	puts("boot from QSPI DEV#0\n");
	98	puts("QSPI_CSA_1 mapped to QSPI EMU\n");
	99	break;
	100	default:
	101	printf("invalid setting of SW%u\n", sw);
	102	break;
	103	}
	104	#endif
	105	puts("SERDES1 Reference : ");
	106	printf("Clock1 = 100MHz ");
	107	printf("Clock2 = 161.13MHz");
	108	#else
d1418c15	109	#ifdef CONFIG_FSL_QIXIS
e2b65ea9	110	sw = QIXIS_READ(arch);
e2b65ea9	111	printf("Board Arch: V%d, ", sw >> 4);
27df54b1	112	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
e2b65ea9 YS	113
	114	sw = QIXIS_READ(brdcfg[0]);
	115	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	116
	117	if (sw < 0x8)
	118	printf("vBank: %d\n", sw);
	119	else if (sw == 0x9)
	120	puts("NAND\n");
	121	else
	122	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	123
	124	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
d1418c15	125	#endif
e2b65ea9 YS	126	puts("SERDES1 Reference : ");
	127	printf("Clock1 = 156.25MHz ");
	128	printf("Clock2 = 156.25MHz");
3049a583	129	#endif
e2b65ea9 YS	130
	131	puts("\nSERDES2 Reference : ");
	132	printf("Clock1 = 100MHz ");
	133	printf("Clock2 = 100MHz\n");
	134
	135	return 0;
	136	}
	137
	138	unsigned long get_board_sys_clk(void)
	139	{
d1418c15	140	#ifdef CONFIG_FSL_QIXIS
e2b65ea9 YS	141	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	142
	143	switch (sysclk_conf & 0x0F) {
	144	case QIXIS_SYSCLK_83:
	145	return 83333333;
	146	case QIXIS_SYSCLK_100:
	147	return 100000000;
	148	case QIXIS_SYSCLK_125:
	149	return 125000000;
	150	case QIXIS_SYSCLK_133:
	151	return 133333333;
	152	case QIXIS_SYSCLK_150:
	153	return 150000000;
	154	case QIXIS_SYSCLK_160:
	155	return 160000000;
	156	case QIXIS_SYSCLK_166:
	157	return 166666666;
	158	}
d1418c15 PJ	159	#endif
d1418c15 PJ	160	return 100000000;
e2b65ea9 YS	161	}
	162
	163	int select_i2c_ch_pca9547(u8 ch)
	164	{
	165	int ret;
	166
	167	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	168	if (ret) {
	169	puts("PCA: failed to select proper channel\n");
	170	return ret;
	171	}
	172
	173	return 0;
	174	}
	175
ed2530d0 RH	176	int i2c_multiplexer_select_vid_channel(u8 channel)
	177	{
	178	return select_i2c_ch_pca9547(channel);
	179	}
	180
5a4d744c YL	181	int config_board_mux(int ctrl_type)
5a4d744c YL	182	{
d1418c15	183	#ifdef CONFIG_FSL_QIXIS
5a4d744c YL	184	u8 reg5;
	185
	186	reg5 = QIXIS_READ(brdcfg[5]);
	187
	188	switch (ctrl_type) {
	189	case MUX_TYPE_SDHC:
	190	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	191	break;
5989df7e HW	192	case MUX_TYPE_DSPI:
	193	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	194	break;
5a4d744c YL	195	default:
	196	printf("Wrong mux interface type\n");
	197	return -1;
	198	}
	199
	200	QIXIS_WRITE(brdcfg[5], reg5);
d1418c15	201	#endif
5a4d744c YL	202	return 0;
	203	}
	204
5989df7e HW	205	int board_init(void)
5989df7e HW	206	{
931e8751	207	#ifdef CONFIG_FSL_MC_ENET
abc7d0f7	208	u32 __iomem irq_ccsr = (u32 __iomem )ISC_BASE;
931e8751	209	#endif
5989df7e HW	210
	211	init_final_memctl_regs();
	212
5989df7e HW	213	#ifdef CONFIG_ENV_IS_NOWHERE
	214	gd->env_addr = (ulong)&default_environment[0];
	215	#endif
	216	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	217
d1418c15	218	#ifdef CONFIG_FSL_QIXIS
5989df7e	219	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
d1418c15	220	#endif
15e7c681 UA	221
	222	#ifdef CONFIG_FSL_CAAM
	223	sec_init();
	224	#endif
54ad7b5a SK	225	#ifdef CONFIG_FSL_LS_PPA
	226	ppa_init();
	227	#endif
	228
931e8751	229	#ifdef CONFIG_FSL_MC_ENET
abc7d0f7 SX	230	/* invert AQR405 IRQ pins polarity */
abc7d0f7 SX	231	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
931e8751	232	#endif
a8c6fd4e UA	233	#ifdef CONFIG_FSL_CAAM
	234	sec_init();
	235	#endif
abc7d0f7	236
5989df7e HW	237	return 0;
	238	}
	239
	240	int board_early_init_f(void)
	241	{
3049a583 PJ	242	#ifdef CONFIG_SYS_I2C_EARLY_INIT
	243	i2c_early_init_f();
	244	#endif
5989df7e HW	245	fsl_lsch3_early_init_f();
	246	return 0;
	247	}
	248
5a4d744c YL	249	int misc_init_r(void)
5a4d744c YL	250	{
263536a6 SK	251	char *env_hwconfig;
	252	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	253	u32 val;
b5dfd475 PJ	254	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
b5dfd475 PJ	255	u32 svr = gur_in32(&gur->svr);
263536a6 SK	256
	257	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
	258
00caae6d	259	env_hwconfig = env_get("hwconfig");
263536a6 SK	260
	261	if (hwconfig_f("dspi", env_hwconfig) &&
	262	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	263	config_board_mux(MUX_TYPE_DSPI);
	264	else
	265	config_board_mux(MUX_TYPE_SDHC);
	266
5193405a	267	/*
6cc914ef	268	* LS2081ARDB RevF board has smart voltage translator
5193405a PJ	269	* which needs to be programmed to enable high speed SD interface
	270	* by setting GPIO4_10 output to zero
	271	*/
6cc914ef	272	#ifdef CONFIG_TARGET_LS2081ARDB
5193405a PJ	273	out_le32(GPIO4_GPDIR_ADDR, (1 << 21 \|
	274	in_le32(GPIO4_GPDIR_ADDR)));
	275	out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
	276	in_le32(GPIO4_GPDAT_ADDR)));
3049a583	277	#endif
5a4d744c YL	278	if (hwconfig("sdhc"))
	279	config_board_mux(MUX_TYPE_SDHC);
	280
ed2530d0 RH	281	if (adjust_vdd(0))
ed2530d0 RH	282	printf("Warning: Adjusting core voltage failed.\n");
b5dfd475 PJ	283	/*
	284	* Default value of board env is based on filename which is
	285	* ls2080ardb. Modify board env for other supported SoCs
	286	*/
	287	if ((SVR_SOC_VER(svr) == SVR_LS2088A) \|\|
	288	(SVR_SOC_VER(svr) == SVR_LS2048A))
	289	env_set("board", "ls2088ardb");
	290	else if ((SVR_SOC_VER(svr) == SVR_LS2081A) \|\|
	291	(SVR_SOC_VER(svr) == SVR_LS2041A))
	292	env_set("board", "ls2081ardb");
ed2530d0	293
5a4d744c YL	294	return 0;
	295	}
	296
e2b65ea9 YS	297	void detail_board_ddr_info(void)
	298	{
	299	puts("\nDDR ");
	300	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	301	print_ddr_info(0);
44937214	302	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a	303	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
e2b65ea9 YS	304	puts("\nDP-DDR ");
	305	print_size(gd->bd->bi_dram[2].size, "");
	306	print_ddr_info(CONFIG_DP_DDR_CTRL);
	307	}
44937214	308	#endif
e2b65ea9 YS	309	}
e2b65ea9 YS	310
e2b65ea9 YS	311	#if defined(CONFIG_ARCH_MISC_INIT)
	312	int arch_misc_init(void)
	313	{
e2b65ea9 YS	314	return 0;
	315	}
	316	#endif
	317
e2b65ea9 YS	318	#ifdef CONFIG_FSL_MC_ENET
	319	void fdt_fixup_board_enet(void *fdt)
	320	{
	321	int offset;
	322
e91f1dec	323	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
e2b65ea9 YS	324
e2b65ea9 YS	325	if (offset < 0)
e91f1dec	326	offset = fdt_path_offset(fdt, "/fsl-mc");
e2b65ea9 YS	327
	328	if (offset < 0) {
	329	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	330	__func__, offset);
	331	return;
	332	}
	333
70a131eb	334	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
e2b65ea9 YS	335	fdt_status_okay(fdt, offset);
	336	else
	337	fdt_status_fail(fdt, offset);
	338	}
b7b8410a AG	339
	340	void board_quiesce_devices(void)
	341	{
	342	fsl_mc_ldpaa_exit(gd->bd);
	343	}
e2b65ea9 YS	344	#endif
	345
	346	#ifdef CONFIG_OF_BOARD_SETUP
7794d9ab SK	347	void fsl_fdt_fixup_flash(void *fdt)
	348	{
	349	int offset;
	350
	351	/*
	352	* IFC and QSPI are muxed on board.
	353	* So disable IFC node in dts if QSPI is enabled or
	354	* disable QSPI node in dts in case QSPI is not enabled.
	355	*/
	356	#ifdef CONFIG_FSL_QSPI
	357	offset = fdt_path_offset(fdt, "/soc/ifc");
	358
	359	if (offset < 0)
	360	offset = fdt_path_offset(fdt, "/ifc");
	361	#else
	362	offset = fdt_path_offset(fdt, "/soc/quadspi");
	363
	364	if (offset < 0)
	365	offset = fdt_path_offset(fdt, "/quadspi");
	366	#endif
	367	if (offset < 0)
	368	return;
	369
	370	fdt_status_disabled(fdt, offset);
	371	}
	372
e2b65ea9 YS	373	int ft_board_setup(void blob, bd_t bd)
e2b65ea9 YS	374	{
a2dc818f BS	375	u64 base[CONFIG_NR_DRAM_BANKS];
a2dc818f BS	376	u64 size[CONFIG_NR_DRAM_BANKS];
e2b65ea9 YS	377
	378	ft_cpu_setup(blob, bd);
	379
a2dc818f BS	380	/* fixup DT for the two GPP DDR banks */
	381	base[0] = gd->bd->bi_dram[0].start;
	382	size[0] = gd->bd->bi_dram[0].size;
	383	base[1] = gd->bd->bi_dram[1].start;
	384	size[1] = gd->bd->bi_dram[1].size;
	385
36cc0de0 YS	386	#ifdef CONFIG_RESV_RAM
	387	/* reduce size if reserved memory is within this bank */
	388	if (gd->arch.resv_ram >= base[0] &&
	389	gd->arch.resv_ram < base[0] + size[0])
	390	size[0] = gd->arch.resv_ram - base[0];
	391	else if (gd->arch.resv_ram >= base[1] &&
	392	gd->arch.resv_ram < base[1] + size[1])
	393	size[1] = gd->arch.resv_ram - base[1];
	394	#endif
	395
a2dc818f	396	fdt_fixup_memory_banks(blob, base, size, 2);
e2b65ea9	397
a5c289b9	398	fsl_fdt_fixup_dr_usb(blob, bd);
ef53b8c4	399
7794d9ab SK	400	fsl_fdt_fixup_flash(blob);
7794d9ab SK	401
e2b65ea9 YS	402	#ifdef CONFIG_FSL_MC_ENET
e2b65ea9 YS	403	fdt_fixup_board_enet(blob);
e2b65ea9 YS	404	#endif
	405
	406	return 0;
	407	}
	408	#endif
	409
	410	void qixis_dump_switch(void)
	411	{
d1418c15	412	#ifdef CONFIG_FSL_QIXIS
e2b65ea9 YS	413	int i, nr_of_cfgsw;
	414
	415	QIXIS_WRITE(cms[0], 0x00);
	416	nr_of_cfgsw = QIXIS_READ(cms[1]);
	417
	418	puts("DIP switch settings dump:\n");
	419	for (i = 1; i <= nr_of_cfgsw; i++) {
	420	QIXIS_WRITE(cms[0], i);
	421	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	422	}
d1418c15	423	#endif
e2b65ea9	424	}
fc7b3855 YS	425
	426	/*
	427	* Board rev C and earlier has duplicated I2C addresses for 2nd controller.
	428	* Both slots has 0x54, resulting 2nd slot unusable.
	429	*/
	430	void update_spd_address(unsigned int ctrl_num,
	431	unsigned int slot,
	432	unsigned int *addr)
	433	{
3049a583	434	#ifndef CONFIG_TARGET_LS2081ARDB
d1418c15	435	#ifdef CONFIG_FSL_QIXIS
fc7b3855 YS	436	u8 sw;
	437
	438	sw = QIXIS_READ(arch);
	439	if ((sw & 0xf) < 0x3) {
	440	if (ctrl_num == 1 && slot == 0)
	441	*addr = SPD_EEPROM_ADDRESS4;
	442	else if (ctrl_num == 1 && slot == 1)
	443	*addr = SPD_EEPROM_ADDRESS3;
	444	}
d1418c15	445	#endif
3049a583	446	#endif
fc7b3855	447	}