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1 | /* |
2 | * (C) Copyright 2000-2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
4e5ca3eb WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
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9 | #include <asm/immap.h> |
10 | ||
11 | DECLARE_GLOBAL_DATA_PTR; | |
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12 | |
13 | int checkboard (void) | |
14 | { | |
f28e1bd9 | 15 | puts ("Board: Freescale M5282EVB Evaluation Board\n"); |
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16 | return 0; |
17 | } | |
18 | ||
088454cd | 19 | int initdram(void) |
4e5ca3eb | 20 | { |
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21 | u32 dramsize, i, dramclk; |
22 | ||
6d0f6bcf | 23 | dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; |
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24 | for (i = 0x13; i < 0x20; i++) { |
25 | if (dramsize == (1 << i)) | |
26 | break; | |
27 | } | |
28 | i--; | |
29 | ||
30 | if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) | |
31 | { | |
6d0f6bcf | 32 | dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); |
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33 | |
34 | /* Initialize DRAM Control Register: DCR */ | |
35 | MCFSDRAMC_DCR = (0 | |
36 | | MCFSDRAMC_DCR_RTIM_6 | |
37 | | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); | |
4cb4e654 | 38 | asm("nop"); |
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39 | |
40 | /* Initialize DACR0 */ | |
41 | MCFSDRAMC_DACR0 = (0 | |
6d0f6bcf | 42 | | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE) |
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43 | | MCFSDRAMC_DACR_CASL(1) |
44 | | MCFSDRAMC_DACR_CBM(3) | |
45 | | MCFSDRAMC_DACR_PS_32); | |
4cb4e654 | 46 | asm("nop"); |
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47 | |
48 | /* Initialize DMR0 */ | |
49 | MCFSDRAMC_DMR0 = (0 | |
50 | | ((dramsize - 1) & 0xFFFC0000) | |
51 | | MCFSDRAMC_DMR_V); | |
4cb4e654 | 52 | asm("nop"); |
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53 | |
54 | /* Set IP (bit 3) in DACR */ | |
55 | MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; | |
4cb4e654 | 56 | asm("nop"); |
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57 | |
58 | /* Wait 30ns to allow banks to precharge */ | |
59 | for (i = 0; i < 5; i++) { | |
60 | asm ("nop"); | |
61 | } | |
62 | ||
63 | /* Write to this block to initiate precharge */ | |
6d0f6bcf | 64 | *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; |
4cb4e654 | 65 | asm("nop"); |
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66 | |
67 | /* Set RE (bit 15) in DACR */ | |
68 | MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; | |
4cb4e654 | 69 | asm("nop"); |
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70 | |
71 | /* Wait for at least 8 auto refresh cycles to occur */ | |
72 | for (i = 0; i < 2000; i++) { | |
73 | asm(" nop"); | |
74 | } | |
75 | ||
76 | /* Finish the configuration by issuing the IMRS. */ | |
77 | MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; | |
4cb4e654 | 78 | asm("nop"); |
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79 | |
80 | /* Write to the SDRAM Mode Register */ | |
6d0f6bcf | 81 | *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; |
f28e1bd9 | 82 | } |
088454cd SG |
83 | gd->ram_size = dramsize; |
84 | ||
85 | return 0; | |
4e5ca3eb | 86 | } |