[people/ms/u-boot.git] / board / freescale / m547xevb / m547xevb.c

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	puts("Board: ");
	puts("Freescale FireEngine 5475 EVB\n");
	return 0;
};

int initdram(void)
{
	siu_t *siu = (siu_t *) (MMAP_SIU);
	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
	u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
	u32 temp;
#endif

	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);

	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
	for (i = 0x13; i < 0x20; i++) {
		if (dramsize == (1 << i))
			break;
	}
	i--;
	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);

#ifdef CONFIG_SYS_DRAMSZ1
	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
	for (i = 0x13; i < 0x20; i++) {
		if (temp == (1 << i))
			break;
	}
	i--;
	dramsize += temp;
	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif

	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);

	/* Issue PALL */
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);

	/* Issue LEMR */
	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);

	udelay(500);

	/* Issue PALL */
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);

	/* Perform two refresh cycles */
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);

	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);

	out_be32(&sdram->ctrl,
		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);

	udelay(100);

	gd->ram_size = dramsize;

	return 0;
};

int testdram(void)
{
	/* TODO: XXX XXX XXX */
	printf("DRAM test not implemented!\n");

	return (0);
}

#if defined(CONFIG_PCI)
/*
 * Initialize PCI devices, report devices found.
 */
static struct pci_controller hose;
extern void pci_mcf547x_8x_init(struct pci_controller *hose);

void pci_init_board(void)
{
	pci_mcf547x_8x_init(&hose);
}
#endif				/* CONFIG_PCI */
Commit	Line	Data
1aee1111 TL	1	/*
	2	* (C) Copyright 2000-2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
a4110eec	5	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
1aee1111 TL	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
1aee1111 TL	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
1aee1111 TL	9	*/
	10
	11	#include <config.h>
	12	#include <common.h>
	13	#include <pci.h>
	14	#include <asm/immap.h>
a4110eec	15	#include <asm/io.h>
1aee1111 TL	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
	19	int checkboard(void)
	20	{
	21	puts("Board: ");
	22	puts("Freescale FireEngine 5475 EVB\n");
	23	return 0;
	24	};
	25
088454cd	26	int initdram(void)
1aee1111	27	{
a4110eec AW	28	siu_t siu = (siu_t ) (MMAP_SIU);
a4110eec AW	29	sdram_t sdram = (sdram_t )(MMAP_SDRAM);
1aee1111	30	u32 dramsize, i;
6d0f6bcf	31	#ifdef CONFIG_SYS_DRAMSZ1
77878f16 TL	32	u32 temp;
77878f16 TL	33	#endif
1aee1111	34
a4110eec	35	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
1aee1111	36
6d0f6bcf	37	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
1aee1111 TL	38	for (i = 0x13; i < 0x20; i++) {
	39	if (dramsize == (1 << i))
	40	break;
	41	}
	42	i--;
a4110eec	43	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE \| i);
1aee1111	44
6d0f6bcf JCPV	45	#ifdef CONFIG_SYS_DRAMSZ1
6d0f6bcf JCPV	46	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
1aee1111 TL	47	for (i = 0x13; i < 0x20; i++) {
	48	if (temp == (1 << i))
	49	break;
	50	}
	51	i--;
	52	dramsize += temp;
a4110eec	53	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) \| i);
1aee1111 TL	54	#endif
1aee1111 TL	55
a4110eec AW	56	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
a4110eec AW	57	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
1aee1111 TL	58
1aee1111 TL	59	/* Issue PALL */
a4110eec	60	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 2);
1aee1111 TL	61
1aee1111 TL	62	/* Issue LEMR */
a4110eec AW	63	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
a4110eec AW	64	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE \| 0x04000000);
1aee1111 TL	65
	66	udelay(500);
	67
	68	/* Issue PALL */
a4110eec	69	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 2);
1aee1111 TL	70
1aee1111 TL	71	/* Perform two refresh cycles */
a4110eec AW	72	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 4);
a4110eec AW	73	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 4);
1aee1111	74
a4110eec	75	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
1aee1111	76
a4110eec AW	77	out_be32(&sdram->ctrl,
a4110eec AW	78	(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) \| 0x10000F00);
1aee1111 TL	79
	80	udelay(100);
	81
088454cd SG	82	gd->ram_size = dramsize;
	83
	84	return 0;
1aee1111 TL	85	};
	86
	87	int testdram(void)
	88	{
	89	/* TODO: XXX XXX XXX */
	90	printf("DRAM test not implemented!\n");
	91
	92	return (0);
	93	}
	94
	95	#if defined(CONFIG_PCI)
	96	/*
	97	* Initialize PCI devices, report devices found.
	98	*/
	99	static struct pci_controller hose;
	100	extern void pci_mcf547x_8x_init(struct pci_controller *hose);
	101
	102	void pci_init_board(void)
	103	{
	104	pci_mcf547x_8x_init(&hose);
	105	}
	106	#endif /* CONFIG_PCI */