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board_f: Drop return value from initdram()
[people/ms/u-boot.git] / board / freescale / mpc5121ads / mpc5121ads.c
CommitLineData
8993e54b 1/*
843efb11 2 * (C) Copyright 2007-2009 DENX Software Engineering
8993e54b 3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
8993e54b
RJ		 5 */
6
7#include <common.h>
8993e54b
RJ		 8#include <asm/bitops.h>
9#include <command.h>
843efb11 10#include <asm/io.h>
8a490422 11#include <asm/processor.h>
7629f1c0 12#include <asm/mpc512x.h>
e343ab83 13#include <fdt_support.h>
f31c49db
MM		 14#ifdef CONFIG_MISC_INIT_R
15#include <i2c.h>
16#endif
a5aa3998 17#include <net.h>
9b55a253 18
229549a5
SR		 19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21
70a4da45
RK		 22DECLARE_GLOBAL_DATA_PTR;
23
229549a5
SR		 24void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
25
26/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
27extern int mpc5121_nfc_chip;
28
29/* Control chips select signal on MPC5121ADS board */
30void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
31{
32 unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
33 u8 v;
34
35 v = in_8(csreg);
36 v |= 0x0F;
37
38 if (chip >= 0) {
39 __mpc5121_nfc_select_chip(mtd, 0);
40 v &= ~(1 << mpc5121_nfc_chip);
41 } else {
42 __mpc5121_nfc_select_chip(mtd, -1);
43 }
44
45 out_8(csreg, v);
46}
8993e54b 47
7629f1c0 48int board_early_init_f(void)
8993e54b 49{
8993e54b
RJ		 50 /*
51 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
52 *
53 * Without this the flash identification routine fails, as it needs to issue
54 * write commands in order to establish the device ID.
55 */
8993e54b 56
812493ad 57#ifdef CONFIG_MPC5121ADS_REV2
843efb11 58 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
f31c49db 59#else
843efb11
WD		 60 if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
61 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
f31c49db
MM		 62 } else {
63 /* running from Backup flash */
843efb11 64 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
f31c49db
MM		 65 }
66#endif
8993e54b
RJ		 67 return 0;
68}
69
a5aa3998
MS		 70int is_micron(void){
71
72 ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
73 uchar macaddr[6];
74 u32 brddate, macchk, ismicron;
75
76 /*
77 * MAC address has serial number with date of manufacture
78 * Boards made before Nov-08 #1180 use Micron memory;
79 * 001e59 is the STx vendor #
80 * Default is Elpida since it works for both but is slightly slower
81 */
82 ismicron = 0;
83 if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
84 brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
85 macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
86 debug("brddate = %d\n\t", brddate);
87
88 if (macchk == 0x001e59 && brddate <= 8111180)
89 ismicron = 1;
90 } else if (brd_rev < 0x400) {
91 ismicron = 1;
92 }
93 debug("Using %s Memory settings\n\t",
94 ismicron ? "Micron" : "Elpida");
95 return(ismicron);
96}
97
088454cd 98int initdram(void)
8993e54b
RJ		 99{
100 u32 msize = 0;
a5aa3998
MS		 101 /*
102 * Elpida MDDRC and initialization settings are an alternative
103 * to the Default Micron ones for all but the earliest Rev 4 boards
104 */
da01f534
WD		 105 ddr512x_config_t elpida_mddrc_config = {
106 .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
107 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
108 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
109 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
a5aa3998
MS		 110 };
111
112 u32 elpida_init_sequence[] = {
113 CONFIG_SYS_DDRCMD_NOP,
114 CONFIG_SYS_DDRCMD_NOP,
115 CONFIG_SYS_DDRCMD_NOP,
116 CONFIG_SYS_DDRCMD_NOP,
117 CONFIG_SYS_DDRCMD_NOP,
118 CONFIG_SYS_DDRCMD_NOP,
119 CONFIG_SYS_DDRCMD_NOP,
120 CONFIG_SYS_DDRCMD_NOP,
121 CONFIG_SYS_DDRCMD_NOP,
122 CONFIG_SYS_DDRCMD_NOP,
123 CONFIG_SYS_DDRCMD_PCHG_ALL,
124 CONFIG_SYS_DDRCMD_NOP,
125 CONFIG_SYS_DDRCMD_RFSH,
126 CONFIG_SYS_DDRCMD_NOP,
127 CONFIG_SYS_DDRCMD_RFSH,
128 CONFIG_SYS_DDRCMD_NOP,
129 CONFIG_SYS_DDRCMD_EM2,
130 CONFIG_SYS_DDRCMD_EM3,
131 CONFIG_SYS_DDRCMD_EN_DLL,
132 CONFIG_SYS_ELPIDA_RES_DLL,
133 CONFIG_SYS_DDRCMD_PCHG_ALL,
134 CONFIG_SYS_DDRCMD_RFSH,
135 CONFIG_SYS_DDRCMD_RFSH,
136 CONFIG_SYS_DDRCMD_RFSH,
137 CONFIG_SYS_ELPIDA_INIT_DEV_OP,
138 CONFIG_SYS_DDRCMD_NOP,
139 CONFIG_SYS_DDRCMD_NOP,
140 CONFIG_SYS_DDRCMD_NOP,
141 CONFIG_SYS_DDRCMD_NOP,
142 CONFIG_SYS_DDRCMD_NOP,
143 CONFIG_SYS_DDRCMD_NOP,
144 CONFIG_SYS_DDRCMD_NOP,
145 CONFIG_SYS_DDRCMD_NOP,
146 CONFIG_SYS_DDRCMD_NOP,
147 CONFIG_SYS_DDRCMD_NOP,
148 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
149 CONFIG_SYS_ELPIDA_OCD_EXIT,
150 CONFIG_SYS_DDRCMD_NOP,
151 CONFIG_SYS_DDRCMD_NOP,
152 CONFIG_SYS_DDRCMD_NOP,
153 CONFIG_SYS_DDRCMD_NOP,
154 CONFIG_SYS_DDRCMD_NOP,
155 CONFIG_SYS_DDRCMD_NOP,
156 CONFIG_SYS_DDRCMD_NOP,
157 CONFIG_SYS_DDRCMD_NOP,
158 CONFIG_SYS_DDRCMD_NOP,
159 CONFIG_SYS_DDRCMD_NOP
160 };
161
162 if (is_micron()) {
163 msize = fixed_sdram(NULL, NULL, 0);
164 } else {
da01f534 165 msize = fixed_sdram(&elpida_mddrc_config,
a5aa3998
MS		 166 elpida_init_sequence,
167 sizeof(elpida_init_sequence)/sizeof(u32));
168 }
8993e54b 169
088454cd
SG		 170 gd->ram_size = msize;
171
172 return 0;
8993e54b
RJ		 173}
174
0e1bad47
YS		 175int misc_init_r(void)
176{
177 u8 tmp_val;
178
179 /* Using this for DIU init before the driver in linux takes over
180 * Enable the TFP410 Encoder (I2C address 0x38)
181 */
182
183 i2c_set_bus_num(2);
184 tmp_val = 0xBF;
185 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
186 /* Verify if enabled */
187 tmp_val = 0;
188 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
dffe06fa 189 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
0e1bad47
YS		 190
191 tmp_val = 0x10;
192 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
193 /* Verify if enabled */
194 tmp_val = 0;
195 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
dffe06fa 196 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
0e1bad47 197
0e1bad47
YS		 198 return 0;
199}
72601d04 200
6689484c
KJ		 201static iopin_t ioregs_init[] = {
202 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
203 {
843efb11 204 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
6689484c
KJ		 205 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
206 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
207 },
208 /* Set highest Slew on 9 PATA pins */
209 {
843efb11 210 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
6689484c
KJ		 211 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
212 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
213 },
214 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
215 {
843efb11 216 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
6689484c
KJ		 217 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
218 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
219 },
220 /* FUNC1=SPDIF_TXCLK */
221 {
843efb11 222 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
6689484c
KJ		 223 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
224 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
225 },
226 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
227 {
843efb11 228 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
6689484c
KJ		 229 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
230 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
231 },
232 /* FUNC2=DIU CLK */
233 {
843efb11 234 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
6689484c
KJ		 235 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
236 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
237 },
238 /* FUNC2=DIU_HSYNC */
239 {
843efb11 240 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
6689484c
KJ		 241 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
242 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
243 },
244 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
245 {
843efb11 246 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
6689484c
KJ		 247 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
248 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
249 }
250};
0e1bad47 251
14d19cd1
JR		 252static iopin_t rev2_silicon_pci_ioregs_init[] = {
253 /* FUNC0=PCI Sets next 54 to PCI pads */
254 {
843efb11 255 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
14d19cd1
JR		 256 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
257 }
258};
259
8993e54b
RJ		 260int checkboard (void)
261{
6d0f6bcf
JCPV		 262 ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
263 uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
14d19cd1 264 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
843efb11 265 u32 spridr = in_be32(&im->sysconf.spridr);
8993e54b 266
812493ad 267 printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
b1b54e35 268 brd_rev, cpld_rev);
72601d04 269
16bee7b0 270 /* initialize function mux & slew rate IO inter alia on IO Pins */
72601d04 271 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
6689484c 272
843efb11 273 if (SVR_MJREV (spridr) >= 2)
14d19cd1 274 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
51b67d06 275
8993e54b
RJ		 276 return 0;
277}
281ff9a4 278
7ffe3cd6 279#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0 280int ft_board_setup(void *blob, bd_t *bd)
281ff9a4
GB		 281{
282 ft_cpu_setup(blob, bd);
e895a4b0
SG		 283
284 return 0;
281ff9a4 285}
7ffe3cd6 286#endif /* CONFIG_OF_BOARD_SETUP */
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