[people/ms/u-boot.git] / board / freescale / mpc8313erdb / mpc8313erdb.c

/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
 *
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <ns16550.h>
#include <nand.h>
#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
#include <asm/gpio.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;

	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
		gd->flags |= GD_FLG_SILENT;
#endif
#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
	mpc83xx_gpio_init_f();
#endif

	return 0;
}

int board_early_init_r(void)
{
#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
	mpc83xx_gpio_init_r();
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: Freescale MPC8313ERDB\n");
	return 0;
}

#ifndef CONFIG_SPL_BUILD
static struct pci_region pci_regions[] = {
	{
		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
		.size = CONFIG_SYS_PCI1_MEM_SIZE,
		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
		.flags = PCI_REGION_MEM
	},
	{
		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
		.size = CONFIG_SYS_PCI1_IO_SIZE,
		.flags = PCI_REGION_IO
	}
};

void pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	struct pci_region *reg[] = { pci_regions };

	/* Enable all 3 PCI_CLK_OUTPUTs. */
	clk->occr |= 0xe0000000;

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;

	mpc83xx_pci_init(1, reg);
}

/*
 * Miscellaneous late-boot configurations
 *
 * If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
	int rc = 0;

#ifdef CONFIG_VSC7385_IMAGE
	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
		CONFIG_VSC7385_IMAGE_SIZE)) {
		puts("Failure uploading VSC7385 microcode.\n");
		rc = 1;
	}
#endif

	return rc;
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif

	return 0;
}
#endif
#else /* CONFIG_SPL_BUILD */
void board_init_f(ulong bootflag)
{
	board_early_init_f();
	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
	puts("NAND boot... ");
	timer_init();
	initdram(0);
	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
		      CONFIG_SYS_NAND_U_BOOT_RELOC);
}

void board_init_r(gd_t *gd, ulong dest_addr)
{
	nand_boot();
}

void putc(char c)
{
	if (gd->flags & GD_FLG_SILENT)
		return;

	if (c == '\n')
		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');

	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif
Commit	Line	Data
96b8a054 SW	1	/*
	2	* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
	3	*
	4	* Author: Scott Wood <scottwood@freescale.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
96b8a054 SW	7	*/
	8
	9	#include <common.h>
b3458d2c	10	#if defined(CONFIG_OF_LIBFDT)
3fde9e8b KP	11	#include <libfdt.h>
3fde9e8b KP	12	#endif
96b8a054 SW	13	#include <pci.h>
96b8a054 SW	14	#include <mpc83xx.h>
89c7784e	15	#include <vsc7385.h>
e4c09508 SW	16	#include <ns16550.h>
e4c09508 SW	17	#include <nand.h>
22f4442d	18	#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
0eaf8f9e JH	19	#include <asm/gpio.h>
0eaf8f9e JH	20	#endif
96b8a054 SW	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
	24	int board_early_init_f(void)
	25	{
6d0f6bcf JCPV	26	#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
6d0f6bcf JCPV	27	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
96b8a054 SW	28
	29	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
	30	gd->flags \|= GD_FLG_SILENT;
	31	#endif
22f4442d	32	#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
0eaf8f9e JH	33	mpc83xx_gpio_init_f();
	34	#endif
	35
	36	return 0;
	37	}
	38
	39	int board_early_init_r(void)
	40	{
22f4442d	41	#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
0eaf8f9e JH	42	mpc83xx_gpio_init_r();
0eaf8f9e JH	43	#endif
96b8a054 SW	44
	45	return 0;
	46	}
	47
	48	int checkboard(void)
	49	{
	50	puts("Board: Freescale MPC8313ERDB\n");
	51	return 0;
	52	}
	53
22f4442d	54	#ifndef CONFIG_SPL_BUILD
96b8a054 SW	55	static struct pci_region pci_regions[] = {
96b8a054 SW	56	{
a2873bde KP	57	.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
	58	.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
	59	.size = CONFIG_SYS_PCI1_MEM_SIZE,
	60	.flags = PCI_REGION_MEM \| PCI_REGION_PREFETCH
96b8a054 SW	61	},
96b8a054 SW	62	{
a2873bde KP	63	.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
	64	.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
	65	.size = CONFIG_SYS_PCI1_MMIO_SIZE,
	66	.flags = PCI_REGION_MEM
96b8a054 SW	67	},
96b8a054 SW	68	{
a2873bde KP	69	.bus_start = CONFIG_SYS_PCI1_IO_BASE,
	70	.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
	71	.size = CONFIG_SYS_PCI1_IO_SIZE,
	72	.flags = PCI_REGION_IO
96b8a054 SW	73	}
	74	};
	75
	76	void pci_init_board(void)
	77	{
6d0f6bcf	78	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
96b8a054 SW	79	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
	80	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	81	struct pci_region *reg[] = { pci_regions };
96b8a054 SW	82
	83	/* Enable all 3 PCI_CLK_OUTPUTs. */
	84	clk->occr \|= 0xe0000000;
	85
	86	/*
	87	* Configure PCI Local Access Windows
	88	*/
6d0f6bcf	89	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
96b8a054 SW	90	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_512MB;
96b8a054 SW	91
6d0f6bcf	92	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
96b8a054 SW	93	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
96b8a054 SW	94
6aa3d3bf	95	mpc83xx_pci_init(1, reg);
96b8a054 SW	96	}
96b8a054 SW	97
89c7784e TT	98	/*
	99	* Miscellaneous late-boot configurations
	100	*
	101	* If a VSC7385 microcode image is present, then upload it.
	102	*/
	103	int misc_init_r(void)
	104	{
	105	int rc = 0;
	106
	107	#ifdef CONFIG_VSC7385_IMAGE
	108	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
	109	CONFIG_VSC7385_IMAGE_SIZE)) {
	110	puts("Failure uploading VSC7385 microcode.\n");
	111	rc = 1;
	112	}
	113	#endif
	114
	115	return rc;
	116	}
	117
3fde9e8b	118	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	119	int ft_board_setup(void blob, bd_t bd)
96b8a054	120	{
3fde9e8b KP	121	ft_cpu_setup(blob, bd);
	122	#ifdef CONFIG_PCI
	123	ft_pci_setup(blob, bd);
	124	#endif
e895a4b0 SG	125
e895a4b0 SG	126	return 0;
96b8a054 SW	127	}
96b8a054 SW	128	#endif
22f4442d	129	#else /* CONFIG_SPL_BUILD */
e4c09508 SW	130	void board_init_f(ulong bootflag)
	131	{
	132	board_early_init_f();
6d0f6bcf	133	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
93e14596	134	CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
e4c09508	135	puts("NAND boot... ");
70e2aaf3	136	timer_init();
e4c09508	137	initdram(0);
6e1385d5	138	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
93e14596	139	CONFIG_SYS_NAND_U_BOOT_RELOC);
e4c09508 SW	140	}
	141
	142	void board_init_r(gd_t *gd, ulong dest_addr)
	143	{
	144	nand_boot();
	145	}
	146
	147	void putc(char c)
	148	{
	149	if (gd->flags & GD_FLG_SILENT)
	150	return;
	151
	152	if (c == '\n')
6d0f6bcf	153	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
e4c09508	154
6d0f6bcf	155	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
e4c09508 SW	156	}
e4c09508 SW	157	#endif