[people/ms/u-boot.git] / board / freescale / mpc832xemds / pci.c

/*
 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * PCI Configuration space access support for MPC83xx PCI Bridge
 */
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
#include "../common/pq-mds-pib.h"

DECLARE_GLOBAL_DATA_PTR;

static struct pci_region pci1_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
		size: CONFIG_SYS_PCI1_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI1_IO_BASE,
		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
		size: CONFIG_SYS_PCI1_IO_SIZE,
		flags: PCI_REGION_IO
	},
	{
		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
		size: CONFIG_SYS_PCI1_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
};

#ifdef CONFIG_MPC83XX_PCI2
static struct pci_region pci2_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
		size: CONFIG_SYS_PCI2_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI2_IO_BASE,
		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
		size: CONFIG_SYS_PCI2_IO_SIZE,
		flags: PCI_REGION_IO
	},
	{
		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
		size: CONFIG_SYS_PCI2_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
};
#endif

void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
	struct pci_region *reg[] = { pci1_regions };

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;

	mpc83xx_pci_init(1, reg);

	/*
	 * Configure PCI Inbound Translation Windows
	 */
	pci_ctrl[0].pitar0 = 0x0;
	pci_ctrl[0].pibar0 = 0x0;
	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;

	pci_ctrl[0].pitar1 = 0x0;
	pci_ctrl[0].pibar1 = 0x0;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 &= ~PIWAR_EN;

	pci_ctrl[0].pitar2 = 0x0;
	pci_ctrl[0].pibar2 = 0x0;
	pci_ctrl[0].piebar2 = 0x0;
	pci_ctrl[0].piwar2 &= ~PIWAR_EN;

	/* Unlock the configuration bit */
	mpc83xx_pcislave_unlock(0);
	printf("PCI:   Agent mode enabled\n");
}
#else
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
#ifndef CONFIG_MPC83XX_PCI2
	struct pci_region *reg[] = { pci1_regions };
#else
	struct pci_region *reg[] = { pci1_regions, pci2_regions };
#endif

	/* initialize the PCA9555PW IO expander on the PIB board */
	pib_init();

#if defined(CONFIG_PCI_66M)
	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
	printf("PCI clock is 66MHz\n");
#elif defined(CONFIG_PCI_33M)
	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
	printf("PCI clock is 33MHz\n");
#else
	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
	printf("PCI clock is 66MHz\n");
#endif
	udelay(2000);

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;

	udelay(2000);

#ifndef CONFIG_MPC83XX_PCI2
	mpc83xx_pci_init(1, reg);
#else
	mpc83xx_pci_init(2, reg);
#endif
}
#endif				/* CONFIG_PCISLAVE */
Commit	Line	Data
24c3aca3	1	/*
9993e196	2	* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
24c3aca3	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
24c3aca3 DL	5	*/
	6
	7	/*
	8	* PCI Configuration space access support for MPC83xx PCI Bridge
	9	*/
	10	#include <asm/mmu.h>
	11	#include <asm/io.h>
	12	#include <common.h>
9993e196	13	#include <mpc83xx.h>
24c3aca3 DL	14	#include <pci.h>
24c3aca3 DL	15	#include <i2c.h>
24c3aca3	16	#include <asm/fsl_i2c.h>
9993e196	17	#include "../common/pq-mds-pib.h"
24c3aca3 DL	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
9993e196 KP	21	static struct pci_region pci1_regions[] = {
	22	{
	23	bus_start: CONFIG_SYS_PCI1_MEM_BASE,
	24	phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
	25	size: CONFIG_SYS_PCI1_MEM_SIZE,
	26	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	27	},
	28	{
	29	bus_start: CONFIG_SYS_PCI1_IO_BASE,
	30	phys_start: CONFIG_SYS_PCI1_IO_PHYS,
	31	size: CONFIG_SYS_PCI1_IO_SIZE,
	32	flags: PCI_REGION_IO
	33	},
	34	{
	35	bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
	36	phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
	37	size: CONFIG_SYS_PCI1_MMIO_SIZE,
	38	flags: PCI_REGION_MEM
	39	},
	40	};
24c3aca3	41
9993e196 KP	42	#ifdef CONFIG_MPC83XX_PCI2
9993e196 KP	43	static struct pci_region pci2_regions[] = {
24c3aca3	44	{
9993e196 KP	45	bus_start: CONFIG_SYS_PCI2_MEM_BASE,
	46	phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
	47	size: CONFIG_SYS_PCI2_MEM_SIZE,
	48	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
24c3aca3	49	},
24c3aca3	50	{
9993e196 KP	51	bus_start: CONFIG_SYS_PCI2_IO_BASE,
	52	phys_start: CONFIG_SYS_PCI2_IO_PHYS,
	53	size: CONFIG_SYS_PCI2_IO_SIZE,
	54	flags: PCI_REGION_IO
	55	},
	56	{
	57	bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
	58	phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
	59	size: CONFIG_SYS_PCI2_MMIO_SIZE,
	60	flags: PCI_REGION_MEM
24c3aca3 DL	61	},
24c3aca3 DL	62	};
9993e196 KP	63	#endif
9993e196 KP	64
24c3aca3 DL	65	void pci_init_board(void)
	66	#ifdef CONFIG_PCISLAVE
	67	{
9993e196 KP	68	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
	69	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	70	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
	71	struct pci_region *reg[] = { pci1_regions };
	72
	73	/* Configure PCI Local Access Windows */
	74	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	75	pci_law[0].ar = LAWAR_EN \| LAWAR_SIZE_1G;
	76
	77	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	78	pci_law[1].ar = LAWAR_EN \| LAWAR_SIZE_4M;
	79
6aa3d3bf	80	mpc83xx_pci_init(1, reg);
24c3aca3	81
24c3aca3 DL	82	/*
	83	* Configure PCI Inbound Translation Windows
	84	*/
	85	pci_ctrl[0].pitar0 = 0x0;
	86	pci_ctrl[0].pibar0 = 0x0;
	87	pci_ctrl[0].piwar0 = PIWAR_EN \| PIWAR_RTT_SNOOP \|
	88	PIWAR_WTT_SNOOP \| PIWAR_IWS_4K;
	89
	90	pci_ctrl[0].pitar1 = 0x0;
	91	pci_ctrl[0].pibar1 = 0x0;
	92	pci_ctrl[0].piebar1 = 0x0;
	93	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
	94
	95	pci_ctrl[0].pitar2 = 0x0;
	96	pci_ctrl[0].pibar2 = 0x0;
	97	pci_ctrl[0].piebar2 = 0x0;
	98	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
	99
9993e196 KP	100	/* Unlock the configuration bit */
	101	mpc83xx_pcislave_unlock(0);
	102	printf("PCI: Agent mode enabled\n");
24c3aca3 DL	103	}
	104	#else
	105	{
9993e196 KP	106	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
	107	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
	108	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	109	#ifndef CONFIG_MPC83XX_PCI2
	110	struct pci_region *reg[] = { pci1_regions };
	111	#else
	112	struct pci_region *reg[] = { pci1_regions, pci2_regions };
	113	#endif
24c3aca3	114
9993e196 KP	115	/* initialize the PCA9555PW IO expander on the PIB board */
9993e196 KP	116	pib_init();
24c3aca3	117
2ae18241	118	#if defined(CONFIG_PCI_66M)
24c3aca3 DL	119	clk->occr = OCCR_PCICOE0 \| OCCR_PCICOE1 \| OCCR_PCICOE2;
24c3aca3 DL	120	printf("PCI clock is 66MHz\n");
2ae18241	121	#elif defined(CONFIG_PCI_33M)
24c3aca3 DL	122	clk->occr = OCCR_PCICOE0 \| OCCR_PCICOE1 \| OCCR_PCICOE2 \|
	123	OCCR_PCICD0 \| OCCR_PCICD1 \| OCCR_PCICD2 \| OCCR_PCICR;
	124	printf("PCI clock is 33MHz\n");
	125	#else
	126	clk->occr = OCCR_PCICOE0 \| OCCR_PCICOE1 \| OCCR_PCICOE2;
	127	printf("PCI clock is 66MHz\n");
	128	#endif
	129	udelay(2000);
	130
9993e196 KP	131	/* Configure PCI Local Access Windows */
9993e196 KP	132	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
24c3aca3 DL	133	pci_law[0].ar = LAWAR_EN \| LAWAR_SIZE_512M;
24c3aca3 DL	134
9993e196	135	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
24c3aca3 DL	136	pci_law[1].ar = LAWAR_EN \| LAWAR_SIZE_1M;
24c3aca3 DL	137
24c3aca3	138	udelay(2000);
24c3aca3	139
9993e196	140	#ifndef CONFIG_MPC83XX_PCI2
6aa3d3bf	141	mpc83xx_pci_init(1, reg);
9993e196	142	#else
6aa3d3bf	143	mpc83xx_pci_init(2, reg);
9993e196	144	#endif
24c3aca3 DL	145	}
24c3aca3 DL	146	#endif /* CONFIG_PCISLAVE */