[people/ms/u-boot.git] / board / freescale / mpc8349emds / mpc8349emds.c

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
#ifdef CONFIG_SYS_FSL_DDR2
#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif

#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

int fixed_sdram(void);
void sdram_init(void);

#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
void ddr_enable_ecc(unsigned int dram_size);
#endif

int board_early_init_f (void)
{
	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;

	/* Enable flash write */
	bcsr[1] &= ~0x01;

#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
	/* Use USB PHY on SYS board */
	bcsr[5] |= 0x02;
#endif

	return 0;
}

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)

int initdram(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	phys_size_t msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -ENXIO;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_SYS_FSL_DDR2
	msize = spd_sdram() * 1024 * 1024;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	ddr_enable_ecc(msize);
#endif
#else
	msize = fsl_ddr_sdram();
#endif
#else
	msize = fixed_sdram() * 1024 * 1024;
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

	/* set total bus SDRAM size(bytes)  -- DDR */
	gd->ram_size = msize;

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE;
	u32 ddr_size = msize << 20;	/* DDR size in bytes */
	u32 ddr_size_log2 = __ilog2(ddr_size);

	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);

#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else

#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
	im->ddr.csbnds[2].csbnds =
		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
				CSBNDS_EA_SHIFT) & CSBNDS_EA);
	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;

	/* currently we use only one CS, so disable the other banks */
	im->ddr.cs_config[0] = 0;
	im->ddr.cs_config[1] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;

	im->ddr.sdram_cfg =
		SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
		| SDRAM_CFG_2T_EN
#endif
		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
#if defined (CONFIG_DDR_32BIT)
	/* for 32-bit mode burst length is 8 */
	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
#endif
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;

	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
	udelay(200);

	/* enable DDR controller */
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	return msize;
}
#endif/*!CONFIG_SYS_SPD_EEPROM*/


int checkboard (void)
{
	/*
	 * Warning: do not read the BCSR registers here
	 *
	 * There is a timing bug in the 8349E and 8349EA BCSR code
	 * version 1.2 (read from BCSR 11) that will cause the CFI
	 * flash initialization code to overwrite BCSR 0, disabling
	 * the serial ports and gigabit ethernet
	 */

	puts("Board: Freescale MPC8349EMDS\n");
	return 0;
}

/*
 * if MPC8349EMDS is soldered with SDRAM
 */
#if defined(CONFIG_SYS_BR2_PRELIM)  \
	&& defined(CONFIG_SYS_OR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void sdram_init(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile fsl_lbc_t *lbc = &immap->im_lbc;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */

	/* setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	asm("sync");
	/*1 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*2 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*3 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*4 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*5 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*6 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*7 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*8 times*/
	*sdram_addr = 0xff;
	udelay(100);

	/* 0x58636733; mode register write operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void sdram_init(void)
{
}
#endif

/*
 * The following are used to control the SPI chip selects for the SPI command.
 */
#ifdef CONFIG_MPC8XXX_SPI

#define SPI_CS_MASK	0x80000000

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}

void spi_cs_activate(struct spi_slave *slave)
{
	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];

	iopd->dat &= ~SPI_CS_MASK;
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];

	iopd->dat |=  SPI_CS_MASK;
}
#endif /* CONFIG_HARD_SPI */

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif

	return 0;
}
#endif
Commit	Line	Data
991425fe MB	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
991425fe MB	6	*/
	7
	8	#include <common.h>
	9	#include <ioports.h>
	10	#include <mpc83xx.h>
	11	#include <asm/mpc8349_pci.h>
	12	#include <i2c.h>
80ddd226	13	#include <spi.h>
991425fe	14	#include <miiphy.h>
5614e71b YS	15	#ifdef CONFIG_SYS_FSL_DDR2
5614e71b YS	16	#include <fsl_ddr_sdram.h>
d4b91066	17	#else
991425fe	18	#include <spd_sdram.h>
d4b91066	19	#endif
a30a549a	20
b3458d2c	21	#if defined(CONFIG_OF_LIBFDT)
3fde9e8b	22	#include <libfdt.h>
bf0b542d KP	23	#endif
bf0b542d KP	24
088454cd SG	25	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	26
991425fe MB	27	int fixed_sdram(void);
	28	void sdram_init(void);
	29
0f898604	30	#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
991425fe MB	31	void ddr_enable_ecc(unsigned int dram_size);
	32	#endif
	33
	34	int board_early_init_f (void)
	35	{
6d0f6bcf	36	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
991425fe MB	37
	38	/* Enable flash write */
	39	bcsr[1] &= ~0x01;
	40
6d0f6bcf	41	#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
8fe9bf61 KG	42	/* Use USB PHY on SYS board */
	43	bcsr[5] \|= 0x02;
	44	#endif
	45
991425fe MB	46	return 0;
	47	}
	48
	49	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
	50
088454cd	51	int initdram(void)
991425fe	52	{
6d0f6bcf	53	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
d4b91066	54	phys_size_t msize = 0;
991425fe MB	55
991425fe MB	56	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
088454cd	57	return -ENXIO;
991425fe MB	58
991425fe MB	59	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	60	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
991425fe	61	#if defined(CONFIG_SPD_EEPROM)
5614e71b	62	#ifndef CONFIG_SYS_FSL_DDR2
d4b91066 YS	63	msize = spd_sdram() * 1024 * 1024;
	64	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	65	ddr_enable_ecc(msize);
	66	#endif
	67	#else
	68	msize = fsl_ddr_sdram();
	69	#endif
991425fe	70	#else
d4b91066	71	msize = fixed_sdram() * 1024 * 1024;
991425fe MB	72	#endif
	73	/*
	74	* Initialize SDRAM if it is on local bus.
	75	*/
	76	sdram_init();
	77
088454cd SG	78	/* set total bus SDRAM size(bytes) -- DDR */
	79	gd->ram_size = msize;
	80
	81	return 0;
991425fe MB	82	}
	83
	84	#if !defined(CONFIG_SPD_EEPROM)
	85	/*************************************************************************
	86	* fixed sdram init -- doesn't use serial presence detect.
	87	************************************************************************/
	88	int fixed_sdram(void)
	89	{
6d0f6bcf	90	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
2e651b24 JH	91	u32 msize = CONFIG_SYS_DDR_SIZE;
	92	u32 ddr_size = msize << 20; /* DDR size in bytes */
	93	u32 ddr_size_log2 = __ilog2(ddr_size);
	94
6d0f6bcf	95	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
991425fe	96	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
dc9e499c	97
6d0f6bcf	98	#if (CONFIG_SYS_DDR_SIZE != 256)
991425fe MB	99	#warning Currenly any ddr size other than 256 is not supported
991425fe MB	100	#endif
d61853cf	101	#ifdef CONFIG_DDR_II
6d0f6bcf JCPV	102	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
	103	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
	104	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	105	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	106	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	107	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	108	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	109	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	110	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	111	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	112	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	113	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
d61853cf	114	#else
2e651b24 JH	115
	116	#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
	117	#warning Chip select bounds is only configurable in 16MB increments
	118	#endif
	119	im->ddr.csbnds[2].csbnds =
	120	((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) \|
	121	(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
	122	CSBNDS_EA_SHIFT) & CSBNDS_EA);
	123	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
dc9e499c	124
cf48eb9a	125	/* currently we use only one CS, so disable the other banks */
dc9e499c RJ	126	im->ddr.cs_config[0] = 0;
	127	im->ddr.cs_config[1] = 0;
	128	im->ddr.cs_config[3] = 0;
	129
6d0f6bcf JCPV	130	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
6d0f6bcf JCPV	131	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
cf48eb9a	132
991425fe MB	133	im->ddr.sdram_cfg =
	134	SDRAM_CFG_SREN
	135	#if defined(CONFIG_DDR_2T_TIMING)
	136	\| SDRAM_CFG_2T_EN
	137	#endif
	138	\| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
dc9e499c RJ	139	#if defined (CONFIG_DDR_32BIT)
	140	/* for 32-bit mode burst length is 8 */
	141	im->ddr.sdram_cfg \|= (SDRAM_CFG_32_BE \| SDRAM_CFG_8_BE);
	142	#endif
6d0f6bcf	143	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
991425fe	144
6d0f6bcf	145	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
d61853cf	146	#endif
991425fe MB	147	udelay(200);
991425fe MB	148
dc9e499c	149	/* enable DDR controller */
991425fe	150	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
991425fe MB	151	return msize;
991425fe MB	152	}
6d0f6bcf	153	#endif/!CONFIG_SYS_SPD_EEPROM/
991425fe MB	154
	155
	156	int checkboard (void)
	157	{
447ad576 IS	158	/*
	159	* Warning: do not read the BCSR registers here
	160	*
	161	* There is a timing bug in the 8349E and 8349EA BCSR code
	162	* version 1.2 (read from BCSR 11) that will cause the CFI
	163	* flash initialization code to overwrite BCSR 0, disabling
	164	* the serial ports and gigabit ethernet
	165	*/
	166
991425fe MB	167	puts("Board: Freescale MPC8349EMDS\n");
	168	return 0;
	169	}
	170
991425fe MB	171	/*
	172	* if MPC8349EMDS is soldered with SDRAM
	173	*/
6d0f6bcf JCPV	174	#if defined(CONFIG_SYS_BR2_PRELIM) \
	175	&& defined(CONFIG_SYS_OR2_PRELIM) \
	176	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	177	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
991425fe MB	178	/*
	179	* Initialize SDRAM memory on the Local Bus.
	180	*/
	181
	182	void sdram_init(void)
	183	{
6d0f6bcf	184	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
f51cdaf1	185	volatile fsl_lbc_t *lbc = &immap->im_lbc;
6d0f6bcf	186	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
991425fe	187
991425fe MB	188	/*
	189	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	190	*/
	191
	192	/* setup mtrpt, lsrt and lbcr for LB bus */
6d0f6bcf JCPV	193	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	194	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	195	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
991425fe MB	196	asm("sync");
	197
	198	/*
	199	* Configure the SDRAM controller Machine Mode Register.
	200	*/
6d0f6bcf	201	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
991425fe	202
6d0f6bcf	203	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
991425fe MB	204	asm("sync");
	205	*sdram_addr = 0xff;
	206	udelay(100);
	207
6d0f6bcf	208	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
991425fe MB	209	asm("sync");
	210	/1 times/
	211	*sdram_addr = 0xff;
	212	udelay(100);
	213	/2 times/
	214	*sdram_addr = 0xff;
	215	udelay(100);
	216	/3 times/
	217	*sdram_addr = 0xff;
	218	udelay(100);
	219	/4 times/
	220	*sdram_addr = 0xff;
	221	udelay(100);
	222	/5 times/
	223	*sdram_addr = 0xff;
	224	udelay(100);
	225	/6 times/
	226	*sdram_addr = 0xff;
	227	udelay(100);
	228	/7 times/
	229	*sdram_addr = 0xff;
	230	udelay(100);
	231	/8 times/
	232	*sdram_addr = 0xff;
	233	udelay(100);
	234
	235	/* 0x58636733; mode register write operation */
6d0f6bcf	236	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
991425fe MB	237	asm("sync");
	238	*sdram_addr = 0xff;
	239	udelay(100);
	240
6d0f6bcf	241	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
991425fe MB	242	asm("sync");
	243	*sdram_addr = 0xff;
	244	udelay(100);
	245	}
	246	#else
	247	void sdram_init(void)
	248	{
991425fe MB	249	}
991425fe MB	250	#endif
d326f4a2	251
80ddd226 BW	252	/*
	253	* The following are used to control the SPI chip selects for the SPI command.
	254	*/
f8cc312b	255	#ifdef CONFIG_MPC8XXX_SPI
80ddd226 BW	256
	257	#define SPI_CS_MASK 0x80000000
	258
d255bb0e HS	259	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	260	{
	261	return bus == 0 && cs == 0;
	262	}
	263
	264	void spi_cs_activate(struct spi_slave *slave)
80ddd226	265	{
6d0f6bcf	266	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
80ddd226	267
d255bb0e	268	iopd->dat &= ~SPI_CS_MASK;
80ddd226 BW	269	}
80ddd226 BW	270
d255bb0e HS	271	void spi_cs_deactivate(struct spi_slave *slave)
d255bb0e HS	272	{
6d0f6bcf	273	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
80ddd226	274
d255bb0e HS	275	iopd->dat \|= SPI_CS_MASK;
d255bb0e HS	276	}
80ddd226 BW	277	#endif /* CONFIG_HARD_SPI */
80ddd226 BW	278
3fde9e8b	279	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	280	int ft_board_setup(void blob, bd_t bd)
bf0b542d	281	{
3fde9e8b KP	282	ft_cpu_setup(blob, bd);
	283	#ifdef CONFIG_PCI
	284	ft_pci_setup(blob, bd);
	285	#endif
e895a4b0 SG	286
e895a4b0 SG	287	return 0;
bf0b542d KP	288	}
bf0b542d KP	289	#endif