[people/ms/u-boot.git] / board / freescale / mpc8360emds / mpc8360emds.c

/*
 * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
 * Dave Liu <daveliu@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <phy.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#include <spd_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <hwconfig.h>
#include <fdt_support.h>
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif
#include "../../../drivers/qe/uec.h"

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{0,  3, 1, 0, 1}, /* TxD0 */
	{0,  4, 1, 0, 1}, /* TxD1 */
	{0,  5, 1, 0, 1}, /* TxD2 */
	{0,  6, 1, 0, 1}, /* TxD3 */
	{1,  6, 1, 0, 3}, /* TxD4 */
	{1,  7, 1, 0, 1}, /* TxD5 */
	{1,  9, 1, 0, 2}, /* TxD6 */
	{1, 10, 1, 0, 2}, /* TxD7 */
	{0,  9, 2, 0, 1}, /* RxD0 */
	{0, 10, 2, 0, 1}, /* RxD1 */
	{0, 11, 2, 0, 1}, /* RxD2 */
	{0, 12, 2, 0, 1}, /* RxD3 */
	{0, 13, 2, 0, 1}, /* RxD4 */
	{1,  1, 2, 0, 2}, /* RxD5 */
	{1,  0, 2, 0, 2}, /* RxD6 */
	{1,  4, 2, 0, 2}, /* RxD7 */
	{0,  7, 1, 0, 1}, /* TX_EN */
	{0,  8, 1, 0, 1}, /* TX_ER */
	{0, 15, 2, 0, 1}, /* RX_DV */
	{0, 16, 2, 0, 1}, /* RX_ER */
	{0,  0, 2, 0, 1}, /* RX_CLK */
	{2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	{2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
	/* GETH2 */
	{0, 17, 1, 0, 1}, /* TxD0 */
	{0, 18, 1, 0, 1}, /* TxD1 */
	{0, 19, 1, 0, 1}, /* TxD2 */
	{0, 20, 1, 0, 1}, /* TxD3 */
	{1,  2, 1, 0, 1}, /* TxD4 */
	{1,  3, 1, 0, 2}, /* TxD5 */
	{1,  5, 1, 0, 3}, /* TxD6 */
	{1,  8, 1, 0, 3}, /* TxD7 */
	{0, 23, 2, 0, 1}, /* RxD0 */
	{0, 24, 2, 0, 1}, /* RxD1 */
	{0, 25, 2, 0, 1}, /* RxD2 */
	{0, 26, 2, 0, 1}, /* RxD3 */
	{0, 27, 2, 0, 1}, /* RxD4 */
	{1, 12, 2, 0, 2}, /* RxD5 */
	{1, 13, 2, 0, 3}, /* RxD6 */
	{1, 11, 2, 0, 2}, /* RxD7 */
	{0, 21, 1, 0, 1}, /* TX_EN */
	{0, 22, 1, 0, 1}, /* TX_ER */
	{0, 29, 2, 0, 1}, /* RX_DV */
	{0, 30, 2, 0, 1}, /* RX_ER */
	{0, 31, 2, 0, 1}, /* RX_CLK */
	{2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	{2,  3, 2, 0, 1}, /* GTX125 - CLK4 */

	{0,  1, 3, 0, 2}, /* MDIO */
	{0,  2, 1, 0, 1}, /* MDC */

	{5,  0, 1, 0, 2}, /* UART2_SOUT */
	{5,  1, 2, 0, 3}, /* UART2_CTS */
	{5,  2, 1, 0, 1}, /* UART2_RTS */
	{5,  3, 2, 0, 2}, /* UART2_SIN */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
static int board_handle_erratum2(void)
{
	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
	       REVID_MINOR(immr->sysconf.spridr) == 1;
}

int board_early_init_f(void)
{
	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;

	/* Enable flash write */
	bcsr[0xa] &= ~0x04;

	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
	if (REVID_MAJOR(immr->sysconf.spridr) == 2)
		bcsr[0xe] = 0x30;

	/* Enable second UART */
	bcsr[0x9] &= ~0x01;

	if (board_handle_erratum2()) {
		void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);

		/*
		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
		 */
		setbits_be32(immap, 0x0c003000);

		/*
		 * IMMR + 0x14AC[20:27] = 10101010
		 * (data delay for both UCC's)
		 */
		clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
	}
	return 0;
}

int board_early_init_r(void)
{
	gd_t *gd;
#ifdef CONFIG_PQ_MDS_PIB
	pib_init();
#endif
	/*
	 * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
	 * So re-setup PCI MEM space used BAT5 after relocated to DDR
	 */
	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
		write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
		write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
	}

	return 0;
}

#ifdef CONFIG_UEC_ETH
static uec_info_t uec_info[] = {
#ifdef CONFIG_UEC_ETH1
	STD_UEC_INFO(1),
#endif
#ifdef CONFIG_UEC_ETH2
	STD_UEC_INFO(2),
#endif
};

int board_eth_init(bd_t *bd)
{
	if (board_handle_erratum2()) {
		int i;

		for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
			uec_info[i].enet_interface_type =
				PHY_INTERFACE_MODE_RGMII_RXID;
			uec_info[i].speed = SPEED_1000;
		}
	}
	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
}
#endif /* CONFIG_UEC_ETH */

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
static int sdram_init(unsigned int base);

phys_size_t initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;
	u32 lbc_sdram_size;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize DDR ECC byte
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
	if (!msize)
		msize = lbc_sdram_size;

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE;
	u32 ddr_size = msize << 20;
	u32 ddr_size_log2 = __ilog2(ddr_size);
	u32 half_ddr_size = ddr_size >> 1;

	im->sysconf.ddrlaw[0].bar =
		CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar =
		LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else

#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
	im->ddr.csbnds[0].csbnds =
		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
				CSBNDS_EA_SHIFT) & CSBNDS_EA);
	im->ddr.csbnds[1].csbnds =
		(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
				CSBNDS_SA_SHIFT) & CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
				CSBNDS_EA_SHIFT) & CSBNDS_EA);

	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;

	im->ddr.cs_config[2] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;

	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
	udelay(200);
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;

	return msize;
}
#endif				/*!CONFIG_SYS_SPD_EEPROM */

int checkboard(void)
{
	puts("Board: Freescale MPC8360EMDS\n");
	return 0;
}

/*
 * if MPC8360EMDS is soldered with SDRAM
 */
#ifdef CONFIG_SYS_LB_SDRAM
/*
 * Initialize SDRAM memory on the Local Bus.
 */

static int sdram_init(unsigned int base)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	fsl_lbc_t *lbc = LBC_BASE_ADDR;
	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	int rem = base % sdram_size;
	uint *sdram_addr;

	/* window base address should be aligned to the window size */
	if (rem)
		base = base - rem + sdram_size;

	/*
	 * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
	 * After relocated to DDR, reuse BAT5 for PCI MEM space
	 */
	if (base > CONFIG_MAX_MEM_MAPPED) {
		unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
		unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;

		/* Setup the BAT6 for SDRAM */
		write_bat(DBAT6, batu, batl);
		write_bat(IBAT6, batu, batl);
	}

	sdram_addr = (uint *)base;
	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_br(2, base | CONFIG_SYS_BR2);
	set_lbc_or(2, CONFIG_SYS_OR2);
	immap->sysconf.lblaw[2].bar = base;
	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;

	/*setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;	/* Normal Operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;	/* Precharge All Banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	/*
	 * We need do 8 times auto refresh operation.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
	asm("sync");
	*sdram_addr = 0xff;	/* 1 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 2 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 3 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 4 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 5 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 6 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 7 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 8 times */
	udelay(100);

	/* Mode register write operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*(sdram_addr + 0xcc) = 0xff;
	udelay(100);

	/* Normal operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	/*
	 * In non-aligned case we don't [normally] use that memory because
	 * there is a hole.
	 */
	if (rem)
		return 0;
	return CONFIG_SYS_LBC_SDRAM_SIZE;
}
#else
static int sdram_init(unsigned int base) { return 0; }
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
{
	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
		return;

	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
			   "peripheral", sizeof("peripheral"), 1);
}

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	ft_board_fixup_qe_usb(blob, bd);
	/*
	 * mpc8360ea pb mds errata 2: RGMII timing
	 * if on mpc8360ea rev. 2.1,
	 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	 */
	if (board_handle_erratum2()) {
		int nodeoffset;
		const char *prop;
		int path;

		nodeoffset = fdt_path_offset(blob, "/aliases");
		if (nodeoffset >= 0) {
#if defined(CONFIG_HAS_ETH0)
			/* fixup UCC 1 if using rgmii-id mode */
			prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
			if (prop) {
				path = fdt_path_offset(blob, prop);
				prop = fdt_getprop(blob, path,
						   "phy-connection-type", 0);
				if (prop && (strcmp(prop, "rgmii-id") == 0))
					fdt_fixup_phy_connection(blob, path,
						PHY_INTERFACE_MODE_RGMII_RXID);
			}
#endif
#if defined(CONFIG_HAS_ETH1)
			/* fixup UCC 2 if using rgmii-id mode */
			prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
			if (prop) {
				path = fdt_path_offset(blob, prop);
				prop = fdt_getprop(blob, path,
						   "phy-connection-type", 0);
				if (prop && (strcmp(prop, "rgmii-id") == 0))
					fdt_fixup_phy_connection(blob, path,
						PHY_INTERFACE_MODE_RGMII_RXID);
			}
#endif
		}
	}
}
#endif
Commit	Line	Data
5f820439	1	/*
d37be07e	2	* Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
5f820439	3	* Dave Liu <daveliu@freescale.com>
5f820439	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5f820439 DL	6	*/
	7
	8	#include <common.h>
	9	#include <ioports.h>
	10	#include <mpc83xx.h>
	11	#include <i2c.h>
5f820439	12	#include <miiphy.h>
865ff856	13	#include <phy.h>
5f820439 DL	14	#if defined(CONFIG_PCI)
	15	#include <pci.h>
	16	#endif
5f820439	17	#include <spd_sdram.h>
5f820439	18	#include <asm/mmu.h>
89da44ce	19	#include <asm/io.h>
a1964ea5	20	#include <asm/fsl_enet.h>
d37be07e	21	#include <asm/mmu.h>
b3458d2c	22	#if defined(CONFIG_OF_LIBFDT)
213bf8c8	23	#include <libfdt.h>
213bf8c8	24	#endif
da6eea0f AV	25	#include <hwconfig.h>
da6eea0f AV	26	#include <fdt_support.h>
14778585	27	#if defined(CONFIG_PQ_MDS_PIB)
e58fe957	28	#include "../common/pq-mds-pib.h"
14778585	29	#endif
89da44ce	30	#include "../../../drivers/qe/uec.h"
5f820439	31
7737d5c6 DL	32	const qe_iop_conf_t qe_iop_conf_tab[] = {
	33	/* GETH1 */
	34	{0, 3, 1, 0, 1}, /* TxD0 */
	35	{0, 4, 1, 0, 1}, /* TxD1 */
	36	{0, 5, 1, 0, 1}, /* TxD2 */
	37	{0, 6, 1, 0, 1}, /* TxD3 */
	38	{1, 6, 1, 0, 3}, /* TxD4 */
	39	{1, 7, 1, 0, 1}, /* TxD5 */
	40	{1, 9, 1, 0, 2}, /* TxD6 */
	41	{1, 10, 1, 0, 2}, /* TxD7 */
	42	{0, 9, 2, 0, 1}, /* RxD0 */
	43	{0, 10, 2, 0, 1}, /* RxD1 */
	44	{0, 11, 2, 0, 1}, /* RxD2 */
	45	{0, 12, 2, 0, 1}, /* RxD3 */
	46	{0, 13, 2, 0, 1}, /* RxD4 */
	47	{1, 1, 2, 0, 2}, /* RxD5 */
	48	{1, 0, 2, 0, 2}, /* RxD6 */
	49	{1, 4, 2, 0, 2}, /* RxD7 */
	50	{0, 7, 1, 0, 1}, /* TX_EN */
	51	{0, 8, 1, 0, 1}, /* TX_ER */
	52	{0, 15, 2, 0, 1}, /* RX_DV */
	53	{0, 16, 2, 0, 1}, /* RX_ER */
	54	{0, 0, 2, 0, 1}, /* RX_CLK */
	55	{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	56	{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
	57	/* GETH2 */
	58	{0, 17, 1, 0, 1}, /* TxD0 */
	59	{0, 18, 1, 0, 1}, /* TxD1 */
	60	{0, 19, 1, 0, 1}, /* TxD2 */
	61	{0, 20, 1, 0, 1}, /* TxD3 */
	62	{1, 2, 1, 0, 1}, /* TxD4 */
	63	{1, 3, 1, 0, 2}, /* TxD5 */
	64	{1, 5, 1, 0, 3}, /* TxD6 */
	65	{1, 8, 1, 0, 3}, /* TxD7 */
	66	{0, 23, 2, 0, 1}, /* RxD0 */
	67	{0, 24, 2, 0, 1}, /* RxD1 */
	68	{0, 25, 2, 0, 1}, /* RxD2 */
	69	{0, 26, 2, 0, 1}, /* RxD3 */
	70	{0, 27, 2, 0, 1}, /* RxD4 */
	71	{1, 12, 2, 0, 2}, /* RxD5 */
	72	{1, 13, 2, 0, 3}, /* RxD6 */
	73	{1, 11, 2, 0, 2}, /* RxD7 */
	74	{0, 21, 1, 0, 1}, /* TX_EN */
	75	{0, 22, 1, 0, 1}, /* TX_ER */
	76	{0, 29, 2, 0, 1}, /* RX_DV */
	77	{0, 30, 2, 0, 1}, /* RX_ER */
	78	{0, 31, 2, 0, 1}, /* RX_CLK */
	79	{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	80	{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
	81
	82	{0, 1, 3, 0, 2}, /* MDIO */
	83	{0, 2, 1, 0, 1}, /* MDC */
	84
651d96f7 AV	85	{5, 0, 1, 0, 2}, /* UART2_SOUT */
	86	{5, 1, 2, 0, 3}, /* UART2_CTS */
	87	{5, 2, 1, 0, 1}, /* UART2_RTS */
	88	{5, 3, 2, 0, 2}, /* UART2_SIN */
	89
7737d5c6 DL	90	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	91	};
	92
89da44ce AV	93	/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
89da44ce AV	94	static int board_handle_erratum2(void)
5f820439	95	{
89da44ce	96	const immap_t immr = (immap_t )CONFIG_SYS_IMMR;
3fc0bd15	97
89da44ce AV	98	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
	99	REVID_MINOR(immr->sysconf.spridr) == 1;
	100	}
	101
	102	int board_early_init_f(void)
	103	{
6d0f6bcf	104	const immap_t immr = (immap_t )CONFIG_SYS_IMMR;
89da44ce	105	u8 bcsr = (u8 )CONFIG_SYS_BCSR;
5f820439 DL	106
	107	/* Enable flash write */
	108	bcsr[0xa] &= ~0x04;
	109
e5c4ade4 KP	110	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
e5c4ade4 KP	111	if (REVID_MAJOR(immr->sysconf.spridr) == 2)
3fc0bd15 KP	112	bcsr[0xe] = 0x30;
3fc0bd15 KP	113
651d96f7 AV	114	/* Enable second UART */
	115	bcsr[0x9] &= ~0x01;
	116
89da44ce AV	117	if (board_handle_erratum2()) {
	118	void immap = (immap_t )(CONFIG_SYS_IMMR + 0x14a8);
	119
	120	/*
	121	* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
	122	* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
	123	*/
	124	setbits_be32(immap, 0x0c003000);
	125
	126	/*
	127	* IMMR + 0x14AC[20:27] = 10101010
	128	* (data delay for both UCC's)
	129	*/
	130	clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
	131	}
5f820439 DL	132	return 0;
	133	}
	134
14778585 TL	135	int board_early_init_r(void)
14778585 TL	136	{
d37be07e	137	gd_t *gd;
14778585 TL	138	#ifdef CONFIG_PQ_MDS_PIB
	139	pib_init();
	140	#endif
d37be07e JH	141	/*
	142	* BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
	143	* So re-setup PCI MEM space used BAT5 after relocated to DDR
	144	*/
	145	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
	146	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
	147	write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
	148	write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
	149	}
	150
14778585 TL	151	return 0;
	152	}
	153
89da44ce AV	154	#ifdef CONFIG_UEC_ETH
	155	static uec_info_t uec_info[] = {
	156	#ifdef CONFIG_UEC_ETH1
	157	STD_UEC_INFO(1),
	158	#endif
	159	#ifdef CONFIG_UEC_ETH2
	160	STD_UEC_INFO(2),
	161	#endif
	162	};
	163
	164	int board_eth_init(bd_t *bd)
	165	{
	166	if (board_handle_erratum2()) {
	167	int i;
	168
b86c7709	169	for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
865ff856 AF	170	uec_info[i].enet_interface_type =
	171	PHY_INTERFACE_MODE_RGMII_RXID;
	172	uec_info[i].speed = SPEED_1000;
b86c7709	173	}
89da44ce AV	174	}
	175	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
	176	}
	177	#endif /* CONFIG_UEC_ETH */
	178
9adda545	179	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5f820439 DL	180	extern void ddr_enable_ecc(unsigned int dram_size);
	181	#endif
	182	int fixed_sdram(void);
5c2ff323	183	static int sdram_init(unsigned int base);
5f820439	184
9973e3c6	185	phys_size_t initdram(int board_type)
5f820439	186	{
6d0f6bcf	187	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
5f820439	188	u32 msize = 0;
034477bb	189	u32 lbc_sdram_size;
5f820439 DL	190
	191	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	192	return -1;
	193
	194	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	195	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
5f820439 DL	196	#if defined(CONFIG_SPD_EEPROM)
	197	msize = spd_sdram();
	198	#else
	199	msize = fixed_sdram();
	200	#endif
	201
9adda545	202	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5f820439 DL	203	/*
	204	* Initialize DDR ECC byte
	205	*/
	206	ddr_enable_ecc(msize * 1024 * 1024);
	207	#endif
	208	/*
	209	* Initialize SDRAM if it is on local bus.
	210	*/
034477bb AV	211	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
	212	if (!msize)
	213	msize = lbc_sdram_size;
bbea46f7	214
5f820439 DL	215	/* return total bus SDRAM size(bytes) -- DDR */
	216	return (msize * 1024 * 1024);
	217	}
	218
	219	#if !defined(CONFIG_SPD_EEPROM)
	220	/*************************************************************************
	221	* fixed sdram init -- doesn't use serial presence detect.
	222	************************************************************************/
	223	int fixed_sdram(void)
	224	{
6d0f6bcf	225	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
2e651b24 JH	226	u32 msize = CONFIG_SYS_DDR_SIZE;
	227	u32 ddr_size = msize << 20;
	228	u32 ddr_size_log2 = __ilog2(ddr_size);
	229	u32 half_ddr_size = ddr_size >> 1;
	230
	231	im->sysconf.ddrlaw[0].bar =
	232	CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
5f820439	233	im->sysconf.ddrlaw[0].ar =
2e651b24	234	LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
6d0f6bcf	235	#if (CONFIG_SYS_DDR_SIZE != 256)
5f820439 DL	236	#warning Currenly any ddr size other than 256 is not supported
5f820439 DL	237	#endif
d61853cf	238	#ifdef CONFIG_DDR_II
6d0f6bcf JCPV	239	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	240	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	241	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	242	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	243	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	244	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	245	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	246	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	247	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	248	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	249	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	250	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
d61853cf	251	#else
5f820439	252
2e651b24 JH	253	#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
	254	#warning Chip select bounds is only configurable in 16MB increments
	255	#endif
	256	im->ddr.csbnds[0].csbnds =
	257	((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) \|
	258	(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
	259	CSBNDS_EA_SHIFT) & CSBNDS_EA);
	260	im->ddr.csbnds[1].csbnds =
	261	(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
	262	CSBNDS_SA_SHIFT) & CSBNDS_SA) \|
	263	(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
	264	CSBNDS_EA_SHIFT) & CSBNDS_EA);
	265
	266	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	267	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
	268
	269	im->ddr.cs_config[2] = 0;
	270	im->ddr.cs_config[3] = 0;
5f820439	271
6d0f6bcf JCPV	272	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	273	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	274	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
5f820439	275
6d0f6bcf JCPV	276	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
6d0f6bcf JCPV	277	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
d61853cf	278	#endif
5f820439 DL	279	udelay(200);
	280	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	281
	282	return msize;
	283	}
6d0f6bcf	284	#endif /!CONFIG_SYS_SPD_EEPROM /
5f820439 DL	285
	286	int checkboard(void)
	287	{
	288	puts("Board: Freescale MPC8360EMDS\n");
	289	return 0;
	290	}
	291
	292	/*
	293	* if MPC8360EMDS is soldered with SDRAM
	294	*/
5c2ff323	295	#ifdef CONFIG_SYS_LB_SDRAM
5f820439 DL	296	/*
	297	* Initialize SDRAM memory on the Local Bus.
	298	*/
	299
5c2ff323	300	static int sdram_init(unsigned int base)
5f820439	301	{
6d0f6bcf	302	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
f51cdaf1	303	fsl_lbc_t *lbc = LBC_BASE_ADDR;
5c2ff323 AV	304	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	305	int rem = base % sdram_size;
	306	uint *sdram_addr;
5f820439	307
5c2ff323 AV	308	/* window base address should be aligned to the window size */
	309	if (rem)
	310	base = base - rem + sdram_size;
	311
d37be07e JH	312	/*
	313	* Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
	314	* After relocated to DDR, reuse BAT5 for PCI MEM space
	315	*/
	316	if (base > CONFIG_MAX_MEM_MAPPED) {
	317	unsigned long batl = base \| BATL_PP_10 \| BATL_MEMCOHERENCE;
	318	unsigned long batu = base \| BATU_BL_64M \| BATU_VS \| BATU_VP;
	319
	320	/* Setup the BAT6 for SDRAM */
	321	write_bat(DBAT6, batu, batl);
	322	write_bat(IBAT6, batu, batl);
	323	}
	324
5c2ff323	325	sdram_addr = (uint *)base;
5f820439	326	/*
5c2ff323	327	* Setup SDRAM Base and Option Registers
5f820439	328	*/
f51cdaf1 BB	329	set_lbc_br(2, base \| CONFIG_SYS_BR2);
f51cdaf1 BB	330	set_lbc_or(2, CONFIG_SYS_OR2);
5c2ff323 AV	331	immap->sysconf.lblaw[2].bar = base;
	332	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
	333
5f820439	334	/setup mtrpt, lsrt and lbcr for LB bus /
6d0f6bcf JCPV	335	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	336	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	337	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
5f820439 DL	338	asm("sync");
	339
	340	/*
	341	* Configure the SDRAM controller Machine Mode Register.
	342	*/
6d0f6bcf JCPV	343	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
6d0f6bcf JCPV	344	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
5f820439 DL	345	asm("sync");
	346	*sdram_addr = 0xff;
	347	udelay(100);
	348
	349	/*
	350	* We need do 8 times auto refresh operation.
	351	*/
6d0f6bcf	352	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
5f820439 DL	353	asm("sync");
	354	sdram_addr = 0xff; / 1 times */
	355	udelay(100);
	356	sdram_addr = 0xff; / 2 times */
	357	udelay(100);
	358	sdram_addr = 0xff; / 3 times */
	359	udelay(100);
	360	sdram_addr = 0xff; / 4 times */
	361	udelay(100);
	362	sdram_addr = 0xff; / 5 times */
	363	udelay(100);
	364	sdram_addr = 0xff; / 6 times */
	365	udelay(100);
	366	sdram_addr = 0xff; / 7 times */
	367	udelay(100);
	368	sdram_addr = 0xff; / 8 times */
	369	udelay(100);
	370
	371	/* Mode register write operation */
6d0f6bcf	372	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
5f820439 DL	373	asm("sync");
	374	*(sdram_addr + 0xcc) = 0xff;
	375	udelay(100);
	376
	377	/* Normal operation */
6d0f6bcf	378	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 \| 0x40000000;
5f820439 DL	379	asm("sync");
	380	*sdram_addr = 0xff;
	381	udelay(100);
5c2ff323 AV	382
	383	/*
	384	* In non-aligned case we don't [normally] use that memory because
	385	* there is a hole.
	386	*/
	387	if (rem)
	388	return 0;
	389	return CONFIG_SYS_LBC_SDRAM_SIZE;
5f820439 DL	390	}
5f820439 DL	391	#else
5c2ff323	392	static int sdram_init(unsigned int base) { return 0; }
5f820439 DL	393	#endif
5f820439 DL	394
3fde9e8b	395	#if defined(CONFIG_OF_BOARD_SETUP)
da6eea0f AV	396	static void ft_board_fixup_qe_usb(void blob, bd_t bd)
	397	{
	398	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
	399	return;
	400
	401	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
	402	"peripheral", sizeof("peripheral"), 1);
	403	}
	404
3fde9e8b	405	void ft_board_setup(void blob, bd_t bd)
bf0b542d	406	{
3fde9e8b	407	ft_cpu_setup(blob, bd);
213bf8c8 GVB	408	#ifdef CONFIG_PCI
	409	ft_pci_setup(blob, bd);
	410	#endif
da6eea0f	411	ft_board_fixup_qe_usb(blob, bd);
24f86843 KP	412	/*
	413	* mpc8360ea pb mds errata 2: RGMII timing
	414	* if on mpc8360ea rev. 2.1,
	415	* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	416	*/
89da44ce	417	if (board_handle_erratum2()) {
24f86843	418	int nodeoffset;
f602082b	419	const char *prop;
363eea9f	420	int path;
24f86843	421
f09880ea	422	nodeoffset = fdt_path_offset(blob, "/aliases");
24f86843	423	if (nodeoffset >= 0) {
5b8bc606 KP	424	#if defined(CONFIG_HAS_ETH0)
5b8bc606 KP	425	/* fixup UCC 1 if using rgmii-id mode */
363eea9f KP	426	prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
	427	if (prop) {
	428	path = fdt_path_offset(blob, prop);
f09880ea	429	prop = fdt_getprop(blob, path,
93e14596	430	"phy-connection-type", 0);
5b8bc606	431	if (prop && (strcmp(prop, "rgmii-id") == 0))
a1964ea5	432	fdt_fixup_phy_connection(blob, path,
865ff856	433	PHY_INTERFACE_MODE_RGMII_RXID);
5b8bc606 KP	434	}
	435	#endif
	436	#if defined(CONFIG_HAS_ETH1)
	437	/* fixup UCC 2 if using rgmii-id mode */
363eea9f KP	438	prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
	439	if (prop) {
	440	path = fdt_path_offset(blob, prop);
f09880ea	441	prop = fdt_getprop(blob, path,
93e14596	442	"phy-connection-type", 0);
5b8bc606	443	if (prop && (strcmp(prop, "rgmii-id") == 0))
a1964ea5	444	fdt_fixup_phy_connection(blob, path,
865ff856	445	PHY_INTERFACE_MODE_RGMII_RXID);
5b8bc606 KP	446	}
5b8bc606 KP	447	#endif
24f86843 KP	448	}
24f86843 KP	449	}
bf0b542d	450	}
3fde9e8b	451	#endif