[people/ms/u-boot.git] / board / freescale / mpc8360emds / mpc8360emds.c

/*
 * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
 * Dave Liu <daveliu@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#include <spd_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <hwconfig.h>
#include <fdt_support.h>
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif
#include "../../../drivers/qe/uec.h"

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{0,  3, 1, 0, 1}, /* TxD0 */
	{0,  4, 1, 0, 1}, /* TxD1 */
	{0,  5, 1, 0, 1}, /* TxD2 */
	{0,  6, 1, 0, 1}, /* TxD3 */
	{1,  6, 1, 0, 3}, /* TxD4 */
	{1,  7, 1, 0, 1}, /* TxD5 */
	{1,  9, 1, 0, 2}, /* TxD6 */
	{1, 10, 1, 0, 2}, /* TxD7 */
	{0,  9, 2, 0, 1}, /* RxD0 */
	{0, 10, 2, 0, 1}, /* RxD1 */
	{0, 11, 2, 0, 1}, /* RxD2 */
	{0, 12, 2, 0, 1}, /* RxD3 */
	{0, 13, 2, 0, 1}, /* RxD4 */
	{1,  1, 2, 0, 2}, /* RxD5 */
	{1,  0, 2, 0, 2}, /* RxD6 */
	{1,  4, 2, 0, 2}, /* RxD7 */
	{0,  7, 1, 0, 1}, /* TX_EN */
	{0,  8, 1, 0, 1}, /* TX_ER */
	{0, 15, 2, 0, 1}, /* RX_DV */
	{0, 16, 2, 0, 1}, /* RX_ER */
	{0,  0, 2, 0, 1}, /* RX_CLK */
	{2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	{2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
	/* GETH2 */
	{0, 17, 1, 0, 1}, /* TxD0 */
	{0, 18, 1, 0, 1}, /* TxD1 */
	{0, 19, 1, 0, 1}, /* TxD2 */
	{0, 20, 1, 0, 1}, /* TxD3 */
	{1,  2, 1, 0, 1}, /* TxD4 */
	{1,  3, 1, 0, 2}, /* TxD5 */
	{1,  5, 1, 0, 3}, /* TxD6 */
	{1,  8, 1, 0, 3}, /* TxD7 */
	{0, 23, 2, 0, 1}, /* RxD0 */
	{0, 24, 2, 0, 1}, /* RxD1 */
	{0, 25, 2, 0, 1}, /* RxD2 */
	{0, 26, 2, 0, 1}, /* RxD3 */
	{0, 27, 2, 0, 1}, /* RxD4 */
	{1, 12, 2, 0, 2}, /* RxD5 */
	{1, 13, 2, 0, 3}, /* RxD6 */
	{1, 11, 2, 0, 2}, /* RxD7 */
	{0, 21, 1, 0, 1}, /* TX_EN */
	{0, 22, 1, 0, 1}, /* TX_ER */
	{0, 29, 2, 0, 1}, /* RX_DV */
	{0, 30, 2, 0, 1}, /* RX_ER */
	{0, 31, 2, 0, 1}, /* RX_CLK */
	{2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	{2,  3, 2, 0, 1}, /* GTX125 - CLK4 */

	{0,  1, 3, 0, 2}, /* MDIO */
	{0,  2, 1, 0, 1}, /* MDC */

	{5,  0, 1, 0, 2}, /* UART2_SOUT */
	{5,  1, 2, 0, 3}, /* UART2_CTS */
	{5,  2, 1, 0, 1}, /* UART2_RTS */
	{5,  3, 2, 0, 2}, /* UART2_SIN */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
static int board_handle_erratum2(void)
{
	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
	       REVID_MINOR(immr->sysconf.spridr) == 1;
}

int board_early_init_f(void)
{
	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;

	/* Enable flash write */
	bcsr[0xa] &= ~0x04;

	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
	if (REVID_MAJOR(immr->sysconf.spridr) == 2)
		bcsr[0xe] = 0x30;

	/* Enable second UART */
	bcsr[0x9] &= ~0x01;

	if (board_handle_erratum2()) {
		void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);

		/*
		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
		 */
		setbits_be32(immap, 0x0c003000);

		/*
		 * IMMR + 0x14AC[20:27] = 10101010
		 * (data delay for both UCC's)
		 */
		clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
	}
	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_PQ_MDS_PIB
	pib_init();
#endif
	return 0;
}

#ifdef CONFIG_UEC_ETH
static uec_info_t uec_info[] = {
#ifdef CONFIG_UEC_ETH1
	STD_UEC_INFO(1),
#endif
#ifdef CONFIG_UEC_ETH2
	STD_UEC_INFO(2),
#endif
};

int board_eth_init(bd_t *bd)
{
	if (board_handle_erratum2()) {
		int i;

		for (i = 0; i < ARRAY_SIZE(uec_info); i++)
			uec_info[i].enet_interface_type = RGMII_RXID;
			uec_info[i].speed = 1000;
	}
	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
}
#endif /* CONFIG_UEC_ETH */

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
static int sdram_init(unsigned int base);

phys_size_t initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;
	u32 lbc_sdram_size;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize DDR ECC byte
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
	if (!msize)
		msize = lbc_sdram_size;

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CONFIG_SYS_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].ar =
	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
	im->ddr.csbnds[0].csbnds = 0x00000007;
	im->ddr.csbnds[1].csbnds = 0x0008000f;

	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;

	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;

	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
	udelay(200);
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;

	return msize;
}
#endif				/*!CONFIG_SYS_SPD_EEPROM */

int checkboard(void)
{
	puts("Board: Freescale MPC8360EMDS\n");
	return 0;
}

/*
 * if MPC8360EMDS is soldered with SDRAM
 */
#ifdef CONFIG_SYS_LB_SDRAM
/*
 * Initialize SDRAM memory on the Local Bus.
 */

static int sdram_init(unsigned int base)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	fsl_lbc_t *lbc = LBC_BASE_ADDR;
	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	int rem = base % sdram_size;
	uint *sdram_addr;

	/* window base address should be aligned to the window size */
	if (rem)
		base = base - rem + sdram_size;

	sdram_addr = (uint *)base;
	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_br(2, base | CONFIG_SYS_BR2);
	set_lbc_or(2, CONFIG_SYS_OR2);
	immap->sysconf.lblaw[2].bar = base;
	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;

	/*setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;	/* Normal Operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;	/* Precharge All Banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	/*
	 * We need do 8 times auto refresh operation.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
	asm("sync");
	*sdram_addr = 0xff;	/* 1 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 2 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 3 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 4 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 5 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 6 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 7 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 8 times */
	udelay(100);

	/* Mode register write operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*(sdram_addr + 0xcc) = 0xff;
	udelay(100);

	/* Normal operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	/*
	 * In non-aligned case we don't [normally] use that memory because
	 * there is a hole.
	 */
	if (rem)
		return 0;
	return CONFIG_SYS_LBC_SDRAM_SIZE;
}
#else
static int sdram_init(unsigned int base) { return 0; }
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
{
	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
		return;

	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
			   "peripheral", sizeof("peripheral"), 1);
}

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	ft_board_fixup_qe_usb(blob, bd);
	/*
	 * mpc8360ea pb mds errata 2: RGMII timing
	 * if on mpc8360ea rev. 2.1,
	 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	 */
	if (board_handle_erratum2()) {
		int nodeoffset;
		const char *prop;
		int path;

		nodeoffset = fdt_path_offset(blob, "/aliases");
		if (nodeoffset >= 0) {
#if defined(CONFIG_HAS_ETH0)
			/* fixup UCC 1 if using rgmii-id mode */
			prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
			if (prop) {
				path = fdt_path_offset(blob, prop);
				prop = fdt_getprop(blob, path,
				                   "phy-connection-type", 0);
				if (prop && (strcmp(prop, "rgmii-id") == 0))
					fdt_fixup_phy_connection(blob, path,
								RGMII_RXID);
			}
#endif
#if defined(CONFIG_HAS_ETH1)
			/* fixup UCC 2 if using rgmii-id mode */
			prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
			if (prop) {
				path = fdt_path_offset(blob, prop);
				prop = fdt_getprop(blob, path,
				                   "phy-connection-type", 0);
				if (prop && (strcmp(prop, "rgmii-id") == 0))
					fdt_fixup_phy_connection(blob, path,
								RGMII_RXID);
			}
#endif
		}
	}
}
#endif
Commit	Line	Data
5f820439	1	/*
a1964ea5	2	* Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
5f820439	3	* Dave Liu <daveliu@freescale.com>
5f820439 DL	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*/
	13
	14	#include <common.h>
	15	#include <ioports.h>
	16	#include <mpc83xx.h>
	17	#include <i2c.h>
5f820439	18	#include <miiphy.h>
5f820439 DL	19	#if defined(CONFIG_PCI)
	20	#include <pci.h>
	21	#endif
5f820439	22	#include <spd_sdram.h>
5f820439	23	#include <asm/mmu.h>
89da44ce	24	#include <asm/io.h>
a1964ea5	25	#include <asm/fsl_enet.h>
b3458d2c	26	#if defined(CONFIG_OF_LIBFDT)
213bf8c8	27	#include <libfdt.h>
213bf8c8	28	#endif
da6eea0f AV	29	#include <hwconfig.h>
da6eea0f AV	30	#include <fdt_support.h>
14778585	31	#if defined(CONFIG_PQ_MDS_PIB)
e58fe957	32	#include "../common/pq-mds-pib.h"
14778585	33	#endif
89da44ce	34	#include "../../../drivers/qe/uec.h"
5f820439	35
7737d5c6 DL	36	const qe_iop_conf_t qe_iop_conf_tab[] = {
	37	/* GETH1 */
	38	{0, 3, 1, 0, 1}, /* TxD0 */
	39	{0, 4, 1, 0, 1}, /* TxD1 */
	40	{0, 5, 1, 0, 1}, /* TxD2 */
	41	{0, 6, 1, 0, 1}, /* TxD3 */
	42	{1, 6, 1, 0, 3}, /* TxD4 */
	43	{1, 7, 1, 0, 1}, /* TxD5 */
	44	{1, 9, 1, 0, 2}, /* TxD6 */
	45	{1, 10, 1, 0, 2}, /* TxD7 */
	46	{0, 9, 2, 0, 1}, /* RxD0 */
	47	{0, 10, 2, 0, 1}, /* RxD1 */
	48	{0, 11, 2, 0, 1}, /* RxD2 */
	49	{0, 12, 2, 0, 1}, /* RxD3 */
	50	{0, 13, 2, 0, 1}, /* RxD4 */
	51	{1, 1, 2, 0, 2}, /* RxD5 */
	52	{1, 0, 2, 0, 2}, /* RxD6 */
	53	{1, 4, 2, 0, 2}, /* RxD7 */
	54	{0, 7, 1, 0, 1}, /* TX_EN */
	55	{0, 8, 1, 0, 1}, /* TX_ER */
	56	{0, 15, 2, 0, 1}, /* RX_DV */
	57	{0, 16, 2, 0, 1}, /* RX_ER */
	58	{0, 0, 2, 0, 1}, /* RX_CLK */
	59	{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	60	{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
	61	/* GETH2 */
	62	{0, 17, 1, 0, 1}, /* TxD0 */
	63	{0, 18, 1, 0, 1}, /* TxD1 */
	64	{0, 19, 1, 0, 1}, /* TxD2 */
	65	{0, 20, 1, 0, 1}, /* TxD3 */
	66	{1, 2, 1, 0, 1}, /* TxD4 */
	67	{1, 3, 1, 0, 2}, /* TxD5 */
	68	{1, 5, 1, 0, 3}, /* TxD6 */
	69	{1, 8, 1, 0, 3}, /* TxD7 */
	70	{0, 23, 2, 0, 1}, /* RxD0 */
	71	{0, 24, 2, 0, 1}, /* RxD1 */
	72	{0, 25, 2, 0, 1}, /* RxD2 */
	73	{0, 26, 2, 0, 1}, /* RxD3 */
	74	{0, 27, 2, 0, 1}, /* RxD4 */
	75	{1, 12, 2, 0, 2}, /* RxD5 */
	76	{1, 13, 2, 0, 3}, /* RxD6 */
	77	{1, 11, 2, 0, 2}, /* RxD7 */
	78	{0, 21, 1, 0, 1}, /* TX_EN */
	79	{0, 22, 1, 0, 1}, /* TX_ER */
	80	{0, 29, 2, 0, 1}, /* RX_DV */
	81	{0, 30, 2, 0, 1}, /* RX_ER */
	82	{0, 31, 2, 0, 1}, /* RX_CLK */
	83	{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	84	{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
	85
	86	{0, 1, 3, 0, 2}, /* MDIO */
	87	{0, 2, 1, 0, 1}, /* MDC */
	88
651d96f7 AV	89	{5, 0, 1, 0, 2}, /* UART2_SOUT */
	90	{5, 1, 2, 0, 3}, /* UART2_CTS */
	91	{5, 2, 1, 0, 1}, /* UART2_RTS */
	92	{5, 3, 2, 0, 2}, /* UART2_SIN */
	93
7737d5c6 DL	94	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	95	};
	96
89da44ce AV	97	/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
89da44ce AV	98	static int board_handle_erratum2(void)
5f820439	99	{
89da44ce	100	const immap_t immr = (immap_t )CONFIG_SYS_IMMR;
3fc0bd15	101
89da44ce AV	102	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
	103	REVID_MINOR(immr->sysconf.spridr) == 1;
	104	}
	105
	106	int board_early_init_f(void)
	107	{
6d0f6bcf	108	const immap_t immr = (immap_t )CONFIG_SYS_IMMR;
89da44ce	109	u8 bcsr = (u8 )CONFIG_SYS_BCSR;
5f820439 DL	110
	111	/* Enable flash write */
	112	bcsr[0xa] &= ~0x04;
	113
e5c4ade4 KP	114	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
e5c4ade4 KP	115	if (REVID_MAJOR(immr->sysconf.spridr) == 2)
3fc0bd15 KP	116	bcsr[0xe] = 0x30;
3fc0bd15 KP	117
651d96f7 AV	118	/* Enable second UART */
	119	bcsr[0x9] &= ~0x01;
	120
89da44ce AV	121	if (board_handle_erratum2()) {
	122	void immap = (immap_t )(CONFIG_SYS_IMMR + 0x14a8);
	123
	124	/*
	125	* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
	126	* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
	127	*/
	128	setbits_be32(immap, 0x0c003000);
	129
	130	/*
	131	* IMMR + 0x14AC[20:27] = 10101010
	132	* (data delay for both UCC's)
	133	*/
	134	clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
	135	}
5f820439 DL	136	return 0;
	137	}
	138
14778585 TL	139	int board_early_init_r(void)
	140	{
	141	#ifdef CONFIG_PQ_MDS_PIB
	142	pib_init();
	143	#endif
	144	return 0;
	145	}
	146
89da44ce AV	147	#ifdef CONFIG_UEC_ETH
	148	static uec_info_t uec_info[] = {
	149	#ifdef CONFIG_UEC_ETH1
	150	STD_UEC_INFO(1),
	151	#endif
	152	#ifdef CONFIG_UEC_ETH2
	153	STD_UEC_INFO(2),
	154	#endif
	155	};
	156
	157	int board_eth_init(bd_t *bd)
	158	{
	159	if (board_handle_erratum2()) {
	160	int i;
	161
	162	for (i = 0; i < ARRAY_SIZE(uec_info); i++)
582c55a0 HS	163	uec_info[i].enet_interface_type = RGMII_RXID;
582c55a0 HS	164	uec_info[i].speed = 1000;
89da44ce AV	165	}
	166	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
	167	}
	168	#endif /* CONFIG_UEC_ETH */
	169
9adda545	170	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5f820439 DL	171	extern void ddr_enable_ecc(unsigned int dram_size);
	172	#endif
	173	int fixed_sdram(void);
5c2ff323	174	static int sdram_init(unsigned int base);
5f820439	175
9973e3c6	176	phys_size_t initdram(int board_type)
5f820439	177	{
6d0f6bcf	178	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
5f820439	179	u32 msize = 0;
034477bb	180	u32 lbc_sdram_size;
5f820439 DL	181
	182	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	183	return -1;
	184
	185	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	186	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
5f820439 DL	187	#if defined(CONFIG_SPD_EEPROM)
	188	msize = spd_sdram();
	189	#else
	190	msize = fixed_sdram();
	191	#endif
	192
9adda545	193	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5f820439 DL	194	/*
	195	* Initialize DDR ECC byte
	196	*/
	197	ddr_enable_ecc(msize * 1024 * 1024);
	198	#endif
	199	/*
	200	* Initialize SDRAM if it is on local bus.
	201	*/
034477bb AV	202	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
	203	if (!msize)
	204	msize = lbc_sdram_size;
bbea46f7	205
5f820439 DL	206	/* return total bus SDRAM size(bytes) -- DDR */
	207	return (msize * 1024 * 1024);
	208	}
	209
	210	#if !defined(CONFIG_SPD_EEPROM)
	211	/*************************************************************************
	212	* fixed sdram init -- doesn't use serial presence detect.
	213	************************************************************************/
	214	int fixed_sdram(void)
	215	{
6d0f6bcf	216	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
5f820439 DL	217	u32 msize = 0;
	218	u32 ddr_size;
	219	u32 ddr_size_log2;
	220
6d0f6bcf	221	msize = CONFIG_SYS_DDR_SIZE;
5f820439 DL	222	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	223	(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
	224	if (ddr_size & 1) {
	225	return -1;
	226	}
	227	}
	228	im->sysconf.ddrlaw[0].ar =
	229	LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
6d0f6bcf	230	#if (CONFIG_SYS_DDR_SIZE != 256)
5f820439 DL	231	#warning Currenly any ddr size other than 256 is not supported
5f820439 DL	232	#endif
d61853cf	233	#ifdef CONFIG_DDR_II
6d0f6bcf JCPV	234	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	235	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	236	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	237	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	238	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	239	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	240	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	241	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	242	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	243	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	244	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	245	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
d61853cf	246	#else
5f820439 DL	247	im->ddr.csbnds[0].csbnds = 0x00000007;
	248	im->ddr.csbnds[1].csbnds = 0x0008000f;
	249
6d0f6bcf JCPV	250	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
6d0f6bcf JCPV	251	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
5f820439	252
6d0f6bcf JCPV	253	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	254	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	255	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
5f820439	256
6d0f6bcf JCPV	257	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
6d0f6bcf JCPV	258	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
d61853cf	259	#endif
5f820439 DL	260	udelay(200);
	261	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	262
	263	return msize;
	264	}
6d0f6bcf	265	#endif /!CONFIG_SYS_SPD_EEPROM /
5f820439 DL	266
	267	int checkboard(void)
	268	{
	269	puts("Board: Freescale MPC8360EMDS\n");
	270	return 0;
	271	}
	272
	273	/*
	274	* if MPC8360EMDS is soldered with SDRAM
	275	*/
5c2ff323	276	#ifdef CONFIG_SYS_LB_SDRAM
5f820439 DL	277	/*
	278	* Initialize SDRAM memory on the Local Bus.
	279	*/
	280
5c2ff323	281	static int sdram_init(unsigned int base)
5f820439	282	{
6d0f6bcf	283	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
f51cdaf1	284	fsl_lbc_t *lbc = LBC_BASE_ADDR;
5c2ff323 AV	285	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	286	int rem = base % sdram_size;
	287	uint *sdram_addr;
5f820439	288
5c2ff323 AV	289	/* window base address should be aligned to the window size */
	290	if (rem)
	291	base = base - rem + sdram_size;
	292
	293	sdram_addr = (uint *)base;
5f820439	294	/*
5c2ff323	295	* Setup SDRAM Base and Option Registers
5f820439	296	*/
f51cdaf1 BB	297	set_lbc_br(2, base \| CONFIG_SYS_BR2);
f51cdaf1 BB	298	set_lbc_or(2, CONFIG_SYS_OR2);
5c2ff323 AV	299	immap->sysconf.lblaw[2].bar = base;
	300	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
	301
5f820439	302	/setup mtrpt, lsrt and lbcr for LB bus /
6d0f6bcf JCPV	303	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	304	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	305	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
5f820439 DL	306	asm("sync");
	307
	308	/*
	309	* Configure the SDRAM controller Machine Mode Register.
	310	*/
6d0f6bcf JCPV	311	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
6d0f6bcf JCPV	312	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
5f820439 DL	313	asm("sync");
	314	*sdram_addr = 0xff;
	315	udelay(100);
	316
	317	/*
	318	* We need do 8 times auto refresh operation.
	319	*/
6d0f6bcf	320	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
5f820439 DL	321	asm("sync");
	322	sdram_addr = 0xff; / 1 times */
	323	udelay(100);
	324	sdram_addr = 0xff; / 2 times */
	325	udelay(100);
	326	sdram_addr = 0xff; / 3 times */
	327	udelay(100);
	328	sdram_addr = 0xff; / 4 times */
	329	udelay(100);
	330	sdram_addr = 0xff; / 5 times */
	331	udelay(100);
	332	sdram_addr = 0xff; / 6 times */
	333	udelay(100);
	334	sdram_addr = 0xff; / 7 times */
	335	udelay(100);
	336	sdram_addr = 0xff; / 8 times */
	337	udelay(100);
	338
	339	/* Mode register write operation */
6d0f6bcf	340	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
5f820439 DL	341	asm("sync");
	342	*(sdram_addr + 0xcc) = 0xff;
	343	udelay(100);
	344
	345	/* Normal operation */
6d0f6bcf	346	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 \| 0x40000000;
5f820439 DL	347	asm("sync");
	348	*sdram_addr = 0xff;
	349	udelay(100);
5c2ff323 AV	350
	351	/*
	352	* In non-aligned case we don't [normally] use that memory because
	353	* there is a hole.
	354	*/
	355	if (rem)
	356	return 0;
	357	return CONFIG_SYS_LBC_SDRAM_SIZE;
5f820439 DL	358	}
5f820439 DL	359	#else
5c2ff323	360	static int sdram_init(unsigned int base) { return 0; }
5f820439 DL	361	#endif
5f820439 DL	362
3fde9e8b	363	#if defined(CONFIG_OF_BOARD_SETUP)
da6eea0f AV	364	static void ft_board_fixup_qe_usb(void blob, bd_t bd)
	365	{
	366	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
	367	return;
	368
	369	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
	370	"peripheral", sizeof("peripheral"), 1);
	371	}
	372
3fde9e8b	373	void ft_board_setup(void blob, bd_t bd)
bf0b542d	374	{
3fde9e8b	375	ft_cpu_setup(blob, bd);
213bf8c8 GVB	376	#ifdef CONFIG_PCI
	377	ft_pci_setup(blob, bd);
	378	#endif
da6eea0f	379	ft_board_fixup_qe_usb(blob, bd);
24f86843 KP	380	/*
	381	* mpc8360ea pb mds errata 2: RGMII timing
	382	* if on mpc8360ea rev. 2.1,
	383	* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	384	*/
89da44ce	385	if (board_handle_erratum2()) {
24f86843	386	int nodeoffset;
f602082b	387	const char *prop;
363eea9f	388	int path;
24f86843	389
f09880ea	390	nodeoffset = fdt_path_offset(blob, "/aliases");
24f86843	391	if (nodeoffset >= 0) {
5b8bc606 KP	392	#if defined(CONFIG_HAS_ETH0)
5b8bc606 KP	393	/* fixup UCC 1 if using rgmii-id mode */
363eea9f KP	394	prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
	395	if (prop) {
	396	path = fdt_path_offset(blob, prop);
f09880ea KP	397	prop = fdt_getprop(blob, path,
f09880ea KP	398	"phy-connection-type", 0);
5b8bc606	399	if (prop && (strcmp(prop, "rgmii-id") == 0))
a1964ea5 KG	400	fdt_fixup_phy_connection(blob, path,
a1964ea5 KG	401	RGMII_RXID);
5b8bc606 KP	402	}
	403	#endif
	404	#if defined(CONFIG_HAS_ETH1)
	405	/* fixup UCC 2 if using rgmii-id mode */
363eea9f KP	406	prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
	407	if (prop) {
	408	path = fdt_path_offset(blob, prop);
f09880ea KP	409	prop = fdt_getprop(blob, path,
f09880ea KP	410	"phy-connection-type", 0);
5b8bc606	411	if (prop && (strcmp(prop, "rgmii-id") == 0))
a1964ea5 KG	412	fdt_fixup_phy_connection(blob, path,
a1964ea5 KG	413	RGMII_RXID);
5b8bc606 KP	414	}
5b8bc606 KP	415	#endif
24f86843 KP	416	}
24f86843 KP	417	}
bf0b542d	418	}
3fde9e8b	419	#endif