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Add wait flags to support board/chip specific delays
[people/ms/u-boot.git] / board / freescale / mpc8360erdk / nand.c
CommitLineData
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1/*
2 * MPC8360E-RDK support for the NAND on FSL UPM
3 *
4 * Copyright (C) 2007 MontaVista Software, Inc.
5 * Anton Vorontsov <avorontsov@ru.mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <config.h>
14#include <common.h>
15#include <asm/io.h>
16#include <asm/immap_83xx.h>
17#include <linux/mtd/mtd.h>
18#include <linux/mtd/fsl_upm.h>
19#include <nand.h>
20
6d0f6bcf 21static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
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22
23static const u32 upm_array[] = {
24 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
25 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */
26 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */
27 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
28 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
29 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
30 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
31 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
32 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
33 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
34 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
35 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
36 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
37 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
38 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
39 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
40};
41
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42static void upm_setup(struct fsl_upm *upm)
43{
44 int i;
45
46 /* write upm array */
47 out_be32(upm->mxmr, MxMR_OP_WARR);
48
49 for (i = 0; i < 64; i++) {
50 out_be32(upm->mdr, upm_array[i]);
51 out_8(upm->io_addr, 0x0);
52 }
53
54 /* normal operation */
55 out_be32(upm->mxmr, MxMR_OP_NORM);
56 while (in_be32(upm->mxmr) != MxMR_OP_NORM)
57 eieio();
58}
59
e93c1c16 60static int dev_ready(int chip_nr)
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61{
62 if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
63 debug("nand ready\n");
64 return 1;
65 }
66
67 debug("nand busy\n");
68 return 0;
69}
70
71static struct fsl_upm_nand fun = {
72 .upm = {
6d0f6bcf 73 .io_addr = (void *)CONFIG_SYS_NAND_BASE,
7ad95949 74 },
b4fe1a71 75 .width = 8,
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76 .upm_cmd_offset = 8,
77 .upm_addr_offset = 16,
78 .dev_ready = dev_ready,
33846df2 79 .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
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80 .chip_delay = 50,
81};
82
83int board_nand_init(struct nand_chip *nand)
84{
85 fun.upm.mxmr = &im->lbus.mamr;
86 fun.upm.mdr = &im->lbus.mdr;
87 fun.upm.mar = &im->lbus.mar;
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88
89 upm_setup(&fun.upm);
90
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91 return fsl_upm_nand_init(nand, &fun);
92}