[people/ms/u-boot.git] / board / freescale / mpc8540ads / mpc8540ads.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);

int checkboard (void)
{
	puts("Board: ADS\n");

#ifdef CONFIG_PCI
	printf("PCI1: 32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#else
	printf("PCI1: disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init();

	return 0;
}


phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
	    volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	    uint temp_ddrdll = 0;

	    /*
	     * Work around to stabilize DDR DLL
	     */
	    temp_ddrdll = gur->ddrdllcr;
	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	    asm("sync;isync;msync");
	}
#endif

#ifdef CONFIG_SPD_EEPROM
	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;
#else
	dram_size = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	/*
	 * Initialize SDRAM.
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}


/*
 * Initialize Local Bus
 */

void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
	 * If localbus freq is > 133MHz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */

	} else if (lbc_hz >= 133) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
}


/*
 * Initialize SDRAM memory on the Local Bus.
 */

void
sdram_init(void)
{
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;

	puts("    SDRAM: ");
	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");

	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("sync");

	/*
	 * Configure the SDRAM controller.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
  #ifndef CONFIG_SYS_RAMBOOT
	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
  #endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */


static struct pci_controller hose;

#endif	/* CONFIG_PCI */


void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}


#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = hose.last_busno - hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif
Commit	Line	Data
9617c8d4	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003, Motorola Inc.
	4	* Xianghua Xiao, (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27
42d1f039	28	#include <common.h>
9aea9530	29	#include <pci.h>
42d1f039	30	#include <asm/processor.h>
9617c8d4	31	#include <asm/mmu.h>
42d1f039	32	#include <asm/immap_85xx.h>
9617c8d4	33	#include <asm/fsl_ddr_sdram.h>
0fd5ec66 KG	34	#include <libfdt.h>
0fd5ec66 KG	35	#include <fdt_support.h>
40d5fa35	36
d9b94f28	37	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
0ac6f8b7	38	extern void ddr_enable_ecc(unsigned int dram_size);
97d80fc3 WD	39	#endif
97d80fc3 WD	40
9aea9530	41	void local_bus_init(void);
0ac6f8b7 WD	42	void sdram_init(void);
0ac6f8b7 WD	43	long int fixed_sdram(void);
97d80fc3	44
42d1f039 WD	45	int checkboard (void)
42d1f039 WD	46	{
97d80fc3	47	puts("Board: ADS\n");
0ac6f8b7 WD	48
0ac6f8b7 WD	49	#ifdef CONFIG_PCI
8ca78f2c	50	printf("PCI1: 32 bit, %d MHz (compiled)\n",
0ac6f8b7 WD	51	CONFIG_SYS_CLK_FREQ / 1000000);
0ac6f8b7 WD	52	#else
8ca78f2c	53	printf("PCI1: disabled\n");
0ac6f8b7 WD	54	#endif
0ac6f8b7 WD	55
9aea9530 WD	56	/*
	57	* Initialize local bus.
	58	*/
	59	local_bus_init();
	60
97d80fc3	61	return 0;
42d1f039 WD	62	}
42d1f039 WD	63
97d80fc3	64
9973e3c6	65	phys_size_t
0ac6f8b7	66	initdram(int board_type)
42d1f039 WD	67	{
42d1f039 WD	68	long dram_size = 0;
97d80fc3	69
0ac6f8b7	70	puts("Initializing\n");
42d1f039	71
0ac6f8b7 WD	72	#if defined(CONFIG_DDR_DLL)
0ac6f8b7 WD	73	{
6d0f6bcf	74	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
9aea9530 WD	75	uint temp_ddrdll = 0;
	76
	77	/*
	78	* Work around to stabilize DDR DLL
	79	*/
	80	temp_ddrdll = gur->ddrdllcr;
	81	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) \| 0x80000000;
	82	asm("sync;isync;msync");
0ac6f8b7	83	}
42d1f039 WD	84	#endif
42d1f039 WD	85
9617c8d4 KG	86	#ifdef CONFIG_SPD_EEPROM
	87	dram_size = fsl_ddr_sdram();
	88	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	89
	90	dram_size *= 0x100000;
42d1f039	91	#else
9617c8d4	92	dram_size = fixed_sdram();
42d1f039 WD	93	#endif
42d1f039 WD	94
d9b94f28	95	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
0ac6f8b7 WD	96	/*
	97	* Initialize and enable DDR ECC.
	98	*/
	99	ddr_enable_ecc(dram_size);
	100	#endif
	101
	102	/*
	103	* Initialize SDRAM.
	104	*/
	105	sdram_init();
	106
	107	puts(" DDR: ");
	108	return dram_size;
	109	}
	110
	111
	112	/*
9aea9530	113	* Initialize Local Bus
0ac6f8b7 WD	114	*/
0ac6f8b7 WD	115
9aea9530 WD	116	void
9aea9530 WD	117	local_bus_init(void)
0ac6f8b7	118	{
6d0f6bcf	119	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	120	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
0ac6f8b7	121
9aea9530 WD	122	uint clkdiv;
	123	uint lbc_hz;
	124	sys_info_t sysinfo;
0ac6f8b7 WD	125
0ac6f8b7 WD	126	/*
9aea9530 WD	127	* Errata LBC11.
9aea9530 WD	128	* Fix Local Bus clock glitch when DLL is enabled.
0ac6f8b7	129	*
8ed44d91 WD	130	* If localbus freq is < 66MHz, DLL bypass mode must be used.
8ed44d91 WD	131	* If localbus freq is > 133MHz, DLL can be safely enabled.
9aea9530	132	* Between 66 and 133, the DLL is enabled with an override workaround.
0ac6f8b7	133	*/
9aea9530 WD	134
9aea9530 WD	135	get_sys_info(&sysinfo);
a5d212a2	136	clkdiv = lbc->lcrr & LCRR_CLKDIV;
9aea9530 WD	137	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	138
	139	if (lbc_hz < 66) {
6d0f6bcf	140	lbc->lcrr = CONFIG_SYS_LBC_LCRR \| 0x80000000; /* DLL Bypass */
9aea9530 WD	141
9aea9530 WD	142	} else if (lbc_hz >= 133) {
6d0f6bcf	143	lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
0ac6f8b7	144
42d1f039	145	} else {
0ac6f8b7 WD	146	/*
	147	* On REV1 boards, need to change CLKDIV before enable DLL.
	148	* Default CLKDIV is 8, change it to 4 temporarily.
	149	*/
9aea9530	150	uint pvr = get_pvr();
0ac6f8b7	151	uint temp_lbcdll = 0;
97d80fc3 WD	152
97d80fc3 WD	153	if (pvr == PVR_85xx_REV1) {
9aea9530	154	/* FIXME: Justify the high bit here. */
0ac6f8b7	155	lbc->lcrr = 0x10000004;
97d80fc3	156	}
0ac6f8b7	157
6d0f6bcf	158	lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
9aea9530 WD	159	udelay(200);
	160
	161	/*
	162	* Sample LBC DLL ctrl reg, upshift it to set the
	163	* override bits.
	164	*/
42d1f039	165	temp_lbcdll = gur->lbcdllcr;
9aea9530 WD	166	gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) \| 0x80000000);
9aea9530 WD	167	asm("sync;isync;msync");
42d1f039	168	}
9aea9530 WD	169	}
	170
	171
	172	/*
	173	* Initialize SDRAM memory on the Local Bus.
	174	*/
	175
	176	void
	177	sdram_init(void)
	178	{
f51cdaf1	179	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	180	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
9aea9530 WD	181
9aea9530 WD	182	puts(" SDRAM: ");
6d0f6bcf	183	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
0ac6f8b7 WD	184
	185	/*
	186	* Setup SDRAM Base and Option Registers
	187	*/
f51cdaf1 BB	188	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
f51cdaf1 BB	189	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
6d0f6bcf	190	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
9aea9530	191	asm("msync");
0ac6f8b7	192
6d0f6bcf JCPV	193	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	194	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
9aea9530	195	asm("sync");
0ac6f8b7 WD	196
	197	/*
	198	* Configure the SDRAM controller.
	199	*/
6d0f6bcf	200	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
9aea9530	201	asm("sync");
0ac6f8b7	202	*sdram_addr = 0xff;
9aea9530 WD	203	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	204	udelay(100);
0ac6f8b7	205
6d0f6bcf	206	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
9aea9530	207	asm("sync");
0ac6f8b7	208	*sdram_addr = 0xff;
9aea9530 WD	209	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	210	udelay(100);
0ac6f8b7	211
6d0f6bcf	212	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
9aea9530	213	asm("sync");
0ac6f8b7	214	*sdram_addr = 0xff;
9aea9530 WD	215	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	216	udelay(100);
42d1f039	217
6d0f6bcf	218	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
9aea9530	219	asm("sync");
0ac6f8b7	220	*sdram_addr = 0xff;
9aea9530 WD	221	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	222	udelay(100);
42d1f039	223
6d0f6bcf	224	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
9aea9530	225	asm("sync");
0ac6f8b7	226	*sdram_addr = 0xff;
9aea9530 WD	227	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	228	udelay(100);
42d1f039 WD	229	}
42d1f039 WD	230
42d1f039 WD	231	#if !defined(CONFIG_SPD_EEPROM)
	232	/*************************************************************************
	233	* fixed sdram init -- doesn't use serial presence detect.
	234	************************************************************************/
	235	long int fixed_sdram (void)
	236	{
6d0f6bcf JCPV	237	#ifndef CONFIG_SYS_RAMBOOT
	238	volatile ccsr_ddr_t ddr= (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
	239
	240	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	241	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	242	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	243	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	244	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	245	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
42d1f039 WD	246	#if defined (CONFIG_DDR_ECC)
	247	ddr->err_disable = 0x0000000D;
	248	ddr->err_sbe = 0x00ff0000;
	249	#endif
	250	asm("sync;isync;msync");
	251	udelay(500);
	252	#if defined (CONFIG_DDR_ECC)
	253	/* Enable ECC checking */
6d0f6bcf	254	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL \| 0x20000000);
42d1f039	255	#else
6d0f6bcf	256	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
42d1f039 WD	257	#endif
	258	asm("sync; isync; msync");
	259	udelay(500);
	260	#endif
6d0f6bcf	261	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
42d1f039 WD	262	}
42d1f039 WD	263	#endif /* !defined(CONFIG_SPD_EEPROM) */
9aea9530 WD	264
	265
	266	#if defined(CONFIG_PCI)
	267	/*
	268	* Initialize PCI Devices, report devices found.
	269	*/
	270
9aea9530	271
52c7a68b	272	static struct pci_controller hose;
9aea9530 WD	273
	274	#endif /* CONFIG_PCI */
	275
	276
	277	void
	278	pci_init_board(void)
	279	{
	280	#ifdef CONFIG_PCI
9aea9530 WD	281	pci_mpc85xx_init(&hose);
	282	#endif /* CONFIG_PCI */
	283	}
40d5fa35 MM	284
40d5fa35 MM	285
0fd5ec66	286	#if defined(CONFIG_OF_BOARD_SETUP)
40d5fa35 MM	287	void
	288	ft_board_setup(void blob, bd_t bd)
	289	{
0fd5ec66 KG	290	int node, tmp[2];
0fd5ec66 KG	291	const char *path;
40d5fa35 MM	292
	293	ft_cpu_setup(blob, bd);
	294
0fd5ec66 KG	295	node = fdt_path_offset(blob, "/aliases");
	296	tmp[0] = 0;
	297	if (node >= 0) {
	298	#ifdef CONFIG_PCI
	299	path = fdt_getprop(blob, node, "pci0", NULL);
	300	if (path) {
	301	tmp[1] = hose.last_busno - hose.first_busno;
	302	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	303	}
	304	#endif
40d5fa35 MM	305	}
	306	}
	307	#endif