projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0db37dc2 KG |
1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * (C) Copyright 2000 | |
| 5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 0db37dc2 KG |
8 | */ |
| 9 | ||
| 10 | #include <common.h> | |
| 11 | #include <asm/mmu.h> | |
| 12 | ||
| 13 | struct fsl_e_tlb_entry tlb_table[] = { | |
| 14 | /* TLB 0 - for temp stack in cache */ | |
| 6d0f6bcf | 15 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
| 0db37dc2 KG |
16 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 17 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 6d0f6bcf | 18 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
| 0db37dc2 KG |
19 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 20 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 6d0f6bcf | 21 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
| 0db37dc2 KG |
22 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 23 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 6d0f6bcf | 24 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
| 0db37dc2 KG |
25 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 26 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 27 | ||
| 28 | /* | |
| 29 | * TLB 0: 16M Non-cacheable, guarded | |
| 30 | * 0xff000000 16M FLASH | |
| 31 | * Out of reset this entry is only 4K. | |
| 32 | */ | |
| 6d0f6bcf | 33 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, |
| 0db37dc2 KG |
34 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 35 | 0, 0, BOOKE_PAGESZ_16M, 1), | |
| 36 | ||
| 37 | /* | |
| 38 | * TLB 1: 256M Non-cacheable, guarded | |
| 39 | * 0x80000000 256M PCI1 MEM First half | |
| 40 | */ | |
| 5af0fdd8 | 41 | SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, |
| 0db37dc2 KG |
42 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 43 | 0, 1, BOOKE_PAGESZ_256M, 1), | |
| 44 | ||
| 45 | /* | |
| 46 | * TLB 2: 256M Non-cacheable, guarded | |
| 47 | * 0x90000000 256M PCI1 MEM Second half | |
| 48 | */ | |
| 5af0fdd8 | 49 | SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, |
| 0db37dc2 KG |
50 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 51 | 0, 2, BOOKE_PAGESZ_256M, 1), | |
| 52 | ||
| 53 | /* | |
| 54 | * TLB 3: 256M Non-cacheable, guarded | |
| 55 | * 0xa0000000 256M PCI2 MEM First half | |
| 56 | */ | |
| 5af0fdd8 | 57 | SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, |
| 0db37dc2 KG |
58 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 59 | 0, 3, BOOKE_PAGESZ_256M, 1), | |
| 60 | ||
| 61 | /* | |
| 62 | * TLB 4: 256M Non-cacheable, guarded | |
| 63 | * 0xb0000000 256M PCI2 MEM Second half | |
| 64 | */ | |
| 5af0fdd8 | 65 | SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, |
| 0db37dc2 KG |
66 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 67 | 0, 4, BOOKE_PAGESZ_256M, 1), | |
| 68 | ||
| 69 | /* | |
| 70 | * TLB 5: 64M Non-cacheable, guarded | |
| 71 | * 0xe000_0000 1M CCSRBAR | |
| 72 | * 0xe200_0000 16M PCI1 IO | |
| 73 | * 0xe300_0000 16M PCI2 IO | |
| 74 | */ | |
| 6d0f6bcf | 75 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
| 0db37dc2 KG |
76 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 77 | 0, 5, BOOKE_PAGESZ_64M, 1), | |
| 78 | ||
| 79 | /* | |
| 80 | * TLB 6: 64M Cacheable, non-guarded | |
| 81 | * 0xf000_0000 64M LBC SDRAM | |
| 82 | */ | |
| 6d0f6bcf | 83 | SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, |
| 0db37dc2 KG |
84 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 85 | 0, 6, BOOKE_PAGESZ_64M, 1), | |
| 86 | ||
| 87 | /* | |
| 88 | * TLB 7: 1M Non-cacheable, guarded | |
| 89 | * 0xf8000000 1M CADMUS registers | |
| 90 | */ | |
| 91 | SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, | |
| 92 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
| 93 | 0, 7, BOOKE_PAGESZ_1M, 1), | |
| 94 | }; | |
| 95 | ||
| 96 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |