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25d83d7f JL |
1 | /* |
2 | * Copyright 2007 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <command.h> | |
837f1ba0 | 25 | #include <pci.h> |
25d83d7f | 26 | #include <asm/processor.h> |
1167a2fd | 27 | #include <asm/mmu.h> |
25d83d7f | 28 | #include <asm/immap_85xx.h> |
837f1ba0 | 29 | #include <asm/immap_fsl_pci.h> |
1167a2fd | 30 | #include <asm/fsl_ddr_sdram.h> |
56a92705 | 31 | #include <asm/io.h> |
25d83d7f | 32 | #include <miiphy.h> |
addce57e KG |
33 | #include <libfdt.h> |
34 | #include <fdt_support.h> | |
216f2a71 | 35 | #include <tsec.h> |
0b252f50 | 36 | #include <netdev.h> |
25d83d7f JL |
37 | |
38 | #include "../common/pixis.h" | |
216f2a71 | 39 | #include "../common/sgmii_riser.h" |
25d83d7f | 40 | |
25d83d7f JL |
41 | int checkboard (void) |
42 | { | |
6d0f6bcf JCPV |
43 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
44 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); | |
45 | volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); | |
25d83d7f | 46 | |
2f15278c | 47 | if ((uint)&gur->porpllsr != 0xe00e0000) { |
9b55a253 | 48 | printf("immap size error %lx\n",(ulong)&gur->porpllsr); |
25d83d7f | 49 | } |
e5852787 KG |
50 | printf ("Board: MPC8544DS, System ID: 0x%02x, " |
51 | "System Version: 0x%02x, FPGA Version: 0x%02x\n", | |
52 | in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), | |
53 | in8(PIXIS_BASE + PIXIS_PVER)); | |
25d83d7f | 54 | |
837f1ba0 ES |
55 | lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ |
56 | lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ | |
57 | ecm->eedr = 0xffffffff; /* Clear ecm errors */ | |
58 | ecm->eeer = 0xffffffff; /* Enable ecm errors */ | |
59 | ||
25d83d7f JL |
60 | return 0; |
61 | } | |
62 | ||
9973e3c6 | 63 | phys_size_t |
25d83d7f JL |
64 | initdram(int board_type) |
65 | { | |
66 | long dram_size = 0; | |
67 | ||
68 | puts("Initializing\n"); | |
69 | ||
1167a2fd KG |
70 | dram_size = fsl_ddr_sdram(); |
71 | ||
72 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); | |
73 | ||
74 | dram_size *= 0x100000; | |
25d83d7f | 75 | |
25d83d7f JL |
76 | puts(" DDR: "); |
77 | return dram_size; | |
78 | } | |
79 | ||
837f1ba0 ES |
80 | #ifdef CONFIG_PCI1 |
81 | static struct pci_controller pci1_hose; | |
82 | #endif | |
83 | ||
84 | #ifdef CONFIG_PCIE1 | |
85 | static struct pci_controller pcie1_hose; | |
86 | #endif | |
87 | ||
88 | #ifdef CONFIG_PCIE2 | |
89 | static struct pci_controller pcie2_hose; | |
90 | #endif | |
91 | ||
92 | #ifdef CONFIG_PCIE3 | |
93 | static struct pci_controller pcie3_hose; | |
94 | #endif | |
95 | ||
2dba0dea KG |
96 | extern int fsl_pci_setup_inbound_windows(struct pci_region *r); |
97 | extern void fsl_pci_init(struct pci_controller *hose); | |
98 | ||
837f1ba0 ES |
99 | int first_free_busno=0; |
100 | ||
101 | void | |
102 | pci_init_board(void) | |
103 | { | |
6d0f6bcf | 104 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
837f1ba0 ES |
105 | uint devdisr = gur->devdisr; |
106 | uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; | |
107 | uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; | |
108 | ||
109 | debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", | |
110 | devdisr, io_sel, host_agent); | |
111 | ||
112 | if (io_sel & 1) { | |
113 | if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) | |
114 | printf (" eTSEC1 is in sgmii mode.\n"); | |
115 | if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) | |
116 | printf (" eTSEC3 is in sgmii mode.\n"); | |
117 | } | |
118 | ||
119 | #ifdef CONFIG_PCIE3 | |
120 | { | |
6d0f6bcf | 121 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; |
837f1ba0 | 122 | struct pci_controller *hose = &pcie3_hose; |
f97abbfb | 123 | int pcie_ep = (host_agent == 1); |
9afc2ef0 | 124 | int pcie_configured = io_sel >= 6; |
2dba0dea | 125 | struct pci_region *r = hose->regions; |
837f1ba0 ES |
126 | |
127 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ | |
128 | printf ("\n PCIE3 connected to ULI as %s (base address %x)", | |
129 | pcie_ep ? "End Point" : "Root Complex", | |
130 | (uint)pci); | |
131 | if (pci->pme_msg_det) { | |
132 | pci->pme_msg_det = 0xffffffff; | |
133 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
134 | } | |
135 | printf ("\n"); | |
136 | ||
137 | /* inbound */ | |
2dba0dea | 138 | r += fsl_pci_setup_inbound_windows(r); |
837f1ba0 ES |
139 | |
140 | /* outbound memory */ | |
2dba0dea | 141 | pci_set_region(r++, |
10795f42 | 142 | CONFIG_SYS_PCIE3_MEM_BUS, |
6d0f6bcf JCPV |
143 | CONFIG_SYS_PCIE3_MEM_PHYS, |
144 | CONFIG_SYS_PCIE3_MEM_SIZE, | |
837f1ba0 ES |
145 | PCI_REGION_MEM); |
146 | ||
147 | /* outbound io */ | |
2dba0dea | 148 | pci_set_region(r++, |
6d0f6bcf JCPV |
149 | CONFIG_SYS_PCIE3_IO_BASE, |
150 | CONFIG_SYS_PCIE3_IO_PHYS, | |
151 | CONFIG_SYS_PCIE3_IO_SIZE, | |
837f1ba0 ES |
152 | PCI_REGION_IO); |
153 | ||
10795f42 | 154 | #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 |
837f1ba0 | 155 | /* outbound memory */ |
2dba0dea | 156 | pci_set_region(r++, |
10795f42 | 157 | CONFIG_SYS_PCIE3_MEM_BUS2, |
6d0f6bcf JCPV |
158 | CONFIG_SYS_PCIE3_MEM_PHYS2, |
159 | CONFIG_SYS_PCIE3_MEM_SIZE2, | |
837f1ba0 | 160 | PCI_REGION_MEM); |
837f1ba0 | 161 | #endif |
2dba0dea | 162 | hose->region_count = r - hose->regions; |
837f1ba0 ES |
163 | hose->first_busno=first_free_busno; |
164 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
165 | ||
166 | fsl_pci_init(hose); | |
167 | ||
168 | first_free_busno=hose->last_busno+1; | |
169 | printf (" PCIE3 on bus %02x - %02x\n", | |
170 | hose->first_busno,hose->last_busno); | |
171 | ||
56a92705 KG |
172 | /* |
173 | * Activate ULI1575 legacy chip by performing a fake | |
174 | * memory access. Needed to make ULI RTC work. | |
175 | */ | |
10795f42 | 176 | in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); |
837f1ba0 ES |
177 | } else { |
178 | printf (" PCIE3: disabled\n"); | |
179 | } | |
180 | ||
181 | } | |
182 | #else | |
183 | gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ | |
184 | #endif | |
185 | ||
186 | #ifdef CONFIG_PCIE1 | |
187 | { | |
6d0f6bcf | 188 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; |
837f1ba0 ES |
189 | struct pci_controller *hose = &pcie1_hose; |
190 | int pcie_ep = (host_agent == 5); | |
6d3a10f7 | 191 | int pcie_configured = io_sel >= 2; |
2dba0dea | 192 | struct pci_region *r = hose->regions; |
837f1ba0 ES |
193 | |
194 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ | |
195 | printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", | |
196 | pcie_ep ? "End Point" : "Root Complex", | |
197 | (uint)pci); | |
198 | if (pci->pme_msg_det) { | |
199 | pci->pme_msg_det = 0xffffffff; | |
200 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
201 | } | |
202 | printf ("\n"); | |
203 | ||
204 | /* inbound */ | |
2dba0dea | 205 | r += fsl_pci_setup_inbound_windows(r); |
837f1ba0 ES |
206 | |
207 | /* outbound memory */ | |
2dba0dea | 208 | pci_set_region(r++, |
10795f42 | 209 | CONFIG_SYS_PCIE1_MEM_BUS, |
6d0f6bcf JCPV |
210 | CONFIG_SYS_PCIE1_MEM_PHYS, |
211 | CONFIG_SYS_PCIE1_MEM_SIZE, | |
837f1ba0 ES |
212 | PCI_REGION_MEM); |
213 | ||
214 | /* outbound io */ | |
2dba0dea | 215 | pci_set_region(r++, |
6d0f6bcf JCPV |
216 | CONFIG_SYS_PCIE1_IO_BASE, |
217 | CONFIG_SYS_PCIE1_IO_PHYS, | |
218 | CONFIG_SYS_PCIE1_IO_SIZE, | |
837f1ba0 ES |
219 | PCI_REGION_IO); |
220 | ||
10795f42 | 221 | #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 |
837f1ba0 | 222 | /* outbound memory */ |
2dba0dea | 223 | pci_set_region(r++, |
10795f42 | 224 | CONFIG_SYS_PCIE1_MEM_BUS2, |
6d0f6bcf JCPV |
225 | CONFIG_SYS_PCIE1_MEM_PHYS2, |
226 | CONFIG_SYS_PCIE1_MEM_SIZE2, | |
837f1ba0 | 227 | PCI_REGION_MEM); |
837f1ba0 | 228 | #endif |
2dba0dea | 229 | hose->region_count = r - hose->regions; |
837f1ba0 ES |
230 | hose->first_busno=first_free_busno; |
231 | ||
232 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
233 | ||
234 | fsl_pci_init(hose); | |
235 | ||
236 | first_free_busno=hose->last_busno+1; | |
237 | printf(" PCIE1 on bus %02x - %02x\n", | |
238 | hose->first_busno,hose->last_busno); | |
239 | ||
240 | } else { | |
241 | printf (" PCIE1: disabled\n"); | |
242 | } | |
243 | ||
244 | } | |
245 | #else | |
246 | gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ | |
247 | #endif | |
248 | ||
249 | #ifdef CONFIG_PCIE2 | |
250 | { | |
6d0f6bcf | 251 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; |
837f1ba0 ES |
252 | struct pci_controller *hose = &pcie2_hose; |
253 | int pcie_ep = (host_agent == 3); | |
6d3a10f7 | 254 | int pcie_configured = io_sel >= 4; |
2dba0dea | 255 | struct pci_region *r = hose->regions; |
837f1ba0 ES |
256 | |
257 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ | |
258 | printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", | |
259 | pcie_ep ? "End Point" : "Root Complex", | |
260 | (uint)pci); | |
261 | if (pci->pme_msg_det) { | |
262 | pci->pme_msg_det = 0xffffffff; | |
263 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
264 | } | |
265 | printf ("\n"); | |
266 | ||
267 | /* inbound */ | |
2dba0dea | 268 | r += fsl_pci_setup_inbound_windows(r); |
837f1ba0 ES |
269 | |
270 | /* outbound memory */ | |
2dba0dea | 271 | pci_set_region(r++, |
10795f42 | 272 | CONFIG_SYS_PCIE2_MEM_BUS, |
6d0f6bcf JCPV |
273 | CONFIG_SYS_PCIE2_MEM_PHYS, |
274 | CONFIG_SYS_PCIE2_MEM_SIZE, | |
837f1ba0 ES |
275 | PCI_REGION_MEM); |
276 | ||
277 | /* outbound io */ | |
2dba0dea | 278 | pci_set_region(r++, |
6d0f6bcf JCPV |
279 | CONFIG_SYS_PCIE2_IO_BASE, |
280 | CONFIG_SYS_PCIE2_IO_PHYS, | |
281 | CONFIG_SYS_PCIE2_IO_SIZE, | |
837f1ba0 ES |
282 | PCI_REGION_IO); |
283 | ||
10795f42 | 284 | #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 |
837f1ba0 | 285 | /* outbound memory */ |
2dba0dea | 286 | pci_set_region(r++, |
10795f42 | 287 | CONFIG_SYS_PCIE2_MEM_BUS2, |
6d0f6bcf JCPV |
288 | CONFIG_SYS_PCIE2_MEM_PHYS2, |
289 | CONFIG_SYS_PCIE2_MEM_SIZE2, | |
837f1ba0 | 290 | PCI_REGION_MEM); |
837f1ba0 | 291 | #endif |
2dba0dea | 292 | hose->region_count = r - hose->regions; |
837f1ba0 ES |
293 | hose->first_busno=first_free_busno; |
294 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
295 | ||
296 | fsl_pci_init(hose); | |
297 | first_free_busno=hose->last_busno+1; | |
298 | printf (" PCIE2 on bus %02x - %02x\n", | |
299 | hose->first_busno,hose->last_busno); | |
300 | ||
301 | } else { | |
302 | printf (" PCIE2: disabled\n"); | |
303 | } | |
304 | ||
305 | } | |
306 | #else | |
307 | gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ | |
308 | #endif | |
309 | ||
310 | ||
311 | #ifdef CONFIG_PCI1 | |
312 | { | |
6d0f6bcf | 313 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; |
837f1ba0 | 314 | struct pci_controller *hose = &pci1_hose; |
2dba0dea | 315 | struct pci_region *r = hose->regions; |
837f1ba0 ES |
316 | |
317 | uint pci_agent = (host_agent == 6); | |
318 | uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ | |
319 | uint pci_32 = 1; | |
320 | uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ | |
321 | uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ | |
322 | ||
323 | ||
324 | if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { | |
325 | printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", | |
326 | (pci_32) ? 32 : 64, | |
327 | (pci_speed == 33333000) ? "33" : | |
328 | (pci_speed == 66666000) ? "66" : "unknown", | |
329 | pci_clk_sel ? "sync" : "async", | |
330 | pci_agent ? "agent" : "host", | |
331 | pci_arb ? "arbiter" : "external-arbiter", | |
332 | (uint)pci | |
333 | ); | |
334 | ||
335 | /* inbound */ | |
2dba0dea | 336 | r += fsl_pci_setup_inbound_windows(r); |
837f1ba0 ES |
337 | |
338 | /* outbound memory */ | |
2dba0dea | 339 | pci_set_region(r++, |
10795f42 | 340 | CONFIG_SYS_PCI1_MEM_BUS, |
6d0f6bcf JCPV |
341 | CONFIG_SYS_PCI1_MEM_PHYS, |
342 | CONFIG_SYS_PCI1_MEM_SIZE, | |
837f1ba0 ES |
343 | PCI_REGION_MEM); |
344 | ||
345 | /* outbound io */ | |
2dba0dea | 346 | pci_set_region(r++, |
6d0f6bcf JCPV |
347 | CONFIG_SYS_PCI1_IO_BASE, |
348 | CONFIG_SYS_PCI1_IO_PHYS, | |
349 | CONFIG_SYS_PCI1_IO_SIZE, | |
837f1ba0 | 350 | PCI_REGION_IO); |
2dba0dea | 351 | |
10795f42 | 352 | #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 |
837f1ba0 | 353 | /* outbound memory */ |
2dba0dea | 354 | pci_set_region(r++, |
10795f42 | 355 | CONFIG_SYS_PCIE3_MEM_BUS2, |
6d0f6bcf JCPV |
356 | CONFIG_SYS_PCIE3_MEM_PHYS2, |
357 | CONFIG_SYS_PCIE3_MEM_SIZE2, | |
837f1ba0 | 358 | PCI_REGION_MEM); |
837f1ba0 | 359 | #endif |
2dba0dea | 360 | hose->region_count = r - hose->regions; |
837f1ba0 ES |
361 | hose->first_busno=first_free_busno; |
362 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
363 | ||
364 | fsl_pci_init(hose); | |
365 | first_free_busno=hose->last_busno+1; | |
366 | printf ("PCI on bus %02x - %02x\n", | |
367 | hose->first_busno,hose->last_busno); | |
368 | } else { | |
369 | printf (" PCI: disabled\n"); | |
370 | } | |
371 | } | |
372 | #else | |
373 | gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ | |
374 | #endif | |
375 | } | |
376 | ||
377 | ||
25d83d7f JL |
378 | int last_stage_init(void) |
379 | { | |
380 | return 0; | |
381 | } | |
382 | ||
383 | ||
384 | unsigned long | |
385 | get_board_sys_clk(ulong dummy) | |
386 | { | |
387 | u8 i, go_bit, rd_clks; | |
388 | ulong val = 0; | |
389 | ||
390 | go_bit = in8(PIXIS_BASE + PIXIS_VCTL); | |
391 | go_bit &= 0x01; | |
392 | ||
393 | rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); | |
394 | rd_clks &= 0x1C; | |
395 | ||
396 | /* | |
397 | * Only if both go bit and the SCLK bit in VCFGEN0 are set | |
398 | * should we be using the AUX register. Remember, we also set the | |
399 | * GO bit to boot from the alternate bank on the on-board flash | |
400 | */ | |
401 | ||
402 | if (go_bit) { | |
403 | if (rd_clks == 0x1c) | |
404 | i = in8(PIXIS_BASE + PIXIS_AUX); | |
405 | else | |
406 | i = in8(PIXIS_BASE + PIXIS_SPD); | |
407 | } else { | |
408 | i = in8(PIXIS_BASE + PIXIS_SPD); | |
409 | } | |
410 | ||
411 | i &= 0x07; | |
412 | ||
413 | switch (i) { | |
414 | case 0: | |
415 | val = 33333333; | |
416 | break; | |
417 | case 1: | |
418 | val = 40000000; | |
419 | break; | |
420 | case 2: | |
421 | val = 50000000; | |
422 | break; | |
423 | case 3: | |
424 | val = 66666666; | |
425 | break; | |
426 | case 4: | |
427 | val = 83000000; | |
428 | break; | |
429 | case 5: | |
430 | val = 100000000; | |
431 | break; | |
432 | case 6: | |
433 | val = 133333333; | |
434 | break; | |
435 | case 7: | |
436 | val = 166666666; | |
437 | break; | |
438 | } | |
439 | ||
440 | return val; | |
441 | } | |
442 | ||
216f2a71 AF |
443 | int board_eth_init(bd_t *bis) |
444 | { | |
0b252f50 | 445 | #ifdef CONFIG_TSEC_ENET |
216f2a71 | 446 | struct tsec_info_struct tsec_info[2]; |
6d0f6bcf | 447 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
216f2a71 AF |
448 | uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
449 | int num = 0; | |
450 | ||
451 | #ifdef CONFIG_TSEC1 | |
452 | SET_STD_TSEC_INFO(tsec_info[num], 1); | |
453 | if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) | |
454 | tsec_info[num].flags |= TSEC_SGMII; | |
455 | num++; | |
456 | #endif | |
457 | #ifdef CONFIG_TSEC3 | |
458 | SET_STD_TSEC_INFO(tsec_info[num], 3); | |
459 | if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) | |
460 | tsec_info[num].flags |= TSEC_SGMII; | |
461 | num++; | |
462 | #endif | |
463 | ||
464 | if (!num) { | |
465 | printf("No TSECs initialized\n"); | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | if (io_sel & 1) | |
471 | fsl_sgmii_riser_init(tsec_info, num); | |
472 | ||
473 | ||
474 | tsec_eth_init(bis, tsec_info, num); | |
216f2a71 | 475 | #endif |
0b252f50 BW |
476 | return pci_eth_init(bis); |
477 | } | |
216f2a71 | 478 | |
addce57e | 479 | #if defined(CONFIG_OF_BOARD_SETUP) |
2dba0dea | 480 | extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, |
3cbd8231 | 481 | struct pci_controller *hose); |
addce57e | 482 | |
2dba0dea | 483 | void ft_board_setup(void *blob, bd_t *bd) |
25d83d7f | 484 | { |
2f15278c | 485 | ft_cpu_setup(blob, bd); |
25d83d7f | 486 | |
2dba0dea | 487 | |
f75e89e9 | 488 | #ifdef CONFIG_PCI1 |
2dba0dea | 489 | ft_fsl_pci_setup(blob, "pci0", &pci1_hose); |
837f1ba0 ES |
490 | #endif |
491 | #ifdef CONFIG_PCIE2 | |
2dba0dea | 492 | ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); |
addce57e KG |
493 | #endif |
494 | #ifdef CONFIG_PCIE1 | |
2dba0dea | 495 | ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); |
837f1ba0 ES |
496 | #endif |
497 | #ifdef CONFIG_PCIE3 | |
2dba0dea | 498 | ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); |
837f1ba0 | 499 | #endif |
25d83d7f JL |
500 | } |
501 | #endif |