[people/ms/u-boot.git] / board / freescale / mpc8544ds / mpc8544ds.c

/*
 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>

#include "../common/sgmii_riser.h"

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	if (vboot & PIXIS_VBOOT_FMAP)
		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	else
		puts ("Promjet\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info;
	u32 devdisr, pordevsr, io_sel;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno = 0;

	int pcie_ep, pcie_configured;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);
	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);

	puts("\n");

#ifdef CONFIG_PCIE3
	pcie_configured = is_serdes_configured(PCIE3);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
		/* contains both PCIE3 MEM & IO space */
		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
				LAW_TRGT_IF_PCIE_3);
		SET_STD_PCIE_INFO(pci_info, 3);
		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);

		/* outbound memory */
		pci_set_region(&pcie3_hose.regions[0],
			       CONFIG_SYS_PCIE3_MEM_BUS2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie3_hose.region_count = 1;

		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info.regs);
		first_free_busno = fsl_pci_init_port(&pci_info,
					&pcie3_hose, first_free_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
	} else {
		printf("PCIE3: disabled\n");
	}
	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif

#ifdef CONFIG_PCIE1
	SET_STD_PCIE_INFO(pci_info, 1);
	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
#else
	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
#endif

#ifdef CONFIG_PCIE2
	SET_STD_PCIE_INFO(pci_info, 2);
	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
#else
	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
#endif

#ifdef CONFIG_PCI1
	pci_speed = 66666000;
	pci_32 = 1;
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info.regs);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}

int last_stage_init(void)
{
	return 0;
}


unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	go_bit = in_8(pixis_base + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in_8(pixis_base + PIXIS_AUX);
		else
			i = in_8(pixis_base + PIXIS_SPD);
	} else {
		i = in_8(pixis_base + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}


#define MIIM_CIS8204_SLED_CON		0x1b
#define MIIM_CIS8204_SLEDCON_INIT	0x1115
/*
 * Hack to write all 4 PHYs with the LED values
 */
int board_phy_config(struct phy_device *phydev)
{
	static int do_once;
	uint phyid;
	struct mii_dev *bus = phydev->bus;

	if (phydev->drv->config)
		phydev->drv->config(phydev);
	if (do_once)
		return 0;

	for (phyid = 0; phyid < 4; phyid++)
		bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
				MIIM_CIS8204_SLEDCON_INIT);

	do_once = 1;

	return 0;
}


int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[2];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (is_serdes_configured(SGMII_TSEC1)) {
		puts("eTSEC1 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (is_serdes_configured(SGMII_TSEC3)) {
		puts("eTSEC3 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

	if (is_serdes_configured(SGMII_TSEC1) ||
	    is_serdes_configured(SGMII_TSEC3)) {
		fsl_sgmii_riser_init(tsec_info, num);
	}

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;
	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif
Commit	Line	Data
25d83d7f	1	/*
6525d51f	2	* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
25d83d7f	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
25d83d7f JL	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
837f1ba0	9	#include <pci.h>
25d83d7f	10	#include <asm/processor.h>
1167a2fd	11	#include <asm/mmu.h>
25d83d7f	12	#include <asm/immap_85xx.h>
c8514622	13	#include <asm/fsl_pci.h>
1167a2fd	14	#include <asm/fsl_ddr_sdram.h>
5d27e02c	15	#include <asm/fsl_serdes.h>
56a92705	16	#include <asm/io.h>
25d83d7f	17	#include <miiphy.h>
addce57e KG	18	#include <libfdt.h>
addce57e KG	19	#include <fdt_support.h>
063c1263	20	#include <fsl_mdio.h>
216f2a71	21	#include <tsec.h>
0b252f50	22	#include <netdev.h>
25d83d7f	23
216f2a71	24	#include "../common/sgmii_riser.h"
25d83d7f	25
25d83d7f JL	26	int checkboard (void)
25d83d7f JL	27	{
6d0f6bcf	28	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	29	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	30	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6bb5b412 KG	31	u8 vboot;
6bb5b412 KG	32	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	33
2f15278c	34	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	35	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
25d83d7f	36	}
6bb5b412 KG	37	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
	38	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	39	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	40	in_8(pixis_base + PIXIS_PVER));
	41
	42	vboot = in_8(pixis_base + PIXIS_VBOOT);
	43	if (vboot & PIXIS_VBOOT_FMAP)
	44	printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	45	else
	46	puts ("Promjet\n");
25d83d7f	47
837f1ba0 ES	48	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	49	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	50	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	51	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	52
25d83d7f JL	53	return 0;
	54	}
	55
837f1ba0 ES	56	#ifdef CONFIG_PCI1
	57	static struct pci_controller pci1_hose;
	58	#endif
	59
837f1ba0 ES	60	#ifdef CONFIG_PCIE3
	61	static struct pci_controller pcie3_hose;
	62	#endif
	63
645d5a78	64	void pci_init_board(void)
837f1ba0	65	{
6d0f6bcf	66	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
64a1686a	67	struct fsl_pci_info pci_info;
645d5a78 KG	68	u32 devdisr, pordevsr, io_sel;
	69	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	70	int first_free_busno = 0;
645d5a78 KG	71
645d5a78 KG	72	int pcie_ep, pcie_configured;
837f1ba0	73
645d5a78 KG	74	devdisr = in_be32(&gur->devdisr);
	75	pordevsr = in_be32(&gur->pordevsr);
	76	porpllsr = in_be32(&gur->porpllsr);
	77	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	78
	79	debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
837f1ba0	80
645d5a78	81	puts("\n");
837f1ba0 ES	82
837f1ba0 ES	83	#ifdef CONFIG_PCIE3
5d27e02c	84	pcie_configured = is_serdes_configured(PCIE3);
837f1ba0	85
645d5a78	86	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
64a1686a KG	87	/* contains both PCIE3 MEM & IO space */
	88	set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
	89	LAW_TRGT_IF_PCIE_3);
	90	SET_STD_PCIE_INFO(pci_info, 3);
	91	pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
	92
837f1ba0	93	/* outbound memory */
645d5a78	94	pci_set_region(&pcie3_hose.regions[0],
10795f42	95	CONFIG_SYS_PCIE3_MEM_BUS2,
6d0f6bcf JCPV	96	CONFIG_SYS_PCIE3_MEM_PHYS2,
6d0f6bcf JCPV	97	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	98	PCI_REGION_MEM);
837f1ba0	99
645d5a78	100	pcie3_hose.region_count = 1;
64a1686a	101
8ca78f2c PT	102	printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
8ca78f2c PT	103	pcie_ep ? "Endpoint" : "Root Complex",
64a1686a KG	104	pci_info.regs);
64a1686a KG	105	first_free_busno = fsl_pci_init_port(&pci_info,
645d5a78	106	&pcie3_hose, first_free_busno);
837f1ba0	107
56a92705 KG	108	/*
	109	* Activate ULI1575 legacy chip by performing a fake
	110	* memory access. Needed to make ULI RTC work.
	111	*/
10795f42	112	in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
837f1ba0	113	} else {
8ca78f2c	114	printf("PCIE3: disabled\n");
837f1ba0	115	}
645d5a78	116	puts("\n");
837f1ba0	117	#else
645d5a78	118	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
837f1ba0 ES	119	#endif
	120
	121	#ifdef CONFIG_PCIE1
64a1686a KG	122	SET_STD_PCIE_INFO(pci_info, 1);
64a1686a KG	123	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
837f1ba0	124	#else
64a1686a	125	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
837f1ba0 ES	126	#endif
	127
	128	#ifdef CONFIG_PCIE2
64a1686a KG	129	SET_STD_PCIE_INFO(pci_info, 2);
64a1686a KG	130	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
837f1ba0	131	#else
64a1686a	132	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
837f1ba0 ES	133	#endif
837f1ba0 ES	134
837f1ba0	135	#ifdef CONFIG_PCI1
645d5a78 KG	136	pci_speed = 66666000;
	137	pci_32 = 1;
	138	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	139	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
837f1ba0 ES	140
837f1ba0 ES	141	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
64a1686a KG	142	SET_STD_PCI_INFO(pci_info, 1);
	143	set_next_law(pci_info.mem_phys,
	144	law_size_bits(pci_info.mem_size), pci_info.law);
	145	set_next_law(pci_info.io_phys,
	146	law_size_bits(pci_info.io_size), pci_info.law);
	147
	148	pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
8ca78f2c	149	printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
837f1ba0 ES	150	(pci_32) ? 32 : 64,
	151	(pci_speed == 33333000) ? "33" :
	152	(pci_speed == 66666000) ? "66" : "unknown",
	153	pci_clk_sel ? "sync" : "async",
	154	pci_agent ? "agent" : "host",
	155	pci_arb ? "arbiter" : "external-arbiter",
64a1686a	156	pci_info.regs);
837f1ba0	157
64a1686a	158	first_free_busno = fsl_pci_init_port(&pci_info,
645d5a78	159	&pci1_hose, first_free_busno);
837f1ba0	160	} else {
8ca78f2c	161	printf("PCI: disabled\n");
837f1ba0	162	}
645d5a78 KG	163
645d5a78 KG	164	puts("\n");
837f1ba0	165	#else
645d5a78	166	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
837f1ba0 ES	167	#endif
	168	}
	169
25d83d7f JL	170	int last_stage_init(void)
	171	{
	172	return 0;
	173	}
	174
	175
	176	unsigned long
	177	get_board_sys_clk(ulong dummy)
	178	{
	179	u8 i, go_bit, rd_clks;
	180	ulong val = 0;
048e7efe	181	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	182
048e7efe	183	go_bit = in_8(pixis_base + PIXIS_VCTL);
25d83d7f JL	184	go_bit &= 0x01;
25d83d7f JL	185
048e7efe	186	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
25d83d7f JL	187	rd_clks &= 0x1C;
	188
	189	/*
	190	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	191	* should we be using the AUX register. Remember, we also set the
	192	* GO bit to boot from the alternate bank on the on-board flash
	193	*/
	194
	195	if (go_bit) {
	196	if (rd_clks == 0x1c)
048e7efe	197	i = in_8(pixis_base + PIXIS_AUX);
25d83d7f	198	else
048e7efe	199	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f	200	} else {
048e7efe	201	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f JL	202	}
	203
	204	i &= 0x07;
	205
	206	switch (i) {
	207	case 0:
	208	val = 33333333;
	209	break;
	210	case 1:
	211	val = 40000000;
	212	break;
	213	case 2:
	214	val = 50000000;
	215	break;
	216	case 3:
	217	val = 66666666;
	218	break;
	219	case 4:
	220	val = 83000000;
	221	break;
	222	case 5:
	223	val = 100000000;
	224	break;
	225	case 6:
	226	val = 133333333;
	227	break;
	228	case 7:
	229	val = 166666666;
	230	break;
	231	}
	232
	233	return val;
	234	}
	235
063c1263 AF	236
	237	#define MIIM_CIS8204_SLED_CON 0x1b
	238	#define MIIM_CIS8204_SLEDCON_INIT 0x1115
	239	/*
	240	* Hack to write all 4 PHYs with the LED values
	241	*/
	242	int board_phy_config(struct phy_device *phydev)
	243	{
	244	static int do_once;
	245	uint phyid;
	246	struct mii_dev *bus = phydev->bus;
	247
9fafe7da TK	248	if (phydev->drv->config)
9fafe7da TK	249	phydev->drv->config(phydev);
063c1263 AF	250	if (do_once)
	251	return 0;
	252
	253	for (phyid = 0; phyid < 4; phyid++)
	254	bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
	255	MIIM_CIS8204_SLEDCON_INIT);
	256
	257	do_once = 1;
	258
	259	return 0;
	260	}
	261
	262
216f2a71 AF	263	int board_eth_init(bd_t *bis)
216f2a71 AF	264	{
0b252f50	265	#ifdef CONFIG_TSEC_ENET
063c1263	266	struct fsl_pq_mdio_info mdio_info;
216f2a71	267	struct tsec_info_struct tsec_info[2];
216f2a71 AF	268	int num = 0;
	269
	270	#ifdef CONFIG_TSEC1
	271	SET_STD_TSEC_INFO(tsec_info[num], 1);
058d7dc7 KG	272	if (is_serdes_configured(SGMII_TSEC1)) {
058d7dc7 KG	273	puts("eTSEC1 is in sgmii mode.\n");
216f2a71	274	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	275	}
216f2a71 AF	276	num++;
	277	#endif
	278	#ifdef CONFIG_TSEC3
	279	SET_STD_TSEC_INFO(tsec_info[num], 3);
058d7dc7 KG	280	if (is_serdes_configured(SGMII_TSEC3)) {
058d7dc7 KG	281	puts("eTSEC3 is in sgmii mode.\n");
216f2a71	282	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	283	}
216f2a71 AF	284	num++;
	285	#endif
	286
	287	if (!num) {
	288	printf("No TSECs initialized\n");
	289
	290	return 0;
	291	}
	292
058d7dc7 KG	293	if (is_serdes_configured(SGMII_TSEC1) \|\|
058d7dc7 KG	294	is_serdes_configured(SGMII_TSEC3)) {
216f2a71	295	fsl_sgmii_riser_init(tsec_info, num);
058d7dc7	296	}
216f2a71	297
063c1263 AF	298	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	299	mdio_info.name = DEFAULT_MII_NAME;
	300	fsl_pq_mdio_init(bis, &mdio_info);
216f2a71 AF	301
216f2a71 AF	302	tsec_eth_init(bis, tsec_info, num);
216f2a71	303	#endif
0b252f50 BW	304	return pci_eth_init(bis);
0b252f50 BW	305	}
216f2a71	306
addce57e	307	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	308	void ft_board_setup(void blob, bd_t bd)
25d83d7f	309	{
2f15278c	310	ft_cpu_setup(blob, bd);
25d83d7f	311
6525d51f	312	FT_FSL_PCI_SETUP;
2dba0dea	313
feede8b0 AF	314	#ifdef CONFIG_FSL_SGMII_RISER
	315	fsl_sgmii_riser_fdt_fixup(blob);
	316	#endif
25d83d7f JL	317	}
25d83d7f JL	318	#endif