[people/ms/u-boot.git] / board / freescale / mpc8548cds / tlb.c

/*
 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),

	/* TLB 1 */
	/*
	 * Entry 0:
	 * FLASH(cover boot page)	16M	Non-cacheable, guarded
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 0, BOOKE_PAGESZ_16M, 1),

	/*
	 * Entry 1:
	 * CCSRBAR	1M	Non-cacheable, guarded
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_1M, 1),

	/*
	 * Entry 2:
	 * LBC SDRAM	64M	Cacheable, non-guarded
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
		      CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
		      0, 2, BOOKE_PAGESZ_64M, 1),

	/*
	 * Entry 3:
	 * CADMUS registers	1M	Non-cacheable, guarded
	 */
	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_1M, 1),

	/*
	 * Entry 4:
	 * PCI and PCIe MEM	1G	Non-cacheable, guarded
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 4, BOOKE_PAGESZ_1G, 1),

	/*
	 * Entry 5:
	 * PCI1 IO	1M	Non-cacheable, guarded
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 5, BOOKE_PAGESZ_1M, 1),

	/*
	 * Entry 6:
	 * PCIe IO	1M	Non-cacheable, guarded
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 6, BOOKE_PAGESZ_1M, 1),
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
0db37dc2	1	/*
8b47d7ec	2	* Copyright 2008, 2011 Freescale Semiconductor, Inc.
0db37dc2 KG	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
0db37dc2 KG	8	*/
	9
	10	#include <common.h>
	11	#include <asm/mmu.h>
	12
	13	struct fsl_e_tlb_entry tlb_table[] = {
	14	/* TLB 0 - for temp stack in cache */
6d0f6bcf	15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
0db37dc2 KG	16	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
0db37dc2 KG	17	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	18	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
0db37dc2 KG	19	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
0db37dc2 KG	20	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	21	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
0db37dc2 KG	22	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
0db37dc2 KG	23	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	24	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
0db37dc2 KG	25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	26	0, 0, BOOKE_PAGESZ_4K, 0),
	27
fff80975	28	/* TLB 1 */
0db37dc2	29	/*
fff80975	30	* Entry 0:
fff80975	31	* FLASH(cover boot page) 16M Non-cacheable, guarded
0db37dc2	32	*/
fff80975	33	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
0db37dc2 KG	34	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	35	0, 0, BOOKE_PAGESZ_16M, 1),
	36
	37	/*
fff80975	38	* Entry 1:
fff80975	39	* CCSRBAR 1M Non-cacheable, guarded
0db37dc2	40	*/
fff80975	41	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
0db37dc2	42	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
fff80975	43	0, 1, BOOKE_PAGESZ_1M, 1),
0db37dc2	44
0db37dc2	45	/*
fff80975	46	* Entry 2:
fff80975	47	* LBC SDRAM 64M Cacheable, non-guarded
0db37dc2	48	*/
fff80975	49	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
fff80975	50	CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
316f0d0f	51	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_M,
fff80975	52	0, 2, BOOKE_PAGESZ_64M, 1),
0db37dc2 KG	53
0db37dc2 KG	54	/*
fff80975	55	* Entry 3:
fff80975	56	* CADMUS registers 1M Non-cacheable, guarded
0db37dc2	57	*/
fff80975	58	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
0db37dc2	59	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
fff80975	60	0, 3, BOOKE_PAGESZ_1M, 1),
8b47d7ec	61
0db37dc2	62	/*
fff80975	63	* Entry 4:
fff80975	64	* PCI and PCIe MEM 1G Non-cacheable, guarded
0db37dc2	65	*/
fff80975	66	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
0db37dc2	67	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
fff80975	68	0, 4, BOOKE_PAGESZ_1G, 1),
0db37dc2 KG	69
0db37dc2 KG	70	/*
fff80975	71	* Entry 5:
fff80975	72	* PCI1 IO 1M Non-cacheable, guarded
0db37dc2	73	*/
fff80975	74	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
	75	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	76	0, 5, BOOKE_PAGESZ_1M, 1),
0db37dc2 KG	77
0db37dc2 KG	78	/*
fff80975	79	* Entry 6:
fff80975	80	* PCIe IO 1M Non-cacheable, guarded
0db37dc2	81	*/
fff80975	82	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
	83	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	84	0, 6, BOOKE_PAGESZ_1M, 1),
0db37dc2 KG	85	};
	86
	87	int num_tlb_entries = ARRAY_SIZE(tlb_table);