[people/ms/u-boot.git] / board / freescale / mpc8560ads / mpc8560ads.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2003,Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif


void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);


/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
    },

    /* Port B configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*            conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*            conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};


/*
 * MPC8560ADS Board Status & Control Registers
 */
typedef struct bcsr_ {
	volatile unsigned char bcsr0;
	volatile unsigned char bcsr1;
	volatile unsigned char bcsr2;
	volatile unsigned char bcsr3;
	volatile unsigned char bcsr4;
	volatile unsigned char bcsr5;
} bcsr_t;

void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
#endif
	/* reset Giga bit Ethernet port if needed here */

	/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
	bcsr->bcsr2 &= ~FETH2_RST;
	udelay(2);
	bcsr->bcsr2 |=  FETH2_RST;
	udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
	bcsr->bcsr3 &= ~FETH3_RST;
	udelay(2);
	bcsr->bcsr3 |=  FETH3_RST;
	udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
	/* reset PHY */
	miiphy_reset("FCC1 ETHERNET", 0x0);

	/* change PHY address to 0x02 */
	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);

	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}


int checkboard (void)
{
	puts("Board: ADS\n");

#ifdef CONFIG_PCI
	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#else
	printf("    PCI1: disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init();

	return 0;
}


phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	    uint temp_ddrdll = 0;

	    /*
	     * Work around to stabilize DDR DLL
	     */
	    temp_ddrdll = gur->ddrdllcr;
	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	    asm("sync;isync;msync");
	}
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	/*
	 * Initialize SDRAM.
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}


/*
 * Initialize Local Bus
 */

void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	clkdiv = lbc->lcrr & 0x0f;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */

	} else if (lbc_hz >= 133) {
		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
}


/*
 * Initialize SDRAM memory on the Local Bus.
 */

void
sdram_init(void)
{
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;

	puts("    SDRAM: ");
	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	lbc->or2 = CFG_OR2_PRELIM;
	lbc->br2 = CFG_BR2_PRELIM;
	lbc->lbcr = CFG_LBC_LBCR;
	asm("msync");

	lbc->lsrt = CFG_LBC_LSRT;
	lbc->mrtpr = CFG_LBC_MRTPR;
	asm("sync");

	/*
	 * Configure the SDRAM controller.
	 */
	lbc->lsdmr = CFG_LBC_LSDMR_1;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_2;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_3;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_5;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
  #ifndef CFG_RAMBOOT
	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	ddr->sdram_mode = CFG_DDR_MODE;
	ddr->sdram_interval = CFG_DDR_INTERVAL;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CFG_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
  #endif
	return CFG_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
      PCI_IDSEL_NUMBER, PCI_ANY_ID,
      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				   PCI_ENET0_MEMADDR,
				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
      } },
    { }
};
#endif


static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_mpc85xxads_config_table,
#endif
};

#endif	/* CONFIG_PCI */


void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}


#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = hose.last_busno - hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif
Commit	Line	Data
42d1f039	1	/*
97d80fc3	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2003,Motorola Inc.
	4	* Xianghua Xiao, (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27
42d1f039	28	#include <common.h>
9aea9530	29	#include <pci.h>
42d1f039 WD	30	#include <asm/processor.h>
	31	#include <asm/immap_85xx.h>
	32	#include <ioports.h>
a30a549a	33	#include <spd_sdram.h>
42d1f039	34	#include <miiphy.h>
5ce71580 KG	35	#include <libfdt.h>
5ce71580 KG	36	#include <fdt_support.h>
f5012827	37
d9b94f28	38	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
0ac6f8b7 WD	39	extern void ddr_enable_ecc(unsigned int dram_size);
	40	#endif
	41
0ac6f8b7	42
9aea9530	43	void local_bus_init(void);
0ac6f8b7 WD	44	void sdram_init(void);
	45	long int fixed_sdram(void);
	46
42d1f039 WD	47
	48	/*
	49	* I/O Port configuration table
	50	*
	51	* if conf is 1, then that port pin will be configured at boot time
	52	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	53	*/
	54
	55	const iop_conf_t iop_conf_tab[4][32] = {
	56
	57	/* Port A configuration */
	58	{ /* conf ppar psor pdir podr pdat */
	59	/* PA31 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxENB */
	60	/* PA30 / { 0, 1, 0, 0, 0, 0 }, / FCC1 TxClav */
	61	/* PA29 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxSOC */
	62	/* PA28 / { 0, 1, 0, 1, 0, 0 }, / FCC1 RxENB */
	63	/* PA27 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxSOC */
	64	/* PA26 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxClav */
	65	/* PA25 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[0] */
	66	/* PA24 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[1] */
	67	/* PA23 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[2] */
	68	/* PA22 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[3] */
	69	/* PA21 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[4] */
	70	/* PA20 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[5] */
	71	/* PA19 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[6] */
	72	/* PA18 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[7] */
	73	/* PA17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[7] */
	74	/* PA16 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[6] */
	75	/* PA15 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[5] */
	76	/* PA14 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[4] */
	77	/* PA13 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[3] */
	78	/* PA12 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[2] */
	79	/* PA11 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[1] */
	80	/* PA10 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[0] */
	81	/* PA9 / { 0, 1, 1, 1, 0, 0 }, / FCC1 L1TXD */
	82	/* PA8 / { 0, 1, 1, 0, 0, 0 }, / FCC1 L1RXD */
	83	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
	84	/* PA6 / { 0, 1, 1, 1, 0, 0 }, / TDM A1 L1RSYNC */
	85	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
	86	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
	87	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
	88	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
	89	/* PA1 / { 1, 0, 0, 0, 0, 0 }, / FREERUN */
	90	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
	91	},
	92
	93	/* Port B configuration */
	94	{ /* conf ppar psor pdir podr pdat */
	95	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	96	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	97	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	98	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	99	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	100	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	101	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	102	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	103	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	104	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	105	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	106	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	107	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	108	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
	109	/* PB17 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
	110	/* PB16 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
111	/* PB15 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
112	/* PB14 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
113	/* PB13 / { 0, 1, 0, 0, 0, 0 }, / FCC3:COL */
114	/* PB12 / { 0, 1, 0, 0, 0, 0 }, / FCC3:CRS */
115	/* PB11 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
116	/* PB10 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
117	/* PB9 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
118	/* PB8 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
119	/* PB7 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
120	/* PB6 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
121	/* PB5 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
122	/* PB4 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
123	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
124	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
125	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
126	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
127	},
128
129	/* Port C */
130	{ /* conf ppar psor pdir podr pdat */
131	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
132	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
133	/* PC29 / { 0, 1, 1, 0, 0, 0 }, / SCC1 EN CLSN /
134	/* PC28 / { 0, 0, 0, 1, 0, 0 }, / PC28 */
135	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / UART Clock in */
136	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
137	/* PC25 / { 0, 0, 0, 1, 0, 0 }, / PC25 */
138	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
139	/* PC23 / { 0, 1, 0, 1, 0, 0 }, / ATMTFCLK */
140	/* PC22 / { 0, 1, 0, 0, 0, 0 }, / ATMRFCLK */
141	/* PC21 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
142	/* PC20 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
143	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK CLK13 */
144	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK14) */
145	/* PC17 / { 0, 0, 0, 1, 0, 0 }, / PC17 */
146	/* PC16 / { 0, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK16) */
147	/* PC15 / { 1, 1, 0, 0, 0, 0 }, / PC15 */
148	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
149	/* PC13 / { 0, 0, 0, 1, 0, 0 }, / PC13 */
150	/* PC12 / { 0, 1, 0, 1, 0, 0 }, / PC12 */
151	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / LXT971 transmit control */
152	/* PC10 / { 1, 0, 0, 1, 0, 0 }, / FETHMDC */
153	/* PC9 / { 1, 0, 0, 0, 0, 0 }, / FETHMDIO */
154	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
155	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
156	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
157	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
158	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
159	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
160	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
161	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
162	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
163	},
164
165	/* Port D */
166	{ /* conf ppar psor pdir podr pdat */
167	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
168	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
169	/* PD29 / { 1, 1, 0, 1, 0, 0 }, / SCC1 EN TENA */
170	/* PD28 / { 0, 1, 0, 0, 0, 0 }, / PD28 */
171	/* PD27 / { 0, 1, 1, 1, 0, 0 }, / PD27 */
172	/* PD26 / { 0, 0, 0, 1, 0, 0 }, / PD26 */
173	/* PD25 / { 0, 0, 0, 1, 0, 0 }, / PD25 */
174	/* PD24 / { 0, 0, 0, 1, 0, 0 }, / PD24 */
175	/* PD23 / { 0, 0, 0, 1, 0, 0 }, / PD23 */
176	/* PD22 / { 0, 0, 0, 1, 0, 0 }, / PD22 */
177	/* PD21 / { 0, 0, 0, 1, 0, 0 }, / PD21 */
178	/* PD20 / { 0, 0, 0, 1, 0, 0 }, / PD20 */
179	/* PD19 / { 0, 0, 0, 1, 0, 0 }, / PD19 */
180	/* PD18 / { 0, 0, 0, 1, 0, 0 }, / PD18 */
181	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
182	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
183	/* PD15 / { 0, 1, 1, 0, 1, 0 }, / I2C SDA */
184	/* PD14 / { 0, 0, 0, 1, 0, 0 }, / LED */
185	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
186	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
187	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
188	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
189	/* PD9 / { 0, 1, 0, 1, 0, 0 }, / SMC1 TXD */
190	/* PD8 / { 0, 1, 0, 0, 0, 0 }, / SMC1 RXD */
191	/* PD7 / { 0, 0, 0, 1, 0, 1 }, / PD7 */
192	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
193	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
194	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
195	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
196	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
197	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
198	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
199	}
200	};
201
0ac6f8b7 WD	202
	203	/*
	204	* MPC8560ADS Board Status & Control Registers
	205	*/
	206	typedef struct bcsr_ {
42d1f039 WD	207	volatile unsigned char bcsr0;
	208	volatile unsigned char bcsr1;
	209	volatile unsigned char bcsr2;
	210	volatile unsigned char bcsr3;
	211	volatile unsigned char bcsr4;
	212	volatile unsigned char bcsr5;
	213	} bcsr_t;
	214
42d1f039 WD	215	void reset_phy (void)
	216	{
	217	#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
	218	volatile bcsr_t bcsr = (bcsr_t ) CFG_BCSR;
	219	#endif
	220	/* reset Giga bit Ethernet port if needed here */
	221
	222	/* reset the CPM FEC port */
	223	#if (CONFIG_ETHER_INDEX == 2)
	224	bcsr->bcsr2 &= ~FETH2_RST;
	225	udelay(2);
	226	bcsr->bcsr2 \|= FETH2_RST;
	227	udelay(1000);
	228	#elif (CONFIG_ETHER_INDEX == 3)
	229	bcsr->bcsr3 &= ~FETH3_RST;
	230	udelay(2);
	231	bcsr->bcsr3 \|= FETH3_RST;
	232	udelay(1000);
	233	#endif
	234	#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
63ff004c MB	235	/* reset PHY */
	236	miiphy_reset("FCC1 ETHERNET", 0x0);
	237
	238	/* change PHY address to 0x02 */
	239	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
	240
	241	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
	242	PHY_BMCR_AUTON \| PHY_BMCR_RST_NEG);
42d1f039 WD	243	#endif /* CONFIG_MII */
	244	}
	245
9aea9530	246
42d1f039 WD	247	int checkboard (void)
42d1f039 WD	248	{
97d80fc3	249	puts("Board: ADS\n");
0ac6f8b7 WD	250
	251	#ifdef CONFIG_PCI
	252	printf(" PCI1: 32 bit, %d MHz (compiled)\n",
	253	CONFIG_SYS_CLK_FREQ / 1000000);
	254	#else
	255	printf(" PCI1: disabled\n");
	256	#endif
9aea9530 WD	257
	258	/*
	259	* Initialize local bus.
	260	*/
	261	local_bus_init();
	262
97d80fc3	263	return 0;
42d1f039 WD	264	}
	265
	266
9973e3c6	267	phys_size_t
0ac6f8b7	268	initdram(int board_type)
42d1f039 WD	269	{
42d1f039 WD	270	long dram_size = 0;
97d80fc3	271
0ac6f8b7	272	puts("Initializing\n");
42d1f039	273
0ac6f8b7 WD	274	#if defined(CONFIG_DDR_DLL)
0ac6f8b7 WD	275	{
f59b55a5	276	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
9aea9530 WD	277	uint temp_ddrdll = 0;
	278
	279	/*
	280	* Work around to stabilize DDR DLL
	281	*/
	282	temp_ddrdll = gur->ddrdllcr;
	283	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) \| 0x80000000;
	284	asm("sync;isync;msync");
0ac6f8b7	285	}
42d1f039 WD	286	#endif
	287
	288	#if defined(CONFIG_SPD_EEPROM)
	289	dram_size = spd_sdram ();
	290	#else
	291	dram_size = fixed_sdram ();
	292	#endif
	293
d9b94f28	294	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
0ac6f8b7 WD	295	/*
	296	* Initialize and enable DDR ECC.
	297	*/
	298	ddr_enable_ecc(dram_size);
	299	#endif
	300
	301	/*
	302	* Initialize SDRAM.
	303	*/
	304	sdram_init();
	305
	306	puts(" DDR: ");
	307	return dram_size;
	308	}
	309
	310
	311	/*
9aea9530	312	* Initialize Local Bus
0ac6f8b7 WD	313	*/
0ac6f8b7 WD	314
9aea9530 WD	315	void
9aea9530 WD	316	local_bus_init(void)
0ac6f8b7	317	{
f59b55a5	318	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
04db4008	319	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
0ac6f8b7	320
9aea9530 WD	321	uint clkdiv;
	322	uint lbc_hz;
	323	sys_info_t sysinfo;
0ac6f8b7 WD	324
0ac6f8b7 WD	325	/*
9aea9530 WD	326	* Errata LBC11.
9aea9530 WD	327	* Fix Local Bus clock glitch when DLL is enabled.
0ac6f8b7	328	*
9aea9530 WD	329	* If localbus freq is < 66Mhz, DLL bypass mode must be used.
	330	* If localbus freq is > 133Mhz, DLL can be safely enabled.
	331	* Between 66 and 133, the DLL is enabled with an override workaround.
0ac6f8b7	332	*/
9aea9530 WD	333
	334	get_sys_info(&sysinfo);
	335	clkdiv = lbc->lcrr & 0x0f;
	336	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	337
	338	if (lbc_hz < 66) {
	339	lbc->lcrr = CFG_LBC_LCRR \| 0x80000000; /* DLL Bypass */
	340
	341	} else if (lbc_hz >= 133) {
	342	lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
0ac6f8b7	343
42d1f039	344	} else {
0ac6f8b7 WD	345	/*
	346	* On REV1 boards, need to change CLKDIV before enable DLL.
	347	* Default CLKDIV is 8, change it to 4 temporarily.
	348	*/
9aea9530	349	uint pvr = get_pvr();
0ac6f8b7	350	uint temp_lbcdll = 0;
97d80fc3 WD	351
97d80fc3 WD	352	if (pvr == PVR_85xx_REV1) {
9aea9530	353	/* FIXME: Justify the high bit here. */
0ac6f8b7	354	lbc->lcrr = 0x10000004;
97d80fc3	355	}
0ac6f8b7	356
9aea9530 WD	357	lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
	358	udelay(200);
	359
	360	/*
	361	* Sample LBC DLL ctrl reg, upshift it to set the
	362	* override bits.
	363	*/
42d1f039	364	temp_lbcdll = gur->lbcdllcr;
9aea9530 WD	365	gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) \| 0x80000000);
9aea9530 WD	366	asm("sync;isync;msync");
42d1f039	367	}
9aea9530 WD	368	}
	369
	370
	371	/*
	372	* Initialize SDRAM memory on the Local Bus.
	373	*/
	374
	375	void
	376	sdram_init(void)
	377	{
04db4008	378	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
9aea9530 WD	379	uint sdram_addr = (uint )CFG_LBC_SDRAM_BASE;
	380
	381	puts(" SDRAM: ");
	382	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
0ac6f8b7 WD	383
	384	/*
	385	* Setup SDRAM Base and Option Registers
	386	*/
	387	lbc->or2 = CFG_OR2_PRELIM;
42d1f039 WD	388	lbc->br2 = CFG_BR2_PRELIM;
42d1f039 WD	389	lbc->lbcr = CFG_LBC_LBCR;
9aea9530	390	asm("msync");
0ac6f8b7 WD	391
	392	lbc->lsrt = CFG_LBC_LSRT;
	393	lbc->mrtpr = CFG_LBC_MRTPR;
9aea9530	394	asm("sync");
0ac6f8b7 WD	395
	396	/*
	397	* Configure the SDRAM controller.
	398	*/
42d1f039	399	lbc->lsdmr = CFG_LBC_LSDMR_1;
9aea9530	400	asm("sync");
0ac6f8b7	401	*sdram_addr = 0xff;
9aea9530 WD	402	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	403	udelay(100);
0ac6f8b7	404
42d1f039	405	lbc->lsdmr = CFG_LBC_LSDMR_2;
9aea9530	406	asm("sync");
0ac6f8b7	407	*sdram_addr = 0xff;
9aea9530 WD	408	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	409	udelay(100);
0ac6f8b7	410
42d1f039	411	lbc->lsdmr = CFG_LBC_LSDMR_3;
9aea9530	412	asm("sync");
0ac6f8b7	413	*sdram_addr = 0xff;
9aea9530 WD	414	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	415	udelay(100);
42d1f039	416
0ac6f8b7	417	lbc->lsdmr = CFG_LBC_LSDMR_4;
9aea9530	418	asm("sync");
0ac6f8b7	419	*sdram_addr = 0xff;
9aea9530 WD	420	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	421	udelay(100);
42d1f039	422
0ac6f8b7	423	lbc->lsdmr = CFG_LBC_LSDMR_5;
9aea9530	424	asm("sync");
0ac6f8b7	425	*sdram_addr = 0xff;
9aea9530 WD	426	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	427	udelay(100);
42d1f039 WD	428	}
42d1f039 WD	429
42d1f039 WD	430	#if !defined(CONFIG_SPD_EEPROM)
	431	/*************************************************************************
	432	* fixed sdram init -- doesn't use serial presence detect.
	433	************************************************************************/
	434	long int fixed_sdram (void)
	435	{
	436	#ifndef CFG_RAMBOOT
04db4008	437	volatile ccsr_ddr_t ddr= (void )(CFG_MPC85xx_DDR_ADDR);
42d1f039 WD	438
	439	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	440	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
	441	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	442	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	443	ddr->sdram_mode = CFG_DDR_MODE;
	444	ddr->sdram_interval = CFG_DDR_INTERVAL;
	445	#if defined (CONFIG_DDR_ECC)
	446	ddr->err_disable = 0x0000000D;
	447	ddr->err_sbe = 0x00ff0000;
	448	#endif
	449	asm("sync;isync;msync");
	450	udelay(500);
	451	#if defined (CONFIG_DDR_ECC)
	452	/* Enable ECC checking */
	453	ddr->sdram_cfg = (CFG_DDR_CONTROL \| 0x20000000);
	454	#else
	455	ddr->sdram_cfg = CFG_DDR_CONTROL;
	456	#endif
	457	asm("sync; isync; msync");
	458	udelay(500);
	459	#endif
0ac6f8b7	460	return CFG_SDRAM_SIZE * 1024 * 1024;
42d1f039 WD	461	}
42d1f039 WD	462	#endif /* !defined(CONFIG_SPD_EEPROM) */
9aea9530 WD	463
	464
	465	#if defined(CONFIG_PCI)
	466	/*
	467	* Initialize PCI Devices, report devices found.
	468	*/
	469
	470	#ifndef CONFIG_PCI_PNP
	471	static struct pci_config_table pci_mpc85xxads_config_table[] = {
	472	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	473	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	474	pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
	475	PCI_ENET0_MEMADDR,
	476	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER
	477	} },
	478	{ }
	479	};
	480	#endif
	481
	482
	483	static struct pci_controller hose = {
	484	#ifndef CONFIG_PCI_PNP
	485	config_table: pci_mpc85xxads_config_table,
	486	#endif
	487	};
	488
	489	#endif /* CONFIG_PCI */
	490
	491
	492	void
	493	pci_init_board(void)
	494	{
	495	#ifdef CONFIG_PCI
9aea9530 WD	496	pci_mpc85xx_init(&hose);
	497	#endif /* CONFIG_PCI */
	498	}
0e16387d MM	499
0e16387d MM	500
5ce71580	501	#if defined(CONFIG_OF_BOARD_SETUP)
0e16387d MM	502	void
	503	ft_board_setup(void blob, bd_t bd)
	504	{
5ce71580 KG	505	int node, tmp[2];
	506	const char *path;
	507
0e16387d	508	ft_cpu_setup(blob, bd);
5ce71580 KG	509
	510	node = fdt_path_offset(blob, "/aliases");
	511	tmp[0] = 0;
	512	if (node >= 0) {
	513	#ifdef CONFIG_PCI
	514	path = fdt_getprop(blob, node, "pci0", NULL);
	515	if (path) {
	516	tmp[1] = hose.last_busno - hose.first_busno;
	517	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	518	}
	519	#endif
	520	}
0e16387d MM	521	}
0e16387d MM	522	#endif