[people/ms/u-boot.git] / board / freescale / mpc8569mds / mpc8569mds.c

/*
 * Copyright 2009-2010 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <hwconfig.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>

#include "bcsr.h"
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* QE_MUX_MDC */
	{2,  31, 1, 0, 1}, /* QE_MUX_MDC               */

	/* QE_MUX_MDIO */
	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */

#if defined(CONFIG_SYS_UCC_RGMII_MODE)
	/* UCC_1_RGMII */
	{2, 11, 2, 0, 1}, /* CLK12 */
	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
	{0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
	{0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
	{0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
	{0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
	{2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */

	/* UCC_2_RGMII */
	{2, 16, 2, 0, 3}, /* CLK17 */
	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */

	/* UCC_3_RGMII */
	{2, 11, 2, 0, 1}, /* CLK12 */
	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */

	/* UCC_4_RGMII */
	{2, 16, 2, 0, 3}, /* CLK17 */
	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */

#elif defined(CONFIG_SYS_UCC_RMII_MODE)
	/* UCC_1_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */

	/* UCC_2_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */

	/* UCC_3_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */

	/* UCC_4_RMII */
	{2, 15, 2, 0, 1}, /* CLK16 */
	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
#endif

	/* UART1 is muxed with QE PortF bit [9-12].*/
	{5, 12, 2, 0, 3}, /* UART1_SIN */
	{5, 9,  1, 0, 3}, /* UART1_SOUT */
	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
	{5, 11, 1, 0, 2}, /* UART1_RTS_B */

	/* QE UART                                     */
	{0, 19, 1, 0, 2}, /* QEUART_TX                 */
	{1, 17, 2, 0, 3}, /* QEUART_RX                 */
	{0, 25, 1, 0, 1}, /* QEUART_RTS                */
	{1, 23, 2, 0, 1}, /* QEUART_CTS                */

	/* QE USB                                      */
	{5,  3, 1, 0, 1}, /* USB_OE                    */
	{5,  4, 1, 0, 2}, /* USB_TP                    */
	{5,  5, 1, 0, 2}, /* USB_TN                    */
	{5,  6, 2, 0, 2}, /* USB_RP                    */
	{5,  7, 2, 0, 1}, /* USB_RX                    */
	{5,  8, 2, 0, 1}, /* USB_RN                    */
	{2,  4, 2, 0, 2}, /* CLK5                      */

	/* SPI Flash, M25P40                           */
	{4, 27, 3, 0, 1}, /* SPI_MOSI                  */
	{4, 28, 3, 0, 1}, /* SPI_MISO                  */
	{4, 29, 3, 0, 1}, /* SPI_CLK                   */
	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */

	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
};

void local_bus_init(void);

int board_early_init_f (void)
{
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	enable_8569mds_flash_write();

#ifdef CONFIG_QE
	enable_8569mds_qe_uec();
#endif

#if CONFIG_SYS_I2C2_OFFSET
	/* Enable I2C2 signals instead of SD signals */
	volatile struct ccsr_gur *gur;
	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
	gur->plppar1 |= PLPPAR1_I2C2_VAL;
	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
	gur->plpdir1 |= PLPDIR1_I2C2_VAL;

	disable_8569mds_brd_eeprom_write_protect();
#endif

	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
	const u8 flash_esel = 0;

	/*
	 * Remap Boot flash to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,	/* tlb, epn, rpn */
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
		0, flash_esel,				/* ts, esel */
		BOOKE_PAGESZ_64M, 1);			/* tsize, iprot */

	return 0;
}

int checkboard (void)
{
	printf ("Board: 8569 MDS\n");

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
	uint d_init;

	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
#if defined (CONFIG_DDR_ECC)
	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
#endif
	udelay(500);

	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
		udelay(1000);
	}
	debug("DDR: memory initialized\n\n");
	udelay(500);
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	if (clkdiv == 16)
		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	else if (clkdiv == 8)
		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	else if (clkdiv == 4)
		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);

	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
}

static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
{
	const char *status = "disabled";
	int off;
	int err;

	off = fdt_path_offset(blob, alias);
	if (off < 0) {
		printf("WARNING: could not find %s alias: %s.\n", alias,
			fdt_strerror(off));
		return;
	}

	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
	if (err) {
		printf("WARNING: could not set status for serial0: %s.\n",
			fdt_strerror(err));
		return;
	}
}

/*
 * Because of an erratum in prototype boards it is impossible to use eSDHC
 * without disabling UART0 (which makes it quite easy to 'brick' the board
 * by simply issung 'setenv hwconfig esdhc', and not able to interact with
 * U-Boot anylonger).
 *
 * So, but default we assume that the board is a prototype, which is a most
 * safe assumption. There is no way to determine board revision from a
 * register, so we use hwconfig.
 */

static int prototype_board(void)
{
	if (hwconfig_subarg("board", "rev", NULL))
		return hwconfig_subarg_cmp("board", "rev", "prototype");
	return 1;
}

static int esdhc_disables_uart0(void)
{
	return prototype_board() ||
	       hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
}

static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
{
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
	const char *devtype = "serial";
	const char *compat = "ucc_uart";
	const char *clk = "brg9";
	u32 portnum = 0;
	int off = -1;

	if (!hwconfig("qe_uart"))
		return;

	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
		printf("QE UART: won't enable with esdhc.\n");
		return;
	}

	fdt_board_disable_serial(blob, bd, "serial1");

	while (1) {
		const u32 *idx;
		int len;

		off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
		if (off < 0) {
			printf("WARNING: unable to fixup device tree for "
				"QE UART\n");
			return;
		}

		idx = fdt_getprop(blob, off, "cell-index", &len);
		if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
			continue;
		break;
	}

	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));

	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
}

#ifdef CONFIG_FSL_ESDHC

int board_mmc_init(bd_t *bd)
{
	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
	u8 bcsr6 = BCSR6_SD_CARD_1BIT;

	if (!hwconfig("esdhc"))
		return 0;

	printf("Enabling eSDHC...\n"
	       "  For eSDHC to function, I2C2 ");
	if (esdhc_disables_uart0()) {
		printf("and UART0 should be disabled.\n");
		printf("  Redirecting stderr, stdout and stdin to UART1...\n");
		console_assign(stderr, "eserial1");
		console_assign(stdout, "eserial1");
		console_assign(stdin, "eserial1");
		printf("Switched to UART1 (initial log has been printed to "
		       "UART0).\n");

		clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
					       PLPPAR1_ESDHC_4BITS_VAL);
		clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
					       PLPDIR1_ESDHC_4BITS_VAL);
		bcsr6 |= BCSR6_SD_CARD_4BITS;
	} else {
		printf("should be disabled.\n");
	}

	/* Assign I2C2 signals to eSDHC. */
	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
				       PLPPAR1_ESDHC_VAL);
	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
				       PLPDIR1_ESDHC_VAL);

	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
	setbits_8(&bcsr[6], bcsr6);

	return fsl_esdhc_mmc_init(bd);
}

static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
{
	const char *status = "disabled";
	int off = -1;

	if (!hwconfig("esdhc"))
		return;

	if (esdhc_disables_uart0())
		fdt_board_disable_serial(blob, bd, "serial0");

	while (1) {
		const u32 *idx;
		int len;

		off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
		if (off < 0)
			break;

		idx = fdt_getprop(blob, off, "cell-index", &len);
		if (!idx || len != sizeof(*idx))
			continue;

		if (*idx == 1) {
			fdt_setprop(blob, off, "status", status,
				    strlen(status) + 1);
			break;
		}
	}

	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
		off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
		if (off < 0) {
			printf("WARNING: could not find esdhc node\n");
			return;
		}
		fdt_delprop(blob, off, "sdhci,1-bit-only");
	}
}
#else
static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
#endif

static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
{
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;

	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
		clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
	else
		setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);

	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
		clrbits_8(&bcsr[17], BCSR17_USBVCC);
		clrbits_8(&bcsr[17], BCSR17_USBMODE);
		do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
				   "peripheral", sizeof("peripheral"), 1);
	} else {
		setbits_8(&bcsr[17], BCSR17_USBVCC);
		setbits_8(&bcsr[17], BCSR17_USBMODE);
	}

	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
#if defined(CONFIG_PQ_MDS_PIB)
	pib_init();
#endif

	fsl_pcie_init_board(0);
}
#endif /* CONFIG_PCI */

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_SYS_UCC_RMII_MODE)
	int nodeoff, off, err;
	unsigned int val;
	const u32 *ph;
	const u32 *index;

	/* fixup device tree for supporting rmii mode */
	nodeoff = -1;
	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
				"ucc_geth")) >= 0) {
		err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
						"clk16");
		if (err < 0) {
			printf("WARNING: could not set tx-clock-name %s.\n",
				fdt_strerror(err));
			break;
		}

		err = fdt_fixup_phy_connection(blob, nodeoff, RMII);

		if (err < 0) {
			printf("WARNING: could not set phy-connection-type "
				"%s.\n", fdt_strerror(err));
			break;
		}

		index = fdt_getprop(blob, nodeoff, "cell-index", 0);
		if (index == NULL) {
			printf("WARNING: could not get cell-index of ucc\n");
			break;
		}

		ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
		if (ph == NULL) {
			printf("WARNING: could not get phy-handle of ucc\n");
			break;
		}

		off = fdt_node_offset_by_phandle(blob, *ph);
		if (off < 0) {
			printf("WARNING: could not get phy node	%s.\n",
				fdt_strerror(err));
			break;
		}

		val = 0x7 + *index; /* RMII phy address starts from 0x8 */

		err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
		if (err < 0) {
			printf("WARNING: could not set reg for phy-handle "
				"%s.\n", fdt_strerror(err));
			break;
		}
	}
#endif
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

	fdt_board_fixup_esdhc(blob, bd);
	fdt_board_fixup_qe_uart(blob, bd);
	fdt_board_fixup_qe_usb(blob, bd);
}
#endif
Commit	Line	Data
765547dc	1	/*
6525d51f	2	* Copyright 2009-2010 Freescale Semiconductor.
765547dc HW	3	*
	4	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
7f52ed5e	26	#include <hwconfig.h>
765547dc HW	27	#include <pci.h>
	28	#include <asm/processor.h>
	29	#include <asm/mmu.h>
3aed5507	30	#include <asm/cache.h>
765547dc	31	#include <asm/immap_85xx.h>
c8514622	32	#include <asm/fsl_pci.h>
765547dc	33	#include <asm/fsl_ddr_sdram.h>
5d27e02c	34	#include <asm/fsl_serdes.h>
765547dc HW	35	#include <asm/io.h>
	36	#include <spd_sdram.h>
	37	#include <i2c.h>
	38	#include <ioports.h>
	39	#include <libfdt.h>
	40	#include <fdt_support.h>
7f52ed5e	41	#include <fsl_esdhc.h>
765547dc HW	42
765547dc HW	43	#include "bcsr.h"
d9180382 LY	44	#if defined(CONFIG_PQ_MDS_PIB)
	45	#include "../common/pq-mds-pib.h"
	46	#endif
765547dc	47
765547dc HW	48	const qe_iop_conf_t qe_iop_conf_tab[] = {
	49	/* QE_MUX_MDC */
	50	{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
	51
	52	/* QE_MUX_MDIO */
	53	{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
	54
f82107f6	55	#if defined(CONFIG_SYS_UCC_RGMII_MODE)
765547dc HW	56	/* UCC_1_RGMII */
	57	{2, 11, 2, 0, 1}, /* CLK12 */
	58	{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
	59	{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
	60	{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
	61	{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
	62	{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
	63	{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
	64	{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
	65	{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
	66	{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
	67	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
	68	{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
	69	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
	70
	71	/* UCC_2_RGMII */
	72	{2, 16, 2, 0, 3}, /* CLK17 */
	73	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
	74	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
	75	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
	76	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
	77	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
	78	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
	79	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
	80	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
	81	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
	82	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
	83	{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
	84	{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
	85
750098d3 HW	86	/* UCC_3_RGMII */
	87	{2, 11, 2, 0, 1}, /* CLK12 */
	88	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
	89	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
	90	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
	91	{1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
	92	{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
	93	{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
	94	{1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
	95	{1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
	96	{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
	97	{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
	98	{2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
	99	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
	100
	101	/* UCC_4_RGMII */
	102	{2, 16, 2, 0, 3}, /* CLK17 */
	103	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
	104	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
	105	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
	106	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
	107	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
	108	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
	109	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
	110	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
	111	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
	112	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
	113	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
	114	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
	115
f82107f6 HW	116	#elif defined(CONFIG_SYS_UCC_RMII_MODE)
	117	/* UCC_1_RMII */
	118	{2, 15, 2, 0, 1}, /* CLK16 */
	119	{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
	120	{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
	121	{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
	122	{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
	123	{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
	124	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
	125
	126	/* UCC_2_RMII */
	127	{2, 15, 2, 0, 1}, /* CLK16 */
	128	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
	129	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
	130	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
	131	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
	132	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
	133	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
	134
	135	/* UCC_3_RMII */
	136	{2, 15, 2, 0, 1}, /* CLK16 */
	137	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
	138	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
	139	{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
	140	{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
	141	{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
	142	{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
	143
	144	/* UCC_4_RMII */
	145	{2, 15, 2, 0, 1}, /* CLK16 */
	146	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
	147	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
	148	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
	149	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
	150	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
	151	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
	152	#endif
	153
b2aab386 HW	154	/* UART1 is muxed with QE PortF bit [9-12].*/
	155	{5, 12, 2, 0, 3}, /* UART1_SIN */
	156	{5, 9, 1, 0, 3}, /* UART1_SOUT */
	157	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
	158	{5, 11, 1, 0, 2}, /* UART1_RTS_B */
	159
14809b6c AV	160	/* QE UART */
	161	{0, 19, 1, 0, 2}, /* QEUART_TX */
	162	{1, 17, 2, 0, 3}, /* QEUART_RX */
	163	{0, 25, 1, 0, 1}, /* QEUART_RTS */
	164	{1, 23, 2, 0, 1}, /* QEUART_CTS */
	165
3fca8037 AV	166	/* QE USB */
	167	{5, 3, 1, 0, 1}, /* USB_OE */
	168	{5, 4, 1, 0, 2}, /* USB_TP */
	169	{5, 5, 1, 0, 2}, /* USB_TN */
	170	{5, 6, 2, 0, 2}, /* USB_RP */
	171	{5, 7, 2, 0, 1}, /* USB_RX */
	172	{5, 8, 2, 0, 1}, /* USB_RN */
	173	{2, 4, 2, 0, 2}, /* CLK5 */
	174
70d665b1 AV	175	/* SPI Flash, M25P40 */
	176	{4, 27, 3, 0, 1}, /* SPI_MOSI */
	177	{4, 28, 3, 0, 1}, /* SPI_MISO */
	178	{4, 29, 3, 0, 1}, /* SPI_CLK */
	179	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
	180
765547dc HW	181	{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
	182	};
	183
	184	void local_bus_init(void);
	185
	186	int board_early_init_f (void)
	187	{
	188	/*
	189	* Initialize local bus.
	190	*/
	191	local_bus_init ();
	192
	193	enable_8569mds_flash_write();
	194
	195	#ifdef CONFIG_QE
f82107f6	196	enable_8569mds_qe_uec();
765547dc HW	197	#endif
	198
	199	#if CONFIG_SYS_I2C2_OFFSET
	200	/* Enable I2C2 signals instead of SD signals */
	201	volatile struct ccsr_gur *gur;
	202	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
	203	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
	204	gur->plppar1 \|= PLPPAR1_I2C2_VAL;
	205	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
	206	gur->plpdir1 \|= PLPDIR1_I2C2_VAL;
	207
	208	disable_8569mds_brd_eeprom_write_protect();
	209	#endif
	210
	211	return 0;
	212	}
	213
3aed5507 HW	214	int board_early_init_r(void)
	215	{
	216	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
	217	const u8 flash_esel = 0;
	218
	219	/*
	220	* Remap Boot flash to caching-inhibited
	221	* so that flash can be erased properly.
	222	*/
	223
	224	/* Flush d-cache and invalidate i-cache of any FLASH data */
	225	flush_dcache();
	226	invalidate_icache();
	227
	228	/* invalidate existing TLB entry for flash */
	229	disable_tlb(flash_esel);
	230
	231	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
	232	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G, /* perms, wimge */
	233	0, flash_esel, /* ts, esel */
	234	BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
	235
	236	return 0;
	237	}
	238
765547dc HW	239	int checkboard (void)
	240	{
	241	printf ("Board: 8569 MDS\n");
	242
	243	return 0;
	244	}
	245
765547dc HW	246	#if !defined(CONFIG_SPD_EEPROM)
	247	phys_size_t fixed_sdram(void)
	248	{
	249	volatile ccsr_ddr_t ddr = (ccsr_ddr_t )CONFIG_SYS_MPC85xx_DDR_ADDR;
	250	uint d_init;
	251
	252	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
	253	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
	254	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
	255	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
	256	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
	257	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
	258	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
	259	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
	260	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
	261	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
	262	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
	263	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
	264	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
	265	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
	266	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
	267	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
	268	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
	269	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
	270	#if defined (CONFIG_DDR_ECC)
	271	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
	272	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
	273	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
	274	#endif
	275	udelay(500);
	276
	277	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
	278	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	279	d_init = 1;
	280	debug("DDR - 1st controller: memory initializing\n");
	281	/*
	282	* Poll until memory is initialized.
	283	* 512 Meg at 400 might hit this 200 times or so.
	284	*/
	285	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
	286	udelay(1000);
	287	}
	288	debug("DDR: memory initialized\n\n");
	289	udelay(500);
	290	#endif
	291	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	292	}
	293	#endif
	294
	295	/*
	296	* Initialize Local Bus
	297	*/
	298	void
	299	local_bus_init(void)
	300	{
	301	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	302	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
765547dc HW	303
	304	uint clkdiv;
	305	uint lbc_hz;
	306	sys_info_t sysinfo;
	307
	308	get_sys_info(&sysinfo);
	309	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
	310	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	311
	312	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	313	if (clkdiv == 16)
	314	out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	315	else if (clkdiv == 8)
	316	out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	317	else if (clkdiv == 4)
	318	out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
	319
	320	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)\| 0x00030000);
	321	}
	322
14809b6c AV	323	static void fdt_board_disable_serial(void blob, bd_t bd, const char *alias)
	324	{
	325	const char *status = "disabled";
	326	int off;
	327	int err;
	328
	329	off = fdt_path_offset(blob, alias);
	330	if (off < 0) {
	331	printf("WARNING: could not find %s alias: %s.\n", alias,
	332	fdt_strerror(off));
	333	return;
	334	}
	335
	336	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
	337	if (err) {
	338	printf("WARNING: could not set status for serial0: %s.\n",
	339	fdt_strerror(err));
	340	return;
	341	}
	342	}
7f52ed5e AV	343
	344	/*
	345	* Because of an erratum in prototype boards it is impossible to use eSDHC
	346	* without disabling UART0 (which makes it quite easy to 'brick' the board
	347	* by simply issung 'setenv hwconfig esdhc', and not able to interact with
	348	* U-Boot anylonger).
	349	*
	350	* So, but default we assume that the board is a prototype, which is a most
	351	* safe assumption. There is no way to determine board revision from a
	352	* register, so we use hwconfig.
	353	*/
	354
	355	static int prototype_board(void)
	356	{
	357	if (hwconfig_subarg("board", "rev", NULL))
	358	return hwconfig_subarg_cmp("board", "rev", "prototype");
	359	return 1;
	360	}
	361
	362	static int esdhc_disables_uart0(void)
	363	{
	364	return prototype_board() \|\|
	365	hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
	366	}
	367
14809b6c AV	368	static void fdt_board_fixup_qe_uart(void blob, bd_t bd)
	369	{
	370	u8 bcsr = (u8 )CONFIG_SYS_BCSR_BASE;
	371	const char *devtype = "serial";
	372	const char *compat = "ucc_uart";
	373	const char *clk = "brg9";
	374	u32 portnum = 0;
	375	int off = -1;
	376
	377	if (!hwconfig("qe_uart"))
	378	return;
	379
	380	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
	381	printf("QE UART: won't enable with esdhc.\n");
	382	return;
	383	}
	384
	385	fdt_board_disable_serial(blob, bd, "serial1");
	386
	387	while (1) {
	388	const u32 *idx;
	389	int len;
	390
	391	off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
	392	if (off < 0) {
	393	printf("WARNING: unable to fixup device tree for "
	394	"QE UART\n");
	395	return;
	396	}
	397
	398	idx = fdt_getprop(blob, off, "cell-index", &len);
	399	if (!idx \|\| len != sizeof(idx) \|\| idx != fdt32_to_cpu(2))
	400	continue;
	401	break;
	402	}
	403
	404	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
	405	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
	406	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
	407	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
	408	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
	409
	410	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
	411	}
	412
	413	#ifdef CONFIG_FSL_ESDHC
	414
7f52ed5e AV	415	int board_mmc_init(bd_t *bd)
	416	{
	417	struct ccsr_gur gur = (struct ccsr_gur )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	418	u8 bcsr = (u8 )CONFIG_SYS_BCSR_BASE;
	419	u8 bcsr6 = BCSR6_SD_CARD_1BIT;
	420
	421	if (!hwconfig("esdhc"))
	422	return 0;
	423
	424	printf("Enabling eSDHC...\n"
	425	" For eSDHC to function, I2C2 ");
	426	if (esdhc_disables_uart0()) {
	427	printf("and UART0 should be disabled.\n");
	428	printf(" Redirecting stderr, stdout and stdin to UART1...\n");
	429	console_assign(stderr, "eserial1");
	430	console_assign(stdout, "eserial1");
	431	console_assign(stdin, "eserial1");
	432	printf("Switched to UART1 (initial log has been printed to "
	433	"UART0).\n");
c4ca10f1 AV	434
	435	clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
	436	PLPPAR1_ESDHC_4BITS_VAL);
	437	clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
	438	PLPDIR1_ESDHC_4BITS_VAL);
7f52ed5e AV	439	bcsr6 \|= BCSR6_SD_CARD_4BITS;
	440	} else {
	441	printf("should be disabled.\n");
	442	}
	443
	444	/* Assign I2C2 signals to eSDHC. */
	445	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
	446	PLPPAR1_ESDHC_VAL);
	447	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
	448	PLPDIR1_ESDHC_VAL);
	449
	450	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
	451	setbits_8(&bcsr[6], bcsr6);
	452
	453	return fsl_esdhc_mmc_init(bd);
	454	}
	455
	456	static void fdt_board_fixup_esdhc(void blob, bd_t bd)
	457	{
	458	const char *status = "disabled";
14809b6c	459	int off = -1;
7f52ed5e AV	460
	461	if (!hwconfig("esdhc"))
	462	return;
	463
14809b6c AV	464	if (esdhc_disables_uart0())
14809b6c AV	465	fdt_board_disable_serial(blob, bd, "serial0");
7f52ed5e	466
7f52ed5e AV	467	while (1) {
	468	const u32 *idx;
	469	int len;
	470
	471	off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
	472	if (off < 0)
	473	break;
	474
	475	idx = fdt_getprop(blob, off, "cell-index", &len);
	476	if (!idx \|\| len != sizeof(*idx))
	477	continue;
	478
	479	if (*idx == 1) {
	480	fdt_setprop(blob, off, "status", status,
	481	strlen(status) + 1);
	482	break;
	483	}
	484	}
c4ca10f1 AV	485
	486	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
	487	off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
	488	if (off < 0) {
	489	printf("WARNING: could not find esdhc node\n");
	490	return;
	491	}
	492	fdt_delprop(blob, off, "sdhci,1-bit-only");
	493	}
7f52ed5e AV	494	}
	495	#else
	496	static inline void fdt_board_fixup_esdhc(void blob, bd_t bd) {}
	497	#endif
	498
3fca8037 AV	499	static void fdt_board_fixup_qe_usb(void blob, bd_t bd)
	500	{
	501	u8 bcsr = (u8 )CONFIG_SYS_BCSR_BASE;
	502
	503	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
	504	clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
	505	else
	506	setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
	507
	508	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
	509	clrbits_8(&bcsr[17], BCSR17_USBVCC);
	510	clrbits_8(&bcsr[17], BCSR17_USBMODE);
	511	do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
	512	"peripheral", sizeof("peripheral"), 1);
	513	} else {
	514	setbits_8(&bcsr[17], BCSR17_USBVCC);
	515	setbits_8(&bcsr[17], BCSR17_USBMODE);
	516	}
	517
	518	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
	519	}
	520
765547dc	521	#ifdef CONFIG_PCI
c847e98b	522	void pci_init_board(void)
765547dc	523	{
d9180382 LY	524	#if defined(CONFIG_PQ_MDS_PIB)
	525	pib_init();
	526	#endif
	527
94f2bc48	528	fsl_pcie_init_board(0);
765547dc HW	529	}
	530	#endif /* CONFIG_PCI */
	531
	532	#if defined(CONFIG_OF_BOARD_SETUP)
765547dc HW	533	void ft_board_setup(void blob, bd_t bd)
765547dc HW	534	{
f82107f6 HW	535	#if defined(CONFIG_SYS_UCC_RMII_MODE)
	536	int nodeoff, off, err;
	537	unsigned int val;
	538	const u32 *ph;
	539	const u32 *index;
	540
	541	/* fixup device tree for supporting rmii mode */
	542	nodeoff = -1;
	543	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
	544	"ucc_geth")) >= 0) {
	545	err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
	546	"clk16");
	547	if (err < 0) {
	548	printf("WARNING: could not set tx-clock-name %s.\n",
	549	fdt_strerror(err));
	550	break;
	551	}
	552
a1964ea5 KG	553	err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
a1964ea5 KG	554
f82107f6 HW	555	if (err < 0) {
	556	printf("WARNING: could not set phy-connection-type "
	557	"%s.\n", fdt_strerror(err));
	558	break;
	559	}
	560
	561	index = fdt_getprop(blob, nodeoff, "cell-index", 0);
	562	if (index == NULL) {
	563	printf("WARNING: could not get cell-index of ucc\n");
	564	break;
	565	}
	566
	567	ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
	568	if (ph == NULL) {
	569	printf("WARNING: could not get phy-handle of ucc\n");
	570	break;
	571	}
	572
	573	off = fdt_node_offset_by_phandle(blob, *ph);
	574	if (off < 0) {
	575	printf("WARNING: could not get phy node %s.\n",
	576	fdt_strerror(err));
	577	break;
	578	}
	579
	580	val = 0x7 + index; / RMII phy address starts from 0x8 */
	581
	582	err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
	583	if (err < 0) {
	584	printf("WARNING: could not set reg for phy-handle "
	585	"%s.\n", fdt_strerror(err));
	586	break;
	587	}
	588	}
	589	#endif
765547dc HW	590	ft_cpu_setup(blob, bd);
765547dc HW	591
6525d51f KG	592	FT_FSL_PCI_SETUP;
6525d51f KG	593
7f52ed5e	594	fdt_board_fixup_esdhc(blob, bd);
14809b6c	595	fdt_board_fixup_qe_uart(blob, bd);
3fca8037	596	fdt_board_fixup_qe_usb(blob, bd);
765547dc HW	597	}
765547dc HW	598	#endif