[people/ms/u-boot.git] / board / freescale / mpc8610hpcd / mpc8610hpcd.c

/*
 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <i2c.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <netdev.h>

void sdram_init(void);
phys_size_t fixed_sdram(void);
int mpc8610hpcd_diu_init(void);


/* called before any console output */
int board_early_init_f(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_gur_t *gur = &immap->im_gur;

	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */

	return 0;
}

int misc_init_r(void)
{
	u8 tmp_val, version;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	/*Do not use 8259PIC*/
	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);

	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
	version = in_8(pixis_base + PIXIS_PVER);
	if(version >= 0x07) {
		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
	}

	/* Using this for DIU init before the driver in linux takes over
	 *  Enable the TFP410 Encoder (I2C address 0x38)
	 */

	tmp_val = 0xBF;
	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);

	tmp_val = 0x10;
	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);

	return 0;
}

int checkboard(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	mcm->abcr |= 0x00010000; /* 0 */
	mcm->hpmr3 = 0x80000008; /* 4c */
	mcm->hpmr0 = 0;
	mcm->hpmr1 = 0;
	mcm->hpmr2 = 0;
	mcm->hpmr4 = 0;
	mcm->hpmr5 = 0;

	return 0;
}


phys_size_t
initdram(int board_type)
{
	phys_size_t dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram();
#endif

	setup_ddr_bat(dram_size);

	puts(" DDR: ");
	return dram_size;
}


#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
	uint d_init;

	ddr->cs0_bnds = 0x0000001f;
	ddr->cs0_config = 0x80010202;

	ddr->timing_cfg_3 = 0x00000000;
	ddr->timing_cfg_0 = 0x00260802;
	ddr->timing_cfg_1 = 0x3935d322;
	ddr->timing_cfg_2 = 0x14904cc8;
	ddr->sdram_mode = 0x00480432;
	ddr->sdram_mode_2 = 0x00000000;
	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
	ddr->sdram_data_init = 0xDEADBEEF;
	ddr->sdram_clk_cntl = 0x03800000;
	ddr->sdram_cfg_2 = 0x04400010;

#if defined(CONFIG_DDR_ECC)
	ddr->err_int_en = 0x0000000d;
	ddr->err_disable = 0x00000000;
	ddr->err_sbe = 0x00010000;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/


#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
		udelay(1000);

	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}

#endif

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_fsl86xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				 PCI_ENET0_MEMADDR,
				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
	{}
};
#endif


static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

void pci_init_board(void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	struct fsl_pci_info pci_info[3];
	u32 devdisr, pordevsr;
	int first_free_busno = 0;
	int num = 0;

	int pci_agent, pcie_ep, pcie_configured;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);

#ifdef CONFIG_PCIE1
	pcie_configured = is_serdes_configured(PCIE1);

	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
		SET_STD_PCIE_INFO(pci_info[num], 1);
		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
		printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie1_hose, first_free_busno);
	} else {
		printf("PCIE1: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
#endif

#ifdef CONFIG_PCIE2
	pcie_configured = is_serdes_configured(PCIE2);

	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
		SET_STD_PCIE_INFO(pci_info[num], 2);
		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
		printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info[num].regs);
		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie2_hose, first_free_busno);
	} else {
		printf("PCIE2: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
#endif

#ifdef CONFIG_PCI1
	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info[num], 1);
		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
		printf("PCI: connected to PCI slots as %s" \
			" (base address %lx)\n",
			pci_agent ? "Agent" : "Host",
			pci_info[num].regs);
		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
#endif
}

#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;
}
#endif

/*
 * get_board_sys_clk
 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 */

unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	i = in_8(pixis_base + PIXIS_SPD);
	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333000;
		break;
	case 1:
		val = 39999600;
		break;
	case 2:
		val = 49999500;
		break;
	case 3:
		val = 66666000;
		break;
	case 4:
		val = 83332500;
		break;
	case 5:
		val = 99999000;
		break;
	case 6:
		val = 133332000;
		break;
	case 7:
		val = 166665000;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}

void board_reset(void)
{
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	out_8(pixis_base + PIXIS_RST, 0);

	while (1)
		;
}
Commit	Line	Data
3dd2db53	1	/*
6525d51f	2	* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
3dd2db53 JL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
c9974ab0	22
3dd2db53 JL	23	#include <common.h>
	24	#include <command.h>
	25	#include <pci.h>
	26	#include <asm/processor.h>
	27	#include <asm/immap_86xx.h>
c8514622	28	#include <asm/fsl_pci.h>
39aa1a73	29	#include <asm/fsl_ddr_sdram.h>
5d27e02c	30	#include <asm/fsl_serdes.h>
c9974ab0	31	#include <i2c.h>
3dd2db53	32	#include <asm/io.h>
1df170f8 JL	33	#include <libfdt.h>
1df170f8 JL	34	#include <fdt_support.h>
a30a549a	35	#include <spd_sdram.h>
89973f8a	36	#include <netdev.h>
3dd2db53	37
3dd2db53	38	void sdram_init(void);
4c77de3f	39	phys_size_t fixed_sdram(void);
e69e520f	40	int mpc8610hpcd_diu_init(void);
c9974ab0	41
3dd2db53 JL	42
	43	/* called before any console output */
	44	int board_early_init_f(void)
	45	{
6d0f6bcf	46	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53 JL	47	volatile ccsr_gur_t *gur = &immap->im_gur;
3dd2db53 JL	48
a877880c YS	49	gur->gpiocr \|= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
	50
	51	return 0;
	52	}
	53
	54	int misc_init_r(void)
	55	{
	56	u8 tmp_val, version;
048e7efe	57	u8 pixis_base = (u8 )PIXIS_BASE;
a877880c YS	58
a877880c YS	59	/Do not use 8259PIC/
048e7efe KG	60	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
048e7efe KG	61	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val \| 0x80);
a877880c YS	62
a877880c YS	63	/For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt/
048e7efe	64	version = in_8(pixis_base + PIXIS_PVER);
a877880c	65	if(version >= 0x07) {
048e7efe KG	66	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
048e7efe KG	67	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
a877880c YS	68	}
	69
	70	/* Using this for DIU init before the driver in linux takes over
	71	* Enable the TFP410 Encoder (I2C address 0x38)
	72	*/
	73
	74	tmp_val = 0xBF;
	75	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	76	/* Verify if enabled */
	77	tmp_val = 0;
	78	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	79	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
	80
	81	tmp_val = 0x10;
	82	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	83	/* Verify if enabled */
	84	tmp_val = 0;
	85	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	86	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
	87
3dd2db53 JL	88	return 0;
	89	}
	90
	91	int checkboard(void)
	92	{
6d0f6bcf	93	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53	94	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
048e7efe	95	u8 pixis_base = (u8 )PIXIS_BASE;
3dd2db53	96
9b55a253 WD	97	printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
9b55a253 WD	98	"System Version: 0x%02x, FPGA Version: 0x%02x\n",
048e7efe KG	99	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
048e7efe KG	100	in_8(pixis_base + PIXIS_PVER));
3dd2db53 JL	101
	102	mcm->abcr \|= 0x00010000; /* 0 */
	103	mcm->hpmr3 = 0x80000008; /* 4c */
	104	mcm->hpmr0 = 0;
	105	mcm->hpmr1 = 0;
	106	mcm->hpmr2 = 0;
	107	mcm->hpmr4 = 0;
	108	mcm->hpmr5 = 0;
	109
	110	return 0;
	111	}
	112
	113
9973e3c6	114	phys_size_t
3dd2db53 JL	115	initdram(int board_type)
3dd2db53 JL	116	{
4c77de3f	117	phys_size_t dram_size = 0;
3dd2db53 JL	118
3dd2db53 JL	119	#if defined(CONFIG_SPD_EEPROM)
39aa1a73	120	dram_size = fsl_ddr_sdram();
3dd2db53 JL	121	#else
	122	dram_size = fixed_sdram();
	123	#endif
	124
9ff32d8c TT	125	setup_ddr_bat(dram_size);
9ff32d8c TT	126
3dd2db53 JL	127	puts(" DDR: ");
	128	return dram_size;
	129	}
	130
	131
3dd2db53 JL	132	#if !defined(CONFIG_SPD_EEPROM)
	133	/*
	134	* Fixed sdram init -- doesn't use serial presence detect.
	135	*/
	136
4c77de3f	137	phys_size_t fixed_sdram(void)
3dd2db53	138	{
6d0f6bcf JCPV	139	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf JCPV	140	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53 JL	141	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
	142	uint d_init;
	143
	144	ddr->cs0_bnds = 0x0000001f;
	145	ddr->cs0_config = 0x80010202;
	146
45239cf4	147	ddr->timing_cfg_3 = 0x00000000;
3dd2db53 JL	148	ddr->timing_cfg_0 = 0x00260802;
	149	ddr->timing_cfg_1 = 0x3935d322;
	150	ddr->timing_cfg_2 = 0x14904cc8;
e7ee23ec	151	ddr->sdram_mode = 0x00480432;
3dd2db53 JL	152	ddr->sdram_mode_2 = 0x00000000;
	153	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
	154	ddr->sdram_data_init = 0xDEADBEEF;
	155	ddr->sdram_clk_cntl = 0x03800000;
	156	ddr->sdram_cfg_2 = 0x04400010;
	157
	158	#if defined(CONFIG_DDR_ECC)
	159	ddr->err_int_en = 0x0000000d;
	160	ddr->err_disable = 0x00000000;
	161	ddr->err_sbe = 0x00010000;
	162	#endif
	163	asm("sync;isync");
	164
	165	udelay(500);
	166
e7ee23ec	167	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
3dd2db53 JL	168
	169
	170	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	171	d_init = 1;
	172	debug("DDR - 1st controller: memory initializing\n");
	173	/*
	174	* Poll until memory is initialized.
	175	* 512 Meg at 400 might hit this 200 times or so.
	176	*/
	177	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
	178	udelay(1000);
	179
	180	debug("DDR: memory initialized\n\n");
	181	asm("sync; isync");
	182	udelay(500);
	183	#endif
	184
	185	return 512 * 1024 * 1024;
	186	#endif
6d0f6bcf	187	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
3dd2db53 JL	188	}
	189
	190	#endif
	191
	192	#if defined(CONFIG_PCI)
	193	/*
	194	* Initialize PCI Devices, report devices found.
	195	*/
	196
	197	#ifndef CONFIG_PCI_PNP
	198	static struct pci_config_table pci_fsl86xxads_config_table[] = {
	199	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	200	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	201	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	202	PCI_ENET0_MEMADDR,
	203	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER} },
	204	{}
	205	};
	206	#endif
	207
	208
	209	static struct pci_controller pci1_hose = {
	210	#ifndef CONFIG_PCI_PNP
	211	config_table:pci_mpc86xxcts_config_table
	212	#endif
	213	};
	214	#endif /* CONFIG_PCI */
	215
	216	#ifdef CONFIG_PCIE1
	217	static struct pci_controller pcie1_hose;
	218	#endif
	219
	220	#ifdef CONFIG_PCIE2
	221	static struct pci_controller pcie2_hose;
	222	#endif
	223
3dd2db53 JL	224	void pci_init_board(void)
3dd2db53 JL	225	{
6d0f6bcf	226	volatile immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
3dd2db53	227	volatile ccsr_gur_t *gur = &immap->im_gur;
5e3d7050	228	struct fsl_pci_info pci_info[3];
5d27e02c	229	u32 devdisr, pordevsr;
5e3d7050 KG	230	int first_free_busno = 0;
	231	int num = 0;
	232
	233	int pci_agent, pcie_ep, pcie_configured;
	234
	235	devdisr = in_be32(&gur->devdisr);
	236	pordevsr = in_be32(&gur->pordevsr);
3dd2db53	237
3dd2db53	238	#ifdef CONFIG_PCIE1
5d27e02c	239	pcie_configured = is_serdes_configured(PCIE1);
5e3d7050 KG	240
	241	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
	242	SET_STD_PCIE_INFO(pci_info[num], 1);
	243	pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
8ca78f2c PT	244	printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
	245	pcie_ep ? "Endpoint" : "Root Complex",
	246	pci_info[num].regs);
5e3d7050 KG	247
	248	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	249	&pcie1_hose, first_free_busno);
	250	} else {
8ca78f2c	251	printf("PCIE1: disabled\n");
5e3d7050	252	}
3dd2db53	253
5e3d7050 KG	254	puts("\n");
	255	#else
	256	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
	257	#endif
3dd2db53 JL	258
3dd2db53 JL	259	#ifdef CONFIG_PCIE2
5d27e02c	260	pcie_configured = is_serdes_configured(PCIE2);
5e3d7050 KG	261
	262	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
	263	SET_STD_PCIE_INFO(pci_info[num], 2);
	264	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
8ca78f2c PT	265	printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
	266	pcie_ep ? "Endpoint" : "Root Complex",
	267	pci_info[num].regs);
5e3d7050 KG	268	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	269	&pcie2_hose, first_free_busno);
	270	} else {
8ca78f2c	271	printf("PCIE2: disabled\n");
5e3d7050	272	}
3dd2db53	273
5e3d7050 KG	274	puts("\n");
	275	#else
	276	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
	277	#endif
3dd2db53 JL	278
3dd2db53 JL	279	#ifdef CONFIG_PCI1
5e3d7050 KG	280	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
	281	SET_STD_PCI_INFO(pci_info[num], 1);
	282	pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
8ca78f2c	283	printf("PCI: connected to PCI slots as %s" \
5e3d7050	284	" (base address %lx)\n",
3dd2db53	285	pci_agent ? "Agent" : "Host",
5e3d7050 KG	286	pci_info[num].regs);
	287	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	288	&pci1_hose, first_free_busno);
	289	} else {
8ca78f2c	290	printf("PCI: disabled\n");
5e3d7050	291	}
3dd2db53	292
5e3d7050 KG	293	puts("\n");
	294	#else
	295	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
	296	#endif
3dd2db53 JL	297	}
3dd2db53 JL	298
1df170f8	299	#if defined(CONFIG_OF_BOARD_SETUP)
3dd2db53 JL	300	void
	301	ft_board_setup(void blob, bd_t bd)
	302	{
8439f05c	303	ft_cpu_setup(blob, bd);
1df170f8	304
6525d51f	305	FT_FSL_PCI_SETUP;
3dd2db53 JL	306	}
	307	#endif
	308
	309	/*
	310	* get_board_sys_clk
	311	* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
	312	*/
	313
	314	unsigned long
	315	get_board_sys_clk(ulong dummy)
	316	{
a877880c	317	u8 i;
3dd2db53	318	ulong val = 0;
048e7efe	319	u8 pixis_base = (u8 )PIXIS_BASE;
3dd2db53	320
048e7efe	321	i = in_8(pixis_base + PIXIS_SPD);
3dd2db53 JL	322	i &= 0x07;
	323
	324	switch (i) {
	325	case 0:
	326	val = 33333000;
	327	break;
	328	case 1:
	329	val = 39999600;
	330	break;
	331	case 2:
	332	val = 49999500;
	333	break;
	334	case 3:
	335	val = 66666000;
	336	break;
	337	case 4:
	338	val = 83332500;
	339	break;
	340	case 5:
	341	val = 99999000;
	342	break;
	343	case 6:
	344	val = 133332000;
	345	break;
	346	case 7:
	347	val = 166665000;
	348	break;
	349	}
	350
	351	return val;
	352	}
65d3d99c	353
65d3d99c BW	354	int board_eth_init(bd_t *bis)
65d3d99c BW	355	{
89973f8a	356	return pci_eth_init(bis);
65d3d99c	357	}
4ef630df PT	358
	359	void board_reset(void)
	360	{
048e7efe KG	361	u8 pixis_base = (u8 )PIXIS_BASE;
	362
	363	out_8(pixis_base + PIXIS_RST, 0);
4ef630df PT	364
	365	while (1)
	366	;
	367	}