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Commit | Line | Data |
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6a8e5692 | 1 | /* |
712cf7ab | 2 | * Copyright 2008,2011 Freescale Semiconductor, Inc. |
6a8e5692 | 3 | * |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
6a8e5692 KG |
5 | */ |
6 | ||
7 | #include <common.h> | |
6a8e5692 | 8 | |
5614e71b YS |
9 | #include <fsl_ddr_sdram.h> |
10 | #include <fsl_ddr_dimm_params.h> | |
6a8e5692 | 11 | |
712cf7ab | 12 | struct board_specific_parameters { |
3cbd8231 | 13 | u32 n_ranks; |
712cf7ab | 14 | u32 datarate_mhz_high; |
3cbd8231 WD |
15 | u32 clk_adjust; |
16 | u32 cpo; | |
17 | u32 write_data_delay; | |
712cf7ab | 18 | }; |
c21617fd | 19 | |
712cf7ab YS |
20 | /* |
21 | * This table contains all valid speeds we want to override with board | |
22 | * specific parameters. datarate_mhz_high values need to be in ascending order | |
23 | * for each n_ranks group. | |
24 | */ | |
25 | const struct board_specific_parameters dimm0[] = { | |
26 | /* | |
27 | * memory controller 0 | |
28 | * num| hi| clk| cpo|wrdata|2T | |
29 | * ranks| mhz|adjst| | delay| | |
30 | */ | |
31 | {4, 333, 7, 7, 3}, | |
32 | {4, 549, 7, 9, 3}, | |
33 | {4, 650, 7, 10, 4}, | |
34 | {2, 333, 7, 7, 3}, | |
35 | {2, 549, 7, 9, 3}, | |
36 | {2, 650, 7, 10, 4}, | |
37 | {1, 333, 7, 7, 3}, | |
38 | {1, 549, 7, 9, 3}, | |
39 | {1, 650, 7, 10, 4}, | |
40 | {} | |
41 | }; | |
c21617fd | 42 | |
712cf7ab YS |
43 | /* |
44 | * The two slots have slightly different timing. The center values are good | |
45 | * for both slots. We use identical speed tables for them. In future use, if | |
46 | * DIMMs have fewer center values that require two separated tables, copy the | |
47 | * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. | |
48 | */ | |
49 | const struct board_specific_parameters *dimms[] = { | |
50 | dimm0, | |
51 | dimm0, | |
c21617fd HW |
52 | }; |
53 | ||
dfb49108 | 54 | void fsl_ddr_board_options(memctl_options_t *popts, |
c21617fd HW |
55 | dimm_params_t *pdimm, |
56 | unsigned int ctrl_num) | |
6a8e5692 | 57 | { |
712cf7ab YS |
58 | const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
59 | unsigned int i; | |
c21617fd | 60 | ulong ddr_freq; |
6a8e5692 | 61 | |
712cf7ab YS |
62 | if (ctrl_num > 1) { |
63 | printf("Wrong parameter for controller number %d", ctrl_num); | |
64 | return; | |
c21617fd | 65 | } |
712cf7ab YS |
66 | for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
67 | if (pdimm[i].n_ranks) | |
68 | break; | |
69 | } | |
70 | if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ | |
71 | return; | |
72 | ||
73 | pbsp = dimms[ctrl_num]; | |
6a8e5692 | 74 | |
c21617fd HW |
75 | /* Get clk_adjust, cpo, write_data_delay, according to the board ddr |
76 | * freqency and n_banks specified in board_specific_parameters table. | |
6a8e5692 | 77 | */ |
5df4b0ad | 78 | ddr_freq = get_ddr_freq(0) / 1000000; |
712cf7ab YS |
79 | while (pbsp->datarate_mhz_high) { |
80 | if (pbsp->n_ranks == pdimm[i].n_ranks) { | |
81 | if (ddr_freq <= pbsp->datarate_mhz_high) { | |
82 | popts->clk_adjust = pbsp->clk_adjust; | |
83 | popts->cpo_override = pbsp->cpo; | |
84 | popts->write_data_delay = | |
85 | pbsp->write_data_delay; | |
86 | goto found; | |
c21617fd | 87 | } |
712cf7ab | 88 | pbsp_highest = pbsp; |
c21617fd | 89 | } |
712cf7ab | 90 | pbsp++; |
c21617fd HW |
91 | } |
92 | ||
712cf7ab YS |
93 | if (pbsp_highest) { |
94 | printf("Error: board specific timing not found " | |
95 | "for data rate %lu MT/s!\n" | |
96 | "Trying to use the highest speed (%u) parameters\n", | |
97 | ddr_freq, pbsp_highest->datarate_mhz_high); | |
98 | popts->clk_adjust = pbsp_highest->clk_adjust; | |
99 | popts->cpo_override = pbsp_highest->cpo; | |
100 | popts->write_data_delay = pbsp_highest->write_data_delay; | |
101 | } else { | |
102 | panic("DIMM is not supported by this board"); | |
939e5bf9 YS |
103 | } |
104 | ||
712cf7ab | 105 | found: |
b4983e16 | 106 | /* 2T timing enable */ |
0dd38a35 | 107 | popts->twot_en = 1; |
6a8e5692 | 108 | } |