[people/ms/u-boot.git] / board / freescale / mx35pdk / lowlevel_init.S

/*
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include "mx35pdk.h"
#include <asm/arch/lowlevel_macro.S>

/*
 * return soc version
 * 	0x10:  TO1
 *	0x20:  TO2
 *	0x30:  TO3
 */
.macro check_soc_version ret, tmp
	ldr \tmp, =IIM_BASE_ADDR
	ldr \ret, [\tmp, #IIM_SREV]
	cmp \ret, #0x00
	moveq \tmp, #ROMPATCH_REV
	ldreq \ret, [\tmp]
	moveq \ret, \ret, lsl #4
	addne \ret, \ret, #0x10
.endm

/* CPLD on CS5 setup */
.macro init_debug_board
	ldr r0, =DBG_BASE_ADDR
	ldr r1, =DBG_CSCR_U_CONFIG
	str r1, [r0, #0x00]
	ldr r1, =DBG_CSCR_L_CONFIG
	str r1, [r0, #0x04]
	ldr r1, =DBG_CSCR_A_CONFIG
	str r1, [r0, #0x08]
.endm

/* clock setup */
.macro init_clock
	ldr r0, =CCM_BASE_ADDR

	/* default CLKO to 1/32 of the ARM core*/
	ldr r1, [r0, #CLKCTL_COSR]
	bic r1, r1, #0x00000FF00
	bic r1, r1, #0x0000000FF
	mov r2, #0x00006C00
	add r2, r2, #0x67
	orr r1, r1, r2
	str r1, [r0, #CLKCTL_COSR]

	ldr r2, =CCM_CCMR_CONFIG
	str r2, [r0, #CLKCTL_CCMR]

	check_soc_version r1, r2
	cmp r1, #CHIP_REV_2_0
	ldrhs r3, =CCM_MPLL_532_HZ
	bhs 1f
	ldr r2, [r0, #CLKCTL_PDR0]
	tst r2, #CLKMODE_CONSUMER
	ldrne r3, =CCM_MPLL_532_HZ  /* consumer path*/
	ldreq r3, =CCM_MPLL_399_HZ  /* auto path*/
1:
	str r3, [r0, #CLKCTL_MPCTL]

	ldr r1, =CCM_PPLL_300_HZ
	str r1, [r0, #CLKCTL_PPCTL]

	ldr r1, =CCM_PDR0_CONFIG
	bic r1, r1, #0x800000
	str r1, [r0, #CLKCTL_PDR0]

	ldr r1, [r0, #CLKCTL_CGR0]
	orr r1, r1, #0x0C300000
	str r1, [r0, #CLKCTL_CGR0]

	ldr r1, [r0, #CLKCTL_CGR1]
	orr r1, r1, #0x00000C00
	orr r1, r1, #0x00000003
	str r1, [r0, #CLKCTL_CGR1]

	ldr r1, [r0, #CLKCTL_CGR2]
	orr r1, r1, #0x00C00000
	str r1, [r0, #CLKCTL_CGR2]
.endm

.macro setup_sdram
	ldr r0, =ESDCTL_BASE_ADDR
	mov r3, #0x2000
	str r3, [r0, #0x0]
	str r3, [r0, #0x8]

	/*ip(r12) has used to save lr register in upper calling*/
	mov fp, lr

	mov r5, #0x00
	mov r2, #0x00
	mov r1, #CSD0_BASE_ADDR
	bl setup_sdram_bank

	mov r5, #0x00
	mov r2, #0x00
	mov r1, #CSD1_BASE_ADDR
	bl setup_sdram_bank

	mov lr, fp

1:
	ldr r3, =ESDCTL_DELAY_LINE5
	str r3, [r0, #0x30]
.endm

.globl lowlevel_init
lowlevel_init:
	mov r10, lr

	core_init

	init_aips

	init_max

	init_m3if

	init_clock
	init_debug_board

	cmp pc, #PHYS_SDRAM_1
	blo init_sdram_start
	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
	blo skip_sdram_setup

init_sdram_start:
	/*init_sdram*/
	setup_sdram

skip_sdram_setup:
	mov lr, r10
	mov pc, lr


/*
 * r0: ESDCTL control base, r1: sdram slot base
 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
 */
setup_sdram_bank:
	mov r3, #0xE
	tst r2, #0x1
	orreq r3, r3, #0x300 /*DDR2*/
	str r3, [r0, #0x10]
	bic r3, r3, #0x00A
	str r3, [r0, #0x10]
	beq 2f

	mov r3, #0x20000
1:      subs r3, r3, #1
	bne 1b

2:      tst r2, #0x1
	ldreq r3, =ESDCTL_DDR2_CONFIG
	ldrne r3, =ESDCTL_MDDR_CONFIG
	cmp r1, #CSD1_BASE_ADDR
	strlo r3, [r0, #0x4]
	strhs r3, [r0, #0xC]

	ldr r3, =ESDCTL_0x92220000
	strlo r3, [r0, #0x0]
	strhs r3, [r0, #0x8]
	mov r3, #0xDA
	ldr r4, =ESDCTL_PRECHARGE
	strb r3, [r1, r4]

	tst r2, #0x1
	bne skip_set_mode

	cmp r1, #CSD1_BASE_ADDR
	ldr r3, =ESDCTL_0xB2220000
	strlo r3, [r0, #0x0]
	strhs r3, [r0, #0x8]
	mov r3, #0xDA
	ldr r4, =ESDCTL_DDR2_EMR2
	strb r3, [r1, r4]
	ldr r4, =ESDCTL_DDR2_EMR3
	strb r3, [r1, r4]
	ldr r4, =ESDCTL_DDR2_EN_DLL
	strb r3, [r1, r4]
	ldr r4, =ESDCTL_DDR2_RESET_DLL
	strb r3, [r1, r4]

	ldr r3, =ESDCTL_0x92220000
	strlo r3, [r0, #0x0]
	strhs r3, [r0, #0x8]
	mov r3, #0xDA
	ldr r4, =ESDCTL_PRECHARGE
	strb r3, [r1, r4]

skip_set_mode:
	cmp r1, #CSD1_BASE_ADDR
	ldr r3, =ESDCTL_0xA2220000
	strlo r3, [r0, #0x0]
	strhs r3, [r0, #0x8]
	mov r3, #0xDA
	strb r3, [r1]
	strb r3, [r1]

	ldr r3, =ESDCTL_0xB2220000
	strlo r3, [r0, #0x0]
	strhs r3, [r0, #0x8]
	tst r2, #0x1
	ldreq r4, =ESDCTL_DDR2_MR
	ldrne r4, =ESDCTL_MDDR_MR
	mov r3, #0xDA
	strb r3, [r1, r4]
	ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
	streqb r3, [r1, r4]
	ldreq r4, =ESDCTL_DDR2_EN_DLL
	ldrne r4, =ESDCTL_MDDR_EMR
	strb r3, [r1, r4]

	cmp r1, #CSD1_BASE_ADDR
	ldr r3, =ESDCTL_0x82228080
	strlo r3, [r0, #0x0]
	strhs r3, [r0, #0x8]

	tst r2, #0x1
	moveq r4, #0x20000
	movne r4, #0x200
1:      subs r4, r4, #1
	bne 1b

	str r3, [r1, #0x100]
	ldr r4, [r1, #0x100]
	cmp r3, r4
	movne r3, #1
	moveq r3, #0

	mov pc, lr
Commit	Line	Data
eae4988b SB	1	/*
	2	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
eae4988b SB	7	*/
	8
	9	#include <config.h>
	10	#include <asm/arch/imx-regs.h>
a4814a69	11	#include <generated/asm-offsets.h>
eae4988b	12	#include "mx35pdk.h"
151d63cb	13	#include <asm/arch/lowlevel_macro.S>
eae4988b SB	14
	15	/*
	16	* return soc version
	17	* 0x10: TO1
	18	* 0x20: TO2
	19	* 0x30: TO3
	20	*/
	21	.macro check_soc_version ret, tmp
	22	ldr \tmp, =IIM_BASE_ADDR
	23	ldr \ret, [\tmp, #IIM_SREV]
	24	cmp \ret, #0x00
	25	moveq \tmp, #ROMPATCH_REV
	26	ldreq \ret, [\tmp]
	27	moveq \ret, \ret, lsl #4
	28	addne \ret, \ret, #0x10
	29	.endm
	30
eae4988b SB	31	/* CPLD on CS5 setup */
	32	.macro init_debug_board
	33	ldr r0, =DBG_BASE_ADDR
	34	ldr r1, =DBG_CSCR_U_CONFIG
	35	str r1, [r0, #0x00]
	36	ldr r1, =DBG_CSCR_L_CONFIG
	37	str r1, [r0, #0x04]
	38	ldr r1, =DBG_CSCR_A_CONFIG
	39	str r1, [r0, #0x08]
	40	.endm
	41
	42	/* clock setup */
	43	.macro init_clock
	44	ldr r0, =CCM_BASE_ADDR
	45
	46	/* default CLKO to 1/32 of the ARM core*/
	47	ldr r1, [r0, #CLKCTL_COSR]
	48	bic r1, r1, #0x00000FF00
	49	bic r1, r1, #0x0000000FF
	50	mov r2, #0x00006C00
	51	add r2, r2, #0x67
	52	orr r1, r1, r2
	53	str r1, [r0, #CLKCTL_COSR]
	54
	55	ldr r2, =CCM_CCMR_CONFIG
	56	str r2, [r0, #CLKCTL_CCMR]
	57
	58	check_soc_version r1, r2
	59	cmp r1, #CHIP_REV_2_0
	60	ldrhs r3, =CCM_MPLL_532_HZ
	61	bhs 1f
	62	ldr r2, [r0, #CLKCTL_PDR0]
	63	tst r2, #CLKMODE_CONSUMER
	64	ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
	65	ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
	66	1:
	67	str r3, [r0, #CLKCTL_MPCTL]
	68
	69	ldr r1, =CCM_PPLL_300_HZ
	70	str r1, [r0, #CLKCTL_PPCTL]
	71
	72	ldr r1, =CCM_PDR0_CONFIG
	73	bic r1, r1, #0x800000
	74	str r1, [r0, #CLKCTL_PDR0]
	75
	76	ldr r1, [r0, #CLKCTL_CGR0]
	77	orr r1, r1, #0x0C300000
	78	str r1, [r0, #CLKCTL_CGR0]
	79
	80	ldr r1, [r0, #CLKCTL_CGR1]
	81	orr r1, r1, #0x00000C00
	82	orr r1, r1, #0x00000003
	83	str r1, [r0, #CLKCTL_CGR1]
961a7628 BT	84
	85	ldr r1, [r0, #CLKCTL_CGR2]
	86	orr r1, r1, #0x00C00000
	87	str r1, [r0, #CLKCTL_CGR2]
eae4988b SB	88	.endm
	89
	90	.macro setup_sdram
	91	ldr r0, =ESDCTL_BASE_ADDR
	92	mov r3, #0x2000
	93	str r3, [r0, #0x0]
	94	str r3, [r0, #0x8]
	95
	96	/ip(r12) has used to save lr register in upper calling/
	97	mov fp, lr
	98
	99	mov r5, #0x00
	100	mov r2, #0x00
	101	mov r1, #CSD0_BASE_ADDR
	102	bl setup_sdram_bank
6b5acfc1 SB	103
	104	mov r5, #0x00
	105	mov r2, #0x00
	106	mov r1, #CSD1_BASE_ADDR
	107	bl setup_sdram_bank
eae4988b SB	108
	109	mov lr, fp
	110
	111	1:
	112	ldr r3, =ESDCTL_DELAY_LINE5
	113	str r3, [r0, #0x30]
	114	.endm
	115
	116	.globl lowlevel_init
	117	lowlevel_init:
	118	mov r10, lr
	119
151d63cb	120	core_init
eae4988b SB	121
	122	init_aips
	123
	124	init_max
	125
	126	init_m3if
	127
	128	init_clock
	129	init_debug_board
	130
	131	cmp pc, #PHYS_SDRAM_1
	132	blo init_sdram_start
	133	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
	134	blo skip_sdram_setup
	135
	136	init_sdram_start:
	137	/init_sdram/
	138	setup_sdram
	139
	140	skip_sdram_setup:
	141	mov lr, r10
	142	mov pc, lr
	143
	144
	145	/*
	146	* r0: ESDCTL control base, r1: sdram slot base
	147	* r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
	148	*/
	149	setup_sdram_bank:
	150	mov r3, #0xE
	151	tst r2, #0x1
	152	orreq r3, r3, #0x300 /DDR2/
	153	str r3, [r0, #0x10]
	154	bic r3, r3, #0x00A
	155	str r3, [r0, #0x10]
	156	beq 2f
	157
	158	mov r3, #0x20000
	159	1: subs r3, r3, #1
	160	bne 1b
	161
	162	2: tst r2, #0x1
	163	ldreq r3, =ESDCTL_DDR2_CONFIG
	164	ldrne r3, =ESDCTL_MDDR_CONFIG
	165	cmp r1, #CSD1_BASE_ADDR
	166	strlo r3, [r0, #0x4]
	167	strhs r3, [r0, #0xC]
	168
	169	ldr r3, =ESDCTL_0x92220000
	170	strlo r3, [r0, #0x0]
	171	strhs r3, [r0, #0x8]
	172	mov r3, #0xDA
	173	ldr r4, =ESDCTL_PRECHARGE
	174	strb r3, [r1, r4]
	175
	176	tst r2, #0x1
	177	bne skip_set_mode
	178
	179	cmp r1, #CSD1_BASE_ADDR
	180	ldr r3, =ESDCTL_0xB2220000
	181	strlo r3, [r0, #0x0]
	182	strhs r3, [r0, #0x8]
	183	mov r3, #0xDA
	184	ldr r4, =ESDCTL_DDR2_EMR2
185	strb r3, [r1, r4]
186	ldr r4, =ESDCTL_DDR2_EMR3
187	strb r3, [r1, r4]
188	ldr r4, =ESDCTL_DDR2_EN_DLL
189	strb r3, [r1, r4]
190	ldr r4, =ESDCTL_DDR2_RESET_DLL
191	strb r3, [r1, r4]
192
193	ldr r3, =ESDCTL_0x92220000
194	strlo r3, [r0, #0x0]
195	strhs r3, [r0, #0x8]
196	mov r3, #0xDA
197	ldr r4, =ESDCTL_PRECHARGE
198	strb r3, [r1, r4]
199
200	skip_set_mode:
201	cmp r1, #CSD1_BASE_ADDR
202	ldr r3, =ESDCTL_0xA2220000
203	strlo r3, [r0, #0x0]
204	strhs r3, [r0, #0x8]
205	mov r3, #0xDA
206	strb r3, [r1]
207	strb r3, [r1]
208
209	ldr r3, =ESDCTL_0xB2220000
210	strlo r3, [r0, #0x0]
211	strhs r3, [r0, #0x8]
212	tst r2, #0x1
213	ldreq r4, =ESDCTL_DDR2_MR
214	ldrne r4, =ESDCTL_MDDR_MR
215	mov r3, #0xDA
216	strb r3, [r1, r4]
217	ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
218	streqb r3, [r1, r4]
219	ldreq r4, =ESDCTL_DDR2_EN_DLL
220	ldrne r4, =ESDCTL_MDDR_EMR
221	strb r3, [r1, r4]
222
223	cmp r1, #CSD1_BASE_ADDR
224	ldr r3, =ESDCTL_0x82228080
225	strlo r3, [r0, #0x0]
226	strhs r3, [r0, #0x8]
227
228	tst r2, #0x1
229	moveq r4, #0x20000
230	movne r4, #0x200
231	1: subs r4, r4, #1
232	bne 1b
233
234	str r3, [r1, #0x100]
235	ldr r4, [r1, #0x100]
236	cmp r3, r4
237	movne r3, #1
238	moveq r3, #0
239
240	mov pc, lr