[people/ms/u-boot.git] / board / freescale / mx35pdk / mx35pdk.c

/*
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <mc9sdz60.h>
#include <mc13892.h>
#include <linux/types.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <netdev.h>

#ifndef CONFIG_BOARD_LATE_INIT
#error "CONFIG_BOARD_LATE_INIT must be set for this board"
#endif

#ifndef CONFIG_BOARD_EARLY_INIT_F
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
#endif

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	u32 size1, size2;

	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);

	gd->ram_size = size1 + size2;

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;

	return 0;
}

#define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)

static void setup_iomux_i2c(void)
{
	static const iomux_v3_cfg_t i2c1_pads[] = {
		NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
	};

	/* setup pins for I2C1 */
	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
}


static void setup_iomux_spi(void)
{
	static const iomux_v3_cfg_t spi_pads[] = {
		MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
		MX35_PAD_CSPI1_MISO__CSPI1_MISO,
		MX35_PAD_CSPI1_SS0__CSPI1_SS0,
		MX35_PAD_CSPI1_SS1__CSPI1_SS1,
		MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
	};

	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}

#define USBOTG_IN_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
				 PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
#define USBOTG_OUT_PAD_CTRL	(PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)

static void setup_iomux_usbotg(void)
{
	static const iomux_v3_cfg_t usbotg_pads[] = {
		NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
				USBOTG_OUT_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
				USBOTG_IN_PAD_CTRL),
	};

	/* Set up pins for USBOTG. */
	imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
}

#define FEC_PAD_CTRL	(PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
		NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
					PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
		NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
	};

	/* setup pins for FEC */
	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

int board_early_init_f(void)
{
	struct ccm_regs *ccm =
		(struct ccm_regs *)IMX_CCM_BASE;

	/* enable clocks */
	writel(readl(&ccm->cgr0) |
		MXC_CCM_CGR0_EMI_MASK |
		MXC_CCM_CGR0_EDIO_MASK |
		MXC_CCM_CGR0_EPIT1_MASK,
		&ccm->cgr0);

	writel(readl(&ccm->cgr1) |
		MXC_CCM_CGR1_FEC_MASK |
		MXC_CCM_CGR1_GPIO1_MASK |
		MXC_CCM_CGR1_GPIO2_MASK |
		MXC_CCM_CGR1_GPIO3_MASK |
		MXC_CCM_CGR1_I2C1_MASK |
		MXC_CCM_CGR1_I2C2_MASK |
		MXC_CCM_CGR1_IPU_MASK,
		&ccm->cgr1);

	/* Setup NAND */
	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);

	setup_iomux_i2c();
	setup_iomux_usbotg();
	setup_iomux_fec();
	setup_iomux_spi();

	return 0;
}

int board_init(void)
{
	gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;	/* board id for linux */
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

static inline int pmic_detect(void)
{
	unsigned int id;
	struct pmic *p = pmic_get("FSL_PMIC");
	if (!p)
		return -ENODEV;

	pmic_reg_read(p, REG_IDENTIFICATION, &id);

	id = (id >> 6) & 0x7;
	if (id == 0x7)
		return 1;
	return 0;
}

u32 get_board_rev(void)
{
	int rev;

	rev = pmic_detect();

	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}

int board_late_init(void)
{
	u8 val;
	u32 pmic_val;
	struct pmic *p;
	int ret;

	ret = pmic_init(I2C_0);
	if (ret)
		return ret;

	if (pmic_detect()) {
		p = pmic_get("FSL_PMIC");
		imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);

		pmic_reg_read(p, REG_SETTING_0, &pmic_val);
		pmic_reg_write(p, REG_SETTING_0,
			pmic_val | VO_1_30V | VO_1_50V);
		pmic_reg_read(p, REG_MODE_0, &pmic_val);
		pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);

		imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);

		gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
	}

	val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
	mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
	mdelay(200);

	val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
	mdelay(200);

	val |= 0x80;
	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);

	/* Print board revision */
	printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);

	return 0;
}

int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_SMC911X)
	int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	if (rc)
		return rc;
#endif
	return cpu_eth_init(bis);
}

#if defined(CONFIG_FSL_ESDHC)

struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};

int board_mmc_init(bd_t *bis)
{
	static const iomux_v3_cfg_t sdhc1_pads[] = {
		MX35_PAD_SD1_CMD__ESDHC1_CMD,
		MX35_PAD_SD1_CLK__ESDHC1_CLK,
		MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
		MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
		MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
		MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
	};

	/* configure pins for SDHC1 only */
	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));

	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
	return fsl_esdhc_initialize(bis, &esdhc_cfg);
}

int board_mmc_getcd(struct mmc *mmc)
{
	return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
}
#endif
Commit	Line	Data
eae4988b SB	1	/*
	2	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
eae4988b SB	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
1221ce45	11	#include <linux/errno.h>
eae4988b SB	12	#include <asm/arch/imx-regs.h>
eae4988b SB	13	#include <asm/arch/crm_regs.h>
a2ac1b3a	14	#include <asm/arch/clock.h>
105c9eaf	15	#include <asm/arch/iomux-mx35.h>
eae4988b	16	#include <i2c.h>
c7336815	17	#include <power/pmic.h>
eae4988b	18	#include <fsl_pmic.h>
3292539e SB	19	#include <mmc.h>
3292539e SB	20	#include <fsl_esdhc.h>
eae4988b SB	21	#include <mc9sdz60.h>
	22	#include <mc13892.h>
	23	#include <linux/types.h>
a4adedd4	24	#include <asm/gpio.h>
eae4988b SB	25	#include <asm/arch/sys_proto.h>
	26	#include <netdev.h>
	27
9660e442 HR	28	#ifndef CONFIG_BOARD_LATE_INIT
9660e442 HR	29	#error "CONFIG_BOARD_LATE_INIT must be set for this board"
eae4988b SB	30	#endif
	31
	32	#ifndef CONFIG_BOARD_EARLY_INIT_F
	33	#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
	34	#endif
	35
eae4988b SB	36	DECLARE_GLOBAL_DATA_PTR;
	37
	38	int dram_init(void)
	39	{
6b5acfc1 SB	40	u32 size1, size2;
	41
	42	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
	43	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
	44
	45	gd->ram_size = size1 + size2;
eae4988b SB	46
	47	return 0;
	48	}
	49
76b00aca	50	int dram_init_banksize(void)
6b5acfc1 SB	51	{
	52	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	53	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	54
	55	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	56	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
76b00aca SG	57
76b00aca SG	58	return 0;
6b5acfc1 SB	59	}
6b5acfc1 SB	60
105c9eaf BT	61	#define I2C_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| PAD_CTL_ODE)
105c9eaf BT	62
eae4988b SB	63	static void setup_iomux_i2c(void)
eae4988b SB	64	{
105c9eaf BT	65	static const iomux_v3_cfg_t i2c1_pads[] = {
	66	NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
	67	NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
	68	};
eae4988b SB	69
eae4988b SB	70	/* setup pins for I2C1 */
105c9eaf	71	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
eae4988b SB	72	}
	73
	74
	75	static void setup_iomux_spi(void)
	76	{
105c9eaf BT	77	static const iomux_v3_cfg_t spi_pads[] = {
	78	MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
	79	MX35_PAD_CSPI1_MISO__CSPI1_MISO,
	80	MX35_PAD_CSPI1_SS0__CSPI1_SS0,
	81	MX35_PAD_CSPI1_SS1__CSPI1_SS1,
	82	MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
	83	};
	84
	85	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
eae4988b SB	86	}
eae4988b SB	87
105c9eaf BT	88	#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| \
	89	PAD_CTL_DSE_LOW \| PAD_CTL_SRE_SLOW)
	90	#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW \| PAD_CTL_SRE_SLOW)
	91
961a7628 BT	92	static void setup_iomux_usbotg(void)
961a7628 BT	93	{
105c9eaf BT	94	static const iomux_v3_cfg_t usbotg_pads[] = {
	95	NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
	96	USBOTG_OUT_PAD_CTRL),
	97	NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
	98	USBOTG_IN_PAD_CTRL),
	99	};
961a7628 BT	100
961a7628 BT	101	/* Set up pins for USBOTG. */
105c9eaf	102	imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
961a7628 BT	103	}
961a7628 BT	104
105c9eaf BT	105	#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW \| PAD_CTL_SRE_SLOW)
105c9eaf BT	106
eae4988b SB	107	static void setup_iomux_fec(void)
eae4988b SB	108	{
105c9eaf BT	109	static const iomux_v3_cfg_t fec_pads[] = {
	110	NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL \|
	111	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	112	NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL \|
	113	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	114	NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL \|
	115	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	116	NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL \|
	117	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	118	NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL \|
	119	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	120	NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
	121	NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
	122	NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
	123	NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL \|
	124	PAD_CTL_HYS \| PAD_CTL_PUS_22K_UP),
	125	NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
	126	NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL \|
	127	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	128	NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL \|
	129	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	130	NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL \|
	131	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	132	NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
	133	NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL \|
	134	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	135	NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
	136	NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL \|
	137	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN),
	138	NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
	139	};
eae4988b SB	140
eae4988b SB	141	/* setup pins for FEC */
105c9eaf	142	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
eae4988b SB	143	}
	144
	145	int board_early_init_f(void)
	146	{
	147	struct ccm_regs *ccm =
	148	(struct ccm_regs *)IMX_CCM_BASE;
	149
	150	/* enable clocks */
	151	writel(readl(&ccm->cgr0) \|
	152	MXC_CCM_CGR0_EMI_MASK \|
34a31bf5	153	MXC_CCM_CGR0_EDIO_MASK \|
eae4988b SB	154	MXC_CCM_CGR0_EPIT1_MASK,
	155	&ccm->cgr0);
	156
	157	writel(readl(&ccm->cgr1) \|
	158	MXC_CCM_CGR1_FEC_MASK \|
	159	MXC_CCM_CGR1_GPIO1_MASK \|
	160	MXC_CCM_CGR1_GPIO2_MASK \|
	161	MXC_CCM_CGR1_GPIO3_MASK \|
	162	MXC_CCM_CGR1_I2C1_MASK \|
	163	MXC_CCM_CGR1_I2C2_MASK \|
	164	MXC_CCM_CGR1_IPU_MASK,
	165	&ccm->cgr1);
	166
	167	/* Setup NAND */
	168	__raw_writel(readl(&ccm->rcsr) \| MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
	169
	170	setup_iomux_i2c();
961a7628	171	setup_iomux_usbotg();
eae4988b SB	172	setup_iomux_fec();
	173	setup_iomux_spi();
	174
	175	return 0;
	176	}
	177
	178	int board_init(void)
	179	{
	180	gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
	181	/* address of boot parameters */
	182	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	183
	184	return 0;
	185	}
	186
	187	static inline int pmic_detect(void)
	188	{
5213d6e4	189	unsigned int id;
c7336815 ŁM	190	struct pmic *p = pmic_get("FSL_PMIC");
	191	if (!p)
	192	return -ENODEV;
eae4988b	193
5213d6e4	194	pmic_reg_read(p, REG_IDENTIFICATION, &id);
eae4988b SB	195
	196	id = (id >> 6) & 0x7;
	197	if (id == 0x7)
	198	return 1;
	199	return 0;
	200	}
	201
	202	u32 get_board_rev(void)
	203	{
	204	int rev;
	205
	206	rev = pmic_detect();
	207
	208	return (get_cpu_rev() & ~(0xF << 8)) \| (rev & 0xF) << 8;
	209	}
	210
	211	int board_late_init(void)
	212	{
	213	u8 val;
	214	u32 pmic_val;
5213d6e4	215	struct pmic *p;
c7336815 ŁM	216	int ret;
c7336815 ŁM	217
570aa2fa	218	ret = pmic_init(I2C_0);
c7336815 ŁM	219	if (ret)
c7336815 ŁM	220	return ret;
eae4988b SB	221
eae4988b SB	222	if (pmic_detect()) {
c7336815	223	p = pmic_get("FSL_PMIC");
105c9eaf	224	imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
eae4988b	225
5213d6e4 SB	226	pmic_reg_read(p, REG_SETTING_0, &pmic_val);
	227	pmic_reg_write(p, REG_SETTING_0,
	228	pmic_val \| VO_1_30V \| VO_1_50V);
	229	pmic_reg_read(p, REG_MODE_0, &pmic_val);
	230	pmic_reg_write(p, REG_MODE_0, pmic_val \| VGEN3EN);
eae4988b	231
105c9eaf	232	imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
eae4988b	233
68088cee	234	gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
eae4988b SB	235	}
	236
	237	val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) \| 0x04;
	238	mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
	239	mdelay(200);
	240
	241	val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
	242	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
	243	mdelay(200);
	244
	245	val \|= 0x80;
	246	mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
	247
eae4988b	248	/* Print board revision */
ba901df4	249	printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
eae4988b SB	250
	251	return 0;
	252	}
	253
	254	int board_eth_init(bd_t *bis)
	255	{
eae4988b	256	#if defined(CONFIG_SMC911X)
a05f4ab6 FE	257	int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	258	if (rc)
	259	return rc;
eae4988b	260	#endif
a05f4ab6	261	return cpu_eth_init(bis);
eae4988b	262	}
3292539e SB	263
	264	#if defined(CONFIG_FSL_ESDHC)
	265
	266	struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
	267
	268	int board_mmc_init(bd_t *bis)
	269	{
105c9eaf BT	270	static const iomux_v3_cfg_t sdhc1_pads[] = {
	271	MX35_PAD_SD1_CMD__ESDHC1_CMD,
	272	MX35_PAD_SD1_CLK__ESDHC1_CLK,
	273	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
	274	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
	275	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
	276	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
	277	};
	278
3292539e	279	/* configure pins for SDHC1 only */
105c9eaf	280	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
3292539e	281
a2ac1b3a	282	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
3292539e SB	283	return fsl_esdhc_initialize(bis, &esdhc_cfg);
	284	}
	285
	286	int board_mmc_getcd(struct mmc *mmc)
	287	{
	288	return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
	289	}
	290	#endif