[people/ms/u-boot.git] / board / freescale / mx51evk / mx51evk.c

/*
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/mx5_video.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR},
	{MMC_SDHC2_BASE_ADDR},
};
#endif

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				PHYS_SDRAM_1_SIZE);
	return 0;
}

u32 get_board_rev(void)
{
	u32 rev = get_cpu_rev();
	if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
		rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
	return rev;
}

#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		MX51_PAD_UART1_RXD__UART1_RXD,
		MX51_PAD_UART1_TXD__UART1_TXD,
		NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
		NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
				PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
		MX51_PAD_NANDF_CS3__FEC_MDC,
		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
		MX51_PAD_NANDF_D9__FEC_RDATA0,
		MX51_PAD_NANDF_CS6__FEC_TDATA3,
		MX51_PAD_NANDF_CS5__FEC_TDATA2,
		MX51_PAD_NANDF_CS4__FEC_TDATA1,
		MX51_PAD_NANDF_D8__FEC_TDATA0,
		MX51_PAD_NANDF_CS7__FEC_TX_EN,
		MX51_PAD_NANDF_CS2__FEC_TX_ER,
		MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
		MX51_PAD_EIM_CS5__FEC_CRS,
		MX51_PAD_EIM_CS4__FEC_RX_ER,
		NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
	};

	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

#ifdef CONFIG_MXC_SPI
static void setup_iomux_spi(void)
{
	static const iomux_v3_cfg_t spi_pads[] = {
		NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
				MX51_GPIO_PAD_CTRL),
		MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
		NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
		NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
	};

	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
#endif

#ifdef CONFIG_USB_EHCI_MX5
#define MX51EVK_USBH1_HUB_RST	IMX_GPIO_NR(1, 7)
#define MX51EVK_USBH1_STP	IMX_GPIO_NR(1, 27)
#define MX51EVK_USB_CLK_EN_B	IMX_GPIO_NR(2, 1)
#define MX51EVK_USB_PHY_RESET	IMX_GPIO_NR(2, 5)

static void setup_usb_h1(void)
{
	static const iomux_v3_cfg_t usb_h1_pads[] = {
		MX51_PAD_USBH1_CLK__USBH1_CLK,
		MX51_PAD_USBH1_DIR__USBH1_DIR,
		MX51_PAD_USBH1_STP__USBH1_STP,
		MX51_PAD_USBH1_NXT__USBH1_NXT,
		MX51_PAD_USBH1_DATA0__USBH1_DATA0,
		MX51_PAD_USBH1_DATA1__USBH1_DATA1,
		MX51_PAD_USBH1_DATA2__USBH1_DATA2,
		MX51_PAD_USBH1_DATA3__USBH1_DATA3,
		MX51_PAD_USBH1_DATA4__USBH1_DATA4,
		MX51_PAD_USBH1_DATA5__USBH1_DATA5,
		MX51_PAD_USBH1_DATA6__USBH1_DATA6,
		MX51_PAD_USBH1_DATA7__USBH1_DATA7,

		NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
		MX51_PAD_EIM_D17__GPIO2_1,
		MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
	};

	imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
}

int board_ehci_hcd_init(int port)
{
	/* Set USBH1_STP to GPIO and toggle it */
	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
						MX51_USBH_PAD_CTRL));

	gpio_direction_output(MX51EVK_USBH1_STP, 0);
	gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
	mdelay(10);
	gpio_set_value(MX51EVK_USBH1_STP, 1);

	/* Set back USBH1_STP to be function */
	imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);

	/* De-assert USB PHY RESETB */
	gpio_set_value(MX51EVK_USB_PHY_RESET, 1);

	/* Drive USB_CLK_EN_B line low */
	gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);

	/* Reset USB hub */
	gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
	mdelay(2);
	gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
	return 0;
}
#endif

static void power_init(void)
{
	unsigned int val;
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
	struct pmic *p;
	int ret;

	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
	if (ret)
		return;

	p = pmic_get("FSL_PMIC");
	if (!p)
		return;

	/* Write needed to Power Gate 2 register */
	pmic_reg_read(p, REG_POWER_MISC, &val);
	val &= ~PWGT2SPIEN;
	pmic_reg_write(p, REG_POWER_MISC, val);

	/* Externally powered */
	pmic_reg_read(p, REG_CHARGE, &val);
	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
	pmic_reg_write(p, REG_CHARGE, val);

	/* power up the system first */
	pmic_reg_write(p, REG_POWER_MISC, PWUP);

	/* Set core voltage to 1.1V */
	pmic_reg_read(p, REG_SW_0, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
	pmic_reg_write(p, REG_SW_0, val);

	/* Setup VCC (SW2) to 1.25 */
	pmic_reg_read(p, REG_SW_1, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
	pmic_reg_write(p, REG_SW_1, val);

	/* Setup 1V2_DIG1 (SW3) to 1.25 */
	pmic_reg_read(p, REG_SW_2, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
	pmic_reg_write(p, REG_SW_2, val);
	udelay(50);

	/* Raise the core frequency to 800MHz */
	writel(0x0, &mxc_ccm->cacrr);

	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
	/* Setup the switcher mode for SW1 & SW2*/
	pmic_reg_read(p, REG_SW_4, &val);
	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
		(SWMODE_MASK << SWMODE2_SHIFT)));
	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
	pmic_reg_write(p, REG_SW_4, val);

	/* Setup the switcher mode for SW3 & SW4 */
	pmic_reg_read(p, REG_SW_5, &val);
	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
		(SWMODE_MASK << SWMODE4_SHIFT)));
	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
	pmic_reg_write(p, REG_SW_5, val);

	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
	pmic_reg_read(p, REG_SETTING_0, &val);
	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
	val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
	pmic_reg_write(p, REG_SETTING_0, val);

	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
	pmic_reg_read(p, REG_SETTING_1, &val);
	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
	pmic_reg_write(p, REG_SETTING_1, val);

	/* Configure VGEN3 and VCAM regulators to use external PNP */
	val = VGEN3CONFIG | VCAMCONFIG;
	pmic_reg_write(p, REG_MODE_1, val);
	udelay(200);

	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
		VVIDEOEN | VAUDIOEN  | VSDEN;
	pmic_reg_write(p, REG_MODE_1, val);

	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
						NO_PAD_CTRL));
	gpio_direction_output(IMX_GPIO_NR(2, 14), 0);

	udelay(500);

	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
}

#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
						NO_PAD_CTRL));
	gpio_direction_input(IMX_GPIO_NR(1, 0));
	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
						NO_PAD_CTRL));
	gpio_direction_input(IMX_GPIO_NR(1, 6));

	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
		ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
	else
		ret = !gpio_get_value(IMX_GPIO_NR(1, 6));

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	static const iomux_v3_cfg_t sd1_pads[] = {
		NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
			PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
			PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
		NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
	};

	static const iomux_v3_cfg_t sd2_pads[] = {
		NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
		NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
		NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
	};

	u32 index;
	int ret;

	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
			index++) {
		switch (index) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(sd1_pads,
							 ARRAY_SIZE(sd1_pads));
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(sd2_pads,
							 ARRAY_SIZE(sd2_pads));
			break;
		default:
			printf("Warning: you configured more ESDHC controller"
				"(%d) as supported by the board(2)\n",
				CONFIG_SYS_FSL_ESDHC_NUM);
			return -EINVAL;
		}
		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
		if (ret)
			return ret;
	}
	return 0;
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();
#ifdef CONFIG_USB_EHCI_MX5
	setup_usb_h1();
#endif
	setup_iomux_lcd();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_MXC_SPI
	setup_iomux_spi();
	power_init();
#endif

	return 0;
}
#endif

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

int checkboard(void)
{
	puts("Board: MX51EVK\n");

	return 0;
}
Commit	Line	Data
c5fb70c9 SB	1	/*
	2	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
c5fb70c9 SB	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
753fc2eb	9	#include <asm/gpio.h>
c5fb70c9	10	#include <asm/arch/imx-regs.h>
4d15d36c	11	#include <asm/arch/iomux-mx51.h>
1221ce45	12	#include <linux/errno.h>
e4d34492	13	#include <asm/arch/sys_proto.h>
b4377e12	14	#include <asm/arch/crm_regs.h>
a2ac1b3a	15	#include <asm/arch/clock.h>
552a848e	16	#include <asm/mach-imx/mx5_video.h>
c5fb70c9 SB	17	#include <i2c.h>
	18	#include <mmc.h>
	19	#include <fsl_esdhc.h>
c7336815	20	#include <power/pmic.h>
b4377e12 SB	21	#include <fsl_pmic.h>
b4377e12 SB	22	#include <mc13892.h>
e162c6b1	23	#include <usb/ehci-ci.h>
c5fb70c9 SB	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
c5fb70c9 SB	27	#ifdef CONFIG_FSL_ESDHC
c5fb70c9 SB	28	struct fsl_esdhc_cfg esdhc_cfg[2] = {
16e43f35 BT	29	{MMC_SDHC1_BASE_ADDR},
16e43f35 BT	30	{MMC_SDHC2_BASE_ADDR},
c5fb70c9 SB	31	};
	32	#endif
	33
c5fb70c9 SB	34	int dram_init(void)
c5fb70c9 SB	35	{
1ab027cb	36	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	37	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
1ab027cb	38	PHYS_SDRAM_1_SIZE);
c5fb70c9 SB	39	return 0;
	40	}
	41
362635bd BT	42	u32 get_board_rev(void)
	43	{
	44	u32 rev = get_cpu_rev();
	45	if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
	46	rev \|= BOARD_REV_2_0 << BOARD_VER_OFFSET;
	47	return rev;
	48	}
	49
4d15d36c BT	50	#define UART_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| PAD_CTL_DSE_HIGH)
4d15d36c BT	51
c5fb70c9 SB	52	static void setup_iomux_uart(void)
c5fb70c9 SB	53	{
4d15d36c BT	54	static const iomux_v3_cfg_t uart_pads[] = {
	55	MX51_PAD_UART1_RXD__UART1_RXD,
	56	MX51_PAD_UART1_TXD__UART1_TXD,
	57	NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
	58	NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
	59	};
	60
	61	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
c5fb70c9 SB	62	}
c5fb70c9 SB	63
c5fb70c9 SB	64	static void setup_iomux_fec(void)
c5fb70c9 SB	65	{
4d15d36c BT	66	static const iomux_v3_cfg_t fec_pads[] = {
	67	NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS \|
	68	PAD_CTL_PUS_22K_UP \| PAD_CTL_ODE \|
	69	PAD_CTL_DSE_HIGH \| PAD_CTL_SRE_FAST),
	70	MX51_PAD_NANDF_CS3__FEC_MDC,
	71	NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
	72	NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
	73	NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
	74	MX51_PAD_NANDF_D9__FEC_RDATA0,
	75	MX51_PAD_NANDF_CS6__FEC_TDATA3,
	76	MX51_PAD_NANDF_CS5__FEC_TDATA2,
	77	MX51_PAD_NANDF_CS4__FEC_TDATA1,
	78	MX51_PAD_NANDF_D8__FEC_TDATA0,
	79	MX51_PAD_NANDF_CS7__FEC_TX_EN,
	80	MX51_PAD_NANDF_CS2__FEC_TX_ER,
	81	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
	82	NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
	83	NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
	84	MX51_PAD_EIM_CS5__FEC_CRS,
	85	MX51_PAD_EIM_CS4__FEC_RX_ER,
	86	NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
	87	};
	88
	89	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
c5fb70c9 SB	90	}
c5fb70c9 SB	91
b4377e12 SB	92	#ifdef CONFIG_MXC_SPI
	93	static void setup_iomux_spi(void)
	94	{
4d15d36c BT	95	static const iomux_v3_cfg_t spi_pads[] = {
	96	NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS \|
	97	PAD_CTL_DSE_HIGH \| PAD_CTL_SRE_FAST),
	98	NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS \|
	99	PAD_CTL_DSE_HIGH \| PAD_CTL_SRE_FAST),
	100	NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
	101	MX51_GPIO_PAD_CTRL),
	102	MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
	103	NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
	104	NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS \|
	105	PAD_CTL_DSE_HIGH \| PAD_CTL_SRE_FAST),
	106	};
	107
	108	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
b4377e12 SB	109	}
	110	#endif
	111
055d9693	112	#ifdef CONFIG_USB_EHCI_MX5
4d15d36c BT	113	#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
4d15d36c BT	114	#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
76494f7a	115	#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
4d15d36c	116	#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
055d9693 WG	117
	118	static void setup_usb_h1(void)
	119	{
4d15d36c BT	120	static const iomux_v3_cfg_t usb_h1_pads[] = {
	121	MX51_PAD_USBH1_CLK__USBH1_CLK,
	122	MX51_PAD_USBH1_DIR__USBH1_DIR,
	123	MX51_PAD_USBH1_STP__USBH1_STP,
	124	MX51_PAD_USBH1_NXT__USBH1_NXT,
	125	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	126	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	127	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	128	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	129	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	130	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	131	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	132	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	133
	134	NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
	135	MX51_PAD_EIM_D17__GPIO2_1,
	136	MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
	137	};
	138
	139	imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
055d9693 WG	140	}
055d9693 WG	141
60bae5ef	142	int board_ehci_hcd_init(int port)
055d9693 WG	143	{
055d9693 WG	144	/* Set USBH1_STP to GPIO and toggle it */
4d15d36c BT	145	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
4d15d36c BT	146	MX51_USBH_PAD_CTRL));
055d9693 WG	147
	148	gpio_direction_output(MX51EVK_USBH1_STP, 0);
	149	gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
	150	mdelay(10);
	151	gpio_set_value(MX51EVK_USBH1_STP, 1);
	152
	153	/* Set back USBH1_STP to be function */
4d15d36c	154	imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
055d9693 WG	155
	156	/* De-assert USB PHY RESETB */
	157	gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
	158
	159	/* Drive USB_CLK_EN_B line low */
	160	gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
	161
	162	/* Reset USB hub */
	163	gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
	164	mdelay(2);
	165	gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
60bae5ef	166	return 0;
055d9693 WG	167	}
	168	#endif
	169
b4377e12 SB	170	static void power_init(void)
	171	{
	172	unsigned int val;
b4377e12	173	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )MXC_CCM_BASE;
5357265a	174	struct pmic *p;
c7336815	175	int ret;
5357265a	176
56f9cfbb	177	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
c7336815 ŁM	178	if (ret)
	179	return;
	180
	181	p = pmic_get("FSL_PMIC");
	182	if (!p)
	183	return;
b4377e12 SB	184
b4377e12 SB	185	/* Write needed to Power Gate 2 register */
5357265a	186	pmic_reg_read(p, REG_POWER_MISC, &val);
b4377e12	187	val &= ~PWGT2SPIEN;
5357265a	188	pmic_reg_write(p, REG_POWER_MISC, val);
b4377e12	189
888b4f43	190	/* Externally powered */
5357265a	191	pmic_reg_read(p, REG_CHARGE, &val);
888b4f43	192	val \|= ICHRG0 \| ICHRG1 \| ICHRG2 \| ICHRG3 \| CHGAUTOB;
5357265a	193	pmic_reg_write(p, REG_CHARGE, val);
b4377e12 SB	194
b4377e12 SB	195	/* power up the system first */
5357265a	196	pmic_reg_write(p, REG_POWER_MISC, PWUP);
b4377e12 SB	197
b4377e12 SB	198	/* Set core voltage to 1.1V */
5357265a	199	pmic_reg_read(p, REG_SW_0, &val);
c4a3c744	200	val = (val & ~SWx_VOLT_MASK) \| SWx_1_100V;
5357265a	201	pmic_reg_write(p, REG_SW_0, val);
b4377e12 SB	202
b4377e12 SB	203	/* Setup VCC (SW2) to 1.25 */
5357265a	204	pmic_reg_read(p, REG_SW_1, &val);
c4a3c744	205	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
5357265a	206	pmic_reg_write(p, REG_SW_1, val);
b4377e12 SB	207
b4377e12 SB	208	/* Setup 1V2_DIG1 (SW3) to 1.25 */
5357265a	209	pmic_reg_read(p, REG_SW_2, &val);
c4a3c744	210	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
5357265a	211	pmic_reg_write(p, REG_SW_2, val);
b4377e12 SB	212	udelay(50);
	213
	214	/* Raise the core frequency to 800MHz */
	215	writel(0x0, &mxc_ccm->cacrr);
	216
	217	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
	218	/* Setup the switcher mode for SW1 & SW2*/
5357265a	219	pmic_reg_read(p, REG_SW_4, &val);
b4377e12 SB	220	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) \|
	221	(SWMODE_MASK << SWMODE2_SHIFT)));
	222	val \|= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) \|
	223	(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
5357265a	224	pmic_reg_write(p, REG_SW_4, val);
b4377e12 SB	225
b4377e12 SB	226	/* Setup the switcher mode for SW3 & SW4 */
5357265a	227	pmic_reg_read(p, REG_SW_5, &val);
b4377e12 SB	228	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) \|
	229	(SWMODE_MASK << SWMODE4_SHIFT)));
	230	val \|= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) \|
	231	(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
5357265a	232	pmic_reg_write(p, REG_SW_5, val);
b4377e12 SB	233
b4377e12 SB	234	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
5357265a	235	pmic_reg_read(p, REG_SETTING_0, &val);
b4377e12 SB	236	val &= ~(VCAM_MASK \| VGEN3_MASK \| VDIG_MASK);
b4377e12 SB	237	val \|= VDIG_1_65 \| VGEN3_1_8 \| VCAM_2_6;
5357265a	238	pmic_reg_write(p, REG_SETTING_0, val);
b4377e12 SB	239
b4377e12 SB	240	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
5357265a	241	pmic_reg_read(p, REG_SETTING_1, &val);
b4377e12 SB	242	val &= ~(VVIDEO_MASK \| VSD_MASK \| VAUDIO_MASK);
b4377e12 SB	243	val \|= VSD_3_15 \| VAUDIO_3_0 \| VVIDEO_2_775;
5357265a	244	pmic_reg_write(p, REG_SETTING_1, val);
b4377e12 SB	245
	246	/* Configure VGEN3 and VCAM regulators to use external PNP */
	247	val = VGEN3CONFIG \| VCAMCONFIG;
5357265a	248	pmic_reg_write(p, REG_MODE_1, val);
b4377e12 SB	249	udelay(200);
b4377e12 SB	250
b4377e12 SB	251	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
	252	val = VGEN3EN \| VGEN3CONFIG \| VCAMEN \| VCAMCONFIG \|
	253	VVIDEOEN \| VAUDIOEN \| VSDEN;
5357265a	254	pmic_reg_write(p, REG_MODE_1, val);
b4377e12	255
4d15d36c BT	256	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
4d15d36c BT	257	NO_PAD_CTRL));
92550708	258	gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
d736ebea	259
b4377e12 SB	260	udelay(500);
b4377e12 SB	261
92550708	262	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
b4377e12 SB	263	}
b4377e12 SB	264
c5fb70c9	265	#ifdef CONFIG_FSL_ESDHC
314284b1	266	int board_mmc_getcd(struct mmc *mmc)
c5fb70c9 SB	267	{
c5fb70c9 SB	268	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
314284b1	269	int ret;
c5fb70c9	270
4d15d36c BT	271	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
4d15d36c BT	272	NO_PAD_CTRL));
92550708	273	gpio_direction_input(IMX_GPIO_NR(1, 0));
4d15d36c BT	274	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
4d15d36c BT	275	NO_PAD_CTRL));
92550708	276	gpio_direction_input(IMX_GPIO_NR(1, 6));
58aef72d	277
c5fb70c9	278	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
92550708	279	ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
c5fb70c9	280	else
92550708	281	ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
c5fb70c9	282
314284b1	283	return ret;
c5fb70c9 SB	284	}
	285
	286	int board_mmc_init(bd_t *bis)
	287	{
4d15d36c BT	288	static const iomux_v3_cfg_t sd1_pads[] = {
	289	NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX \|
	290	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	291	NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX \|
	292	PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	293	NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX \|
	294	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	295	NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX \|
	296	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	297	NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX \|
	298	PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| PAD_CTL_SRE_FAST),
	299	NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX \|
	300	PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| PAD_CTL_SRE_FAST),
	301	NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
	302	NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
	303	};
	304
	305	static const iomux_v3_cfg_t sd2_pads[] = {
	306	NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
	307	PAD_CTL_DSE_MAX \| PAD_CTL_SRE_FAST),
	308	NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
	309	PAD_CTL_DSE_MAX \| PAD_CTL_SRE_FAST),
	310	NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
	311	PAD_CTL_DSE_MAX \| PAD_CTL_SRE_FAST),
	312	NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
	313	PAD_CTL_DSE_MAX \| PAD_CTL_SRE_FAST),
	314	NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
	315	PAD_CTL_DSE_MAX \| PAD_CTL_SRE_FAST),
	316	NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
	317	PAD_CTL_DSE_MAX \| PAD_CTL_SRE_FAST),
	318	NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
	319	NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
	320	};
	321
c5fb70c9	322	u32 index;
d6af507d	323	int ret;
c5fb70c9	324
a2ac1b3a BT	325	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	326	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	327
c5fb70c9 SB	328	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
	329	index++) {
	330	switch (index) {
	331	case 0:
4d15d36c BT	332	imx_iomux_v3_setup_multiple_pads(sd1_pads,
4d15d36c BT	333	ARRAY_SIZE(sd1_pads));
c5fb70c9 SB	334	break;
c5fb70c9 SB	335	case 1:
4d15d36c BT	336	imx_iomux_v3_setup_multiple_pads(sd2_pads,
4d15d36c BT	337	ARRAY_SIZE(sd2_pads));
c5fb70c9 SB	338	break;
	339	default:
	340	printf("Warning: you configured more ESDHC controller"
	341	"(%d) as supported by the board(2)\n",
	342	CONFIG_SYS_FSL_ESDHC_NUM);
d6af507d	343	return -EINVAL;
c5fb70c9	344	}
d6af507d FE	345	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
	346	if (ret)
	347	return ret;
c5fb70c9	348	}
d6af507d	349	return 0;
c5fb70c9 SB	350	}
	351	#endif
	352
877eb0f9 LHR	353	int board_early_init_f(void)
	354	{
	355	setup_iomux_uart();
	356	setup_iomux_fec();
055d9693 WG	357	#ifdef CONFIG_USB_EHCI_MX5
	358	setup_usb_h1();
	359	#endif
5d71bd21	360	setup_iomux_lcd();
877eb0f9 LHR	361
	362	return 0;
	363	}
	364
c5fb70c9 SB	365	int board_init(void)
c5fb70c9 SB	366	{
c5fb70c9 SB	367	/* address of boot parameters */
	368	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	369
c5fb70c9 SB	370	return 0;
	371	}
	372
9660e442	373	#ifdef CONFIG_BOARD_LATE_INIT
b4377e12 SB	374	int board_late_init(void)
	375	{
	376	#ifdef CONFIG_MXC_SPI
	377	setup_iomux_spi();
	378	power_init();
	379	#endif
f1adefd2	380
b4377e12 SB	381	return 0;
	382	}
	383	#endif
	384
1e080988 FE	385	/*
	386	* Do not overwrite the console
	387	* Use always serial for U-Boot console
	388	*/
	389	int overwrite_console(void)
	390	{
	391	return 1;
	392	}
	393
c5fb70c9 SB	394	int checkboard(void)
c5fb70c9 SB	395	{
51958904	396	puts("Board: MX51EVK\n");
c5fb70c9	397
c5fb70c9 SB	398	return 0;
c5fb70c9 SB	399	}