[people/ms/u-boot.git] / board / freescale / mx53evk / mx53evk.c

/*
 * (C) Copyright 2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <linux/errno.h>
#include <asm/mach-imx/boot_mode.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
#include <mc13892.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				PHYS_SDRAM_1_SIZE);
	return 0;
}

#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
			 PAD_CTL_HYS | PAD_CTL_ODE)

static void setup_i2c(unsigned int port_number)
{
	static const iomux_v3_cfg_t i2c1_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
	};

	static const iomux_v3_cfg_t i2c2_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
	};

	switch (port_number) {
	case 0:
		imx_iomux_v3_setup_multiple_pads(i2c1_pads,
							ARRAY_SIZE(i2c1_pads));
		break;
	case 1:
		imx_iomux_v3_setup_multiple_pads(i2c2_pads,
							ARRAY_SIZE(i2c2_pads));
		break;
	default:
		printf("Warning: Wrong I2C port number\n");
		break;
	}
}

void power_init(void)
{
	unsigned int val;
	struct pmic *p;
	int ret;

	ret = pmic_init(I2C_0);
	if (ret)
		return;

	p = pmic_get("FSL_PMIC");
	if (!p)
		return;

	/* Set VDDA to 1.25V */
	pmic_reg_read(p, REG_SW_2, &val);
	val &= ~SWX_OUT_MASK;
	val |= SWX_OUT_1_25;
	pmic_reg_write(p, REG_SW_2, val);

	/*
	 * Need increase VCC and VDDA to 1.3V
	 * according to MX53 IC TO2 datasheet.
	 */
	if (is_soc_rev(CHIP_REV_2_0) == 0) {
		/* Set VCC to 1.3V for TO2 */
		pmic_reg_read(p, REG_SW_1, &val);
		val &= ~SWX_OUT_MASK;
		val |= SWX_OUT_1_30;
		pmic_reg_write(p, REG_SW_1, val);

		/* Set VDDA to 1.3V for TO2 */
		pmic_reg_read(p, REG_SW_2, &val);
		val &= ~SWX_OUT_MASK;
		val |= SWX_OUT_1_30;
		pmic_reg_write(p, REG_SW_2, val);
	}
}

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
				PAD_CTL_HYS | PAD_CTL_PKE),
	};

	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR},
	{MMC_SDHC3_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
	gpio_direction_input(IMX_GPIO_NR(3, 11));
	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
	gpio_direction_input(IMX_GPIO_NR(3, 13));

	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
		ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
	else
		ret = !gpio_get_value(IMX_GPIO_NR(3, 11));

	return ret;
}

#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
				 PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
				 PAD_CTL_DSE_HIGH)

int board_mmc_init(bd_t *bis)
{
	static const iomux_v3_cfg_t sd1_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
		MX53_PAD_EIM_DA13__GPIO3_13,
	};

	static const iomux_v3_cfg_t sd2_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
				SD_CMD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
		MX53_PAD_EIM_DA11__GPIO3_11,
	};

	u32 index;
	int ret;

	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
		switch (index) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(sd1_pads,
							 ARRAY_SIZE(sd1_pads));
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(sd2_pads,
							 ARRAY_SIZE(sd2_pads));
			break;
		default:
			printf("Warning: you configured more ESDHC controller"
				"(%d) as supported by the board(2)\n",
				CONFIG_SYS_FSL_ESDHC_NUM);
			return -EINVAL;
		}
		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
		if (ret)
			return ret;
	}

	return 0;
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"mmc0",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
	{"mmc1",	MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
	{NULL,		0},
};
#endif

int board_late_init(void)
{
	setup_i2c(1);
	power_init();

#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif
	return 0;
}

int checkboard(void)
{
	puts("Board: MX53EVK\n");

	return 0;
}
Commit	Line	Data
94391fbc LHR	1	/*
	2	* (C) Copyright 2010 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
94391fbc LHR	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/imx-regs.h>
94391fbc LHR	10	#include <asm/arch/sys_proto.h>
94391fbc LHR	11	#include <asm/arch/crm_regs.h>
a2ac1b3a	12	#include <asm/arch/clock.h>
58f07646	13	#include <asm/arch/iomux-mx53.h>
1221ce45	14	#include <linux/errno.h>
552a848e	15	#include <asm/mach-imx/boot_mode.h>
94391fbc LHR	16	#include <netdev.h>
	17	#include <i2c.h>
	18	#include <mmc.h>
	19	#include <fsl_esdhc.h>
c7336815	20	#include <power/pmic.h>
94391fbc	21	#include <fsl_pmic.h>
f7a36474	22	#include <asm/gpio.h>
94391fbc LHR	23	#include <mc13892.h>
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
94391fbc LHR	27	int dram_init(void)
	28	{
	29	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	30	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
94391fbc LHR	31	PHYS_SDRAM_1_SIZE);
	32	return 0;
	33	}
	34
58f07646 BT	35	#define UART_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_DSE_HIGH \| \
	36	PAD_CTL_PUS_100K_UP \| PAD_CTL_ODE)
	37
94391fbc LHR	38	static void setup_iomux_uart(void)
94391fbc LHR	39	{
58f07646 BT	40	static const iomux_v3_cfg_t uart_pads[] = {
	41	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
	42	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
	43	};
	44
	45	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
94391fbc LHR	46	}
94391fbc LHR	47
58f07646 BT	48	#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST \| PAD_CTL_DSE_HIGH \| \
	49	PAD_CTL_HYS \| PAD_CTL_ODE)
	50
94391fbc LHR	51	static void setup_i2c(unsigned int port_number)
94391fbc LHR	52	{
58f07646 BT	53	static const iomux_v3_cfg_t i2c1_pads[] = {
	54	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
	55	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
	56	};
	57
	58	static const iomux_v3_cfg_t i2c2_pads[] = {
	59	NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
	60	NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
	61	};
	62
94391fbc LHR	63	switch (port_number) {
94391fbc LHR	64	case 0:
58f07646 BT	65	imx_iomux_v3_setup_multiple_pads(i2c1_pads,
58f07646 BT	66	ARRAY_SIZE(i2c1_pads));
94391fbc LHR	67	break;
94391fbc LHR	68	case 1:
58f07646 BT	69	imx_iomux_v3_setup_multiple_pads(i2c2_pads,
58f07646 BT	70	ARRAY_SIZE(i2c2_pads));
94391fbc LHR	71	break;
	72	default:
	73	printf("Warning: Wrong I2C port number\n");
	74	break;
	75	}
	76	}
	77
	78	void power_init(void)
	79	{
	80	unsigned int val;
bba1b6cf	81	struct pmic *p;
c7336815	82	int ret;
bba1b6cf	83
570aa2fa	84	ret = pmic_init(I2C_0);
c7336815 ŁM	85	if (ret)
	86	return;
	87
	88	p = pmic_get("FSL_PMIC");
	89	if (!p)
	90	return;
94391fbc LHR	91
94391fbc LHR	92	/* Set VDDA to 1.25V */
bba1b6cf	93	pmic_reg_read(p, REG_SW_2, &val);
94391fbc LHR	94	val &= ~SWX_OUT_MASK;
94391fbc LHR	95	val \|= SWX_OUT_1_25;
bba1b6cf	96	pmic_reg_write(p, REG_SW_2, val);
94391fbc LHR	97
	98	/*
	99	* Need increase VCC and VDDA to 1.3V
	100	* according to MX53 IC TO2 datasheet.
	101	*/
	102	if (is_soc_rev(CHIP_REV_2_0) == 0) {
	103	/* Set VCC to 1.3V for TO2 */
bba1b6cf	104	pmic_reg_read(p, REG_SW_1, &val);
94391fbc LHR	105	val &= ~SWX_OUT_MASK;
94391fbc LHR	106	val \|= SWX_OUT_1_30;
bba1b6cf	107	pmic_reg_write(p, REG_SW_1, val);
94391fbc LHR	108
94391fbc LHR	109	/* Set VDDA to 1.3V for TO2 */
bba1b6cf	110	pmic_reg_read(p, REG_SW_2, &val);
94391fbc LHR	111	val &= ~SWX_OUT_MASK;
94391fbc LHR	112	val \|= SWX_OUT_1_30;
bba1b6cf	113	pmic_reg_write(p, REG_SW_2, val);
94391fbc LHR	114	}
	115	}
	116
	117	static void setup_iomux_fec(void)
	118	{
58f07646 BT	119	static const iomux_v3_cfg_t fec_pads[] = {
	120	NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS \|
	121	PAD_CTL_DSE_HIGH \| PAD_CTL_PUS_22K_UP \| PAD_CTL_ODE),
	122	NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
	123	NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
	124	PAD_CTL_HYS \| PAD_CTL_PKE),
	125	NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
	126	PAD_CTL_HYS \| PAD_CTL_PKE),
	127	NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
	128	NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
	129	NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
	130	NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
	131	PAD_CTL_HYS \| PAD_CTL_PKE),
	132	NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
	133	PAD_CTL_HYS \| PAD_CTL_PKE),
	134	NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
	135	PAD_CTL_HYS \| PAD_CTL_PKE),
	136	};
	137
	138	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
94391fbc LHR	139	}
	140
	141	#ifdef CONFIG_FSL_ESDHC
	142	struct fsl_esdhc_cfg esdhc_cfg[2] = {
16e43f35 BT	143	{MMC_SDHC1_BASE_ADDR},
16e43f35 BT	144	{MMC_SDHC3_BASE_ADDR},
94391fbc LHR	145	};
94391fbc LHR	146
314284b1	147	int board_mmc_getcd(struct mmc *mmc)
94391fbc LHR	148	{
94391fbc LHR	149	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
314284b1	150	int ret;
94391fbc	151
58f07646	152	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
92550708	153	gpio_direction_input(IMX_GPIO_NR(3, 11));
58f07646	154	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
92550708	155	gpio_direction_input(IMX_GPIO_NR(3, 13));
a146dca5	156
94391fbc	157	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
92550708	158	ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
94391fbc	159	else
92550708	160	ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
94391fbc	161
314284b1	162	return ret;
94391fbc LHR	163	}
94391fbc LHR	164
58f07646 BT	165	#define SD_CMD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_DSE_HIGH \| \
	166	PAD_CTL_PUS_100K_UP)
	167	#define SD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	168	PAD_CTL_DSE_HIGH)
	169
94391fbc LHR	170	int board_mmc_init(bd_t *bis)
94391fbc LHR	171	{
58f07646 BT	172	static const iomux_v3_cfg_t sd1_pads[] = {
	173	NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
	174	NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
	175	NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
	176	NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
	177	NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
	178	NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
	179	MX53_PAD_EIM_DA13__GPIO3_13,
	180	};
	181
	182	static const iomux_v3_cfg_t sd2_pads[] = {
	183	NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
	184	SD_CMD_PAD_CTRL),
	185	NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
	186	NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
	187	NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
	188	NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
	189	NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
	190	NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
	191	NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
	192	NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
	193	NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
	194	MX53_PAD_EIM_DA11__GPIO3_11,
	195	};
	196
94391fbc	197	u32 index;
1abd714d	198	int ret;
94391fbc	199
a2ac1b3a BT	200	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	201	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	202
94391fbc LHR	203	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
	204	switch (index) {
	205	case 0:
58f07646 BT	206	imx_iomux_v3_setup_multiple_pads(sd1_pads,
58f07646 BT	207	ARRAY_SIZE(sd1_pads));
94391fbc LHR	208	break;
94391fbc LHR	209	case 1:
58f07646 BT	210	imx_iomux_v3_setup_multiple_pads(sd2_pads,
58f07646 BT	211	ARRAY_SIZE(sd2_pads));
94391fbc LHR	212	break;
	213	default:
	214	printf("Warning: you configured more ESDHC controller"
	215	"(%d) as supported by the board(2)\n",
	216	CONFIG_SYS_FSL_ESDHC_NUM);
1abd714d	217	return -EINVAL;
94391fbc	218	}
1abd714d FE	219	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
	220	if (ret)
	221	return ret;
94391fbc LHR	222	}
94391fbc LHR	223
1abd714d	224	return 0;
94391fbc LHR	225	}
	226	#endif
	227
	228	int board_early_init_f(void)
	229	{
	230	setup_iomux_uart();
	231	setup_iomux_fec();
	232
	233	return 0;
	234	}
	235
	236	int board_init(void)
	237	{
94391fbc LHR	238	/* address of boot parameters */
	239	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	240
	241	return 0;
	242	}
	243
0aff384b TK	244	#ifdef CONFIG_CMD_BMODE
	245	static const struct boot_mode board_boot_modes[] = {
	246	/* 4 bit bus width */
	247	{"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
	248	{"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
	249	{NULL, 0},
	250	};
	251	#endif
	252
94391fbc LHR	253	int board_late_init(void)
	254	{
	255	setup_i2c(1);
	256	power_init();
	257
0aff384b TK	258	#ifdef CONFIG_CMD_BMODE
	259	add_board_boot_modes(board_boot_modes);
	260	#endif
94391fbc LHR	261	return 0;
	262	}
	263
	264	int checkboard(void)
	265	{
51958904	266	puts("Board: MX53EVK\n");
94391fbc	267
94391fbc LHR	268	return 0;
94391fbc LHR	269	}