[people/ms/u-boot.git] / board / freescale / mx53loco / mx53loco.c

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 * Jason Liu <r64343@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <linux/errno.h>
#include <asm/imx-common/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/gpio.h>
#include <power/pmic.h>
#include <dialog_pmic.h>
#include <fsl_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>

#define MX53LOCO_LCD_POWER		IMX_GPIO_NR(3, 24)

DECLARE_GLOBAL_DATA_PTR;

static uint32_t mx53_dram_size[2];

phys_size_t get_effective_memsize(void)
{
	/*
	 * WARNING: We must override get_effective_memsize() function here
	 * to report only the size of the first DRAM bank. This is to make
	 * U-Boot relocator place U-Boot into valid memory, that is, at the
	 * end of the first DRAM bank. If we did not override this function
	 * like so, U-Boot would be placed at the address of the first DRAM
	 * bank + total DRAM size - sizeof(uboot), which in the setup where
	 * each DRAM bank contains 512MiB of DRAM would result in placing
	 * U-Boot into invalid memory area close to the end of the first
	 * DRAM bank.
	 */
	return mx53_dram_size[0];
}

int dram_init(void)
{
	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);

	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = mx53_dram_size[0];

	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = mx53_dram_size[1];

	return 0;
}

u32 get_board_rev(void)
{
	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
	struct fuse_bank *bank = &iim->bank[0];
	struct fuse_bank0_regs *fuse =
		(struct fuse_bank0_regs *)bank->fuse_regs;

	int rev = readl(&fuse->gp[6]);

	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
		rev = 0;

	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}

#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
	/* request VBUS power enable pin, GPIO7_8 */
	imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
	return 0;
}
#endif

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
				PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
				PAD_CTL_HYS | PAD_CTL_PKE),
	};

	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR},
	{MMC_SDHC3_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
	gpio_direction_input(IMX_GPIO_NR(3, 11));
	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
	gpio_direction_input(IMX_GPIO_NR(3, 13));

	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
		ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
	else
		ret = !gpio_get_value(IMX_GPIO_NR(3, 11));

	return ret;
}

#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
				 PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
				 PAD_CTL_DSE_HIGH)

int board_mmc_init(bd_t *bis)
{
	static const iomux_v3_cfg_t sd1_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
		MX53_PAD_EIM_DA13__GPIO3_13,
	};

	static const iomux_v3_cfg_t sd2_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
				SD_CMD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
		MX53_PAD_EIM_DA11__GPIO3_11,
	};

	u32 index;
	int ret;

	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
		switch (index) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(sd1_pads,
							 ARRAY_SIZE(sd1_pads));
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(sd2_pads,
							 ARRAY_SIZE(sd2_pads));
			break;
		default:
			printf("Warning: you configured more ESDHC controller"
				"(%d) as supported by the board(2)\n",
				CONFIG_SYS_FSL_ESDHC_NUM);
			return -EINVAL;
		}
		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
		if (ret)
			return ret;
	}

	return 0;
}
#endif

#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)

static void setup_iomux_i2c(void)
{
	static const iomux_v3_cfg_t i2c1_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
}

static int power_init(void)
{
	unsigned int val;
	int ret;
	struct pmic *p;

	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
		ret = pmic_dialog_init(I2C_PMIC);
		if (ret)
			return ret;

		p = pmic_get("DIALOG_PMIC");
		if (!p)
			return -ENODEV;

		setenv("fdt_file", "imx53-qsb.dtb");

		/* Set VDDA to 1.25V */
		val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
		ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
		if (ret) {
			printf("Writing to BUCKCORE_REG failed: %d\n", ret);
			return ret;
		}

		pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
		val |= DA9052_SUPPLY_VBCOREGO;
		ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
		if (ret) {
			printf("Writing to SUPPLY_REG failed: %d\n", ret);
			return ret;
		}

		/* Set Vcc peripheral to 1.30V */
		ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
		if (ret) {
			printf("Writing to BUCKPRO_REG failed: %d\n", ret);
			return ret;
		}

		ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
		if (ret) {
			printf("Writing to SUPPLY_REG failed: %d\n", ret);
			return ret;
		}

		return ret;
	}

	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
		ret = pmic_init(I2C_0);
		if (ret)
			return ret;

		p = pmic_get("FSL_PMIC");
		if (!p)
			return -ENODEV;

		setenv("fdt_file", "imx53-qsrb.dtb");

		/* Set VDDGP to 1.25V for 1GHz on SW1 */
		pmic_reg_read(p, REG_SW_0, &val);
		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
		ret = pmic_reg_write(p, REG_SW_0, val);
		if (ret) {
			printf("Writing to REG_SW_0 failed: %d\n", ret);
			return ret;
		}

		/* Set VCC as 1.30V on SW2 */
		pmic_reg_read(p, REG_SW_1, &val);
		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
		ret = pmic_reg_write(p, REG_SW_1, val);
		if (ret) {
			printf("Writing to REG_SW_1 failed: %d\n", ret);
			return ret;
		}

		/* Set global reset timer to 4s */
		pmic_reg_read(p, REG_POWER_CTL2, &val);
		val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
		ret = pmic_reg_write(p, REG_POWER_CTL2, val);
		if (ret) {
			printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
			return ret;
		}

		/* Set VUSBSEL and VUSBEN for USB PHY supply*/
		pmic_reg_read(p, REG_MODE_0, &val);
		val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
		ret = pmic_reg_write(p, REG_MODE_0, val);
		if (ret) {
			printf("Writing to REG_MODE_0 failed: %d\n", ret);
			return ret;
		}

		/* Set SWBST to 5V in auto mode */
		val = SWBST_AUTO;
		ret = pmic_reg_write(p, SWBST_CTRL, val);
		if (ret) {
			printf("Writing to SWBST_CTRL failed: %d\n", ret);
			return ret;
		}

		return ret;
	}

	return -1;
}

static void clock_1GHz(void)
{
	int ret;
	u32 ref_clk = MXC_HCLK;
	/*
	 * After increasing voltage to 1.25V, we can switch
	 * CPU clock to 1GHz and DDR to 400MHz safely
	 */
	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
	if (ret)
		printf("CPU:   Switch CPU clock to 1GHZ failed\n");

	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
	if (ret)
		printf("CPU:   Switch DDR clock to 400MHz failed\n");
}

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();
	setup_iomux_lcd();

	return 0;
}

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	mxc_set_sata_internal_clock();
	setup_iomux_i2c();

	return 0;
}

int board_late_init(void)
{
	if (!power_init())
		clock_1GHz();

	return 0;
}

int checkboard(void)
{
	puts("Board: MX53 LOCO\n");

	return 0;
}
Commit	Line	Data
938080dc JL	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	3	* Jason Liu <r64343@freescale.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
938080dc JL	6	*/
	7
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/imx-regs.h>
938080dc JL	11	#include <asm/arch/sys_proto.h>
938080dc JL	12	#include <asm/arch/crm_regs.h>
f92e4e6c	13	#include <asm/arch/clock.h>
721d0b00	14	#include <asm/arch/iomux-mx53.h>
938080dc	15	#include <asm/arch/clock.h>
1221ce45	16	#include <linux/errno.h>
30ea4be9	17	#include <asm/imx-common/mx5_video.h>
938080dc JL	18	#include <netdev.h>
	19	#include <i2c.h>
	20	#include <mmc.h>
	21	#include <fsl_esdhc.h>
50410078	22	#include <asm/gpio.h>
c7336815	23	#include <power/pmic.h>
e7e33722	24	#include <dialog_pmic.h>
5b547f3c	25	#include <fsl_pmic.h>
f714b0a9 FE	26	#include <linux/fb.h>
	27	#include <ipu_pixfmt.h>
	28
3ef0a312	29	#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
938080dc JL	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
31c832f9 MV	33	static uint32_t mx53_dram_size[2];
	34
	35	phys_size_t get_effective_memsize(void)
938080dc	36	{
31c832f9 MV	37	/*
	38	* WARNING: We must override get_effective_memsize() function here
	39	* to report only the size of the first DRAM bank. This is to make
	40	* U-Boot relocator place U-Boot into valid memory, that is, at the
	41	* end of the first DRAM bank. If we did not override this function
	42	* like so, U-Boot would be placed at the address of the first DRAM
	43	* bank + total DRAM size - sizeof(uboot), which in the setup where
	44	* each DRAM bank contains 512MiB of DRAM would result in placing
	45	* U-Boot into invalid memory area close to the end of the first
	46	* DRAM bank.
	47	*/
	48	return mx53_dram_size[0];
	49	}
938080dc	50
31c832f9 MV	51	int dram_init(void)
	52	{
	53	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	54	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
938080dc	55
31c832f9	56	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
938080dc JL	57
	58	return 0;
	59	}
31c832f9	60
76b00aca	61	int dram_init_banksize(void)
938080dc JL	62	{
938080dc JL	63	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
31c832f9	64	gd->bd->bi_dram[0].size = mx53_dram_size[0];
938080dc JL	65
938080dc JL	66	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
31c832f9	67	gd->bd->bi_dram[1].size = mx53_dram_size[1];
76b00aca SG	68
76b00aca SG	69	return 0;
938080dc JL	70	}
938080dc JL	71
54cd1dee FE	72	u32 get_board_rev(void)
	73	{
	74	struct iim_regs iim = (struct iim_regs )IMX_IIM_BASE;
	75	struct fuse_bank *bank = &iim->bank[0];
	76	struct fuse_bank0_regs *fuse =
	77	(struct fuse_bank0_regs *)bank->fuse_regs;
	78
	79	int rev = readl(&fuse->gp[6]);
	80
eae08eb2 FE	81	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
	82	rev = 0;
	83
54cd1dee FE	84	return (get_cpu_rev() & ~(0xF << 8)) \| (rev & 0xF) << 8;
	85	}
	86
721d0b00 BT	87	#define UART_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_DSE_HIGH \| \
	88	PAD_CTL_PUS_100K_UP \| PAD_CTL_ODE)
	89
938080dc JL	90	static void setup_iomux_uart(void)
938080dc JL	91	{
721d0b00 BT	92	static const iomux_v3_cfg_t uart_pads[] = {
	93	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
	94	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
	95	};
	96
	97	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
938080dc JL	98	}
938080dc JL	99
45cf6ada	100	#ifdef CONFIG_USB_EHCI_MX5
60bae5ef	101	int board_ehci_hcd_init(int port)
45cf6ada	102	{
6ecaee82	103	/* request VBUS power enable pin, GPIO7_8 */
721d0b00 BT	104	imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
721d0b00 BT	105	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
60bae5ef	106	return 0;
45cf6ada WG	107	}
	108	#endif
	109
938080dc JL	110	static void setup_iomux_fec(void)
938080dc JL	111	{
721d0b00 BT	112	static const iomux_v3_cfg_t fec_pads[] = {
	113	NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS \|
	114	PAD_CTL_DSE_HIGH \| PAD_CTL_PUS_22K_UP \| PAD_CTL_ODE),
	115	NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
	116	NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
	117	PAD_CTL_HYS \| PAD_CTL_PKE),
	118	NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
	119	PAD_CTL_HYS \| PAD_CTL_PKE),
	120	NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
	121	NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
	122	NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
	123	NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
	124	PAD_CTL_HYS \| PAD_CTL_PKE),
	125	NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
	126	PAD_CTL_HYS \| PAD_CTL_PKE),
	127	NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
	128	PAD_CTL_HYS \| PAD_CTL_PKE),
	129	};
	130
	131	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
938080dc JL	132	}
	133
	134	#ifdef CONFIG_FSL_ESDHC
	135	struct fsl_esdhc_cfg esdhc_cfg[2] = {
16e43f35 BT	136	{MMC_SDHC1_BASE_ADDR},
16e43f35 BT	137	{MMC_SDHC3_BASE_ADDR},
938080dc JL	138	};
938080dc JL	139
314284b1	140	int board_mmc_getcd(struct mmc *mmc)
938080dc JL	141	{
938080dc JL	142	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
314284b1	143	int ret;
938080dc	144
721d0b00	145	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
92550708	146	gpio_direction_input(IMX_GPIO_NR(3, 11));
721d0b00	147	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
92550708	148	gpio_direction_input(IMX_GPIO_NR(3, 13));
73128aad	149
938080dc	150	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
92550708	151	ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
938080dc	152	else
92550708	153	ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
938080dc	154
314284b1	155	return ret;
938080dc JL	156	}
938080dc JL	157
721d0b00 BT	158	#define SD_CMD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_DSE_HIGH \| \
	159	PAD_CTL_PUS_100K_UP)
	160	#define SD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	161	PAD_CTL_DSE_HIGH)
	162
938080dc JL	163	int board_mmc_init(bd_t *bis)
938080dc JL	164	{
721d0b00 BT	165	static const iomux_v3_cfg_t sd1_pads[] = {
	166	NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
	167	NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
	168	NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
	169	NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
	170	NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
	171	NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
	172	MX53_PAD_EIM_DA13__GPIO3_13,
	173	};
	174
	175	static const iomux_v3_cfg_t sd2_pads[] = {
	176	NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
	177	SD_CMD_PAD_CTRL),
	178	NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
	179	NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
	180	NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
	181	NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
	182	NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
	183	NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
	184	NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
	185	NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
	186	NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
	187	MX53_PAD_EIM_DA11__GPIO3_11,
	188	};
	189
938080dc	190	u32 index;
1769502b	191	int ret;
938080dc	192
a2ac1b3a BT	193	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	194	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	195
938080dc JL	196	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
	197	switch (index) {
	198	case 0:
721d0b00 BT	199	imx_iomux_v3_setup_multiple_pads(sd1_pads,
721d0b00 BT	200	ARRAY_SIZE(sd1_pads));
938080dc JL	201	break;
938080dc JL	202	case 1:
721d0b00 BT	203	imx_iomux_v3_setup_multiple_pads(sd2_pads,
721d0b00 BT	204	ARRAY_SIZE(sd2_pads));
938080dc JL	205	break;
	206	default:
	207	printf("Warning: you configured more ESDHC controller"
	208	"(%d) as supported by the board(2)\n",
	209	CONFIG_SYS_FSL_ESDHC_NUM);
1769502b	210	return -EINVAL;
938080dc	211	}
1769502b FE	212	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
	213	if (ret)
	214	return ret;
938080dc JL	215	}
938080dc JL	216
1769502b	217	return 0;
938080dc JL	218	}
	219	#endif
	220
721d0b00 BT	221	#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST \| PAD_CTL_DSE_HIGH \| \
	222	PAD_CTL_PUS_100K_UP \| PAD_CTL_ODE)
	223
e7e33722 FE	224	static void setup_iomux_i2c(void)
e7e33722 FE	225	{
721d0b00 BT	226	static const iomux_v3_cfg_t i2c1_pads[] = {
	227	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
	228	NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
	229	};
	230
	231	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
e7e33722 FE	232	}
	233
	234	static int power_init(void)
	235	{
5b547f3c	236	unsigned int val;
085e728a	237	int ret;
e7e33722 FE	238	struct pmic *p;
e7e33722 FE	239
5b547f3c	240	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
d2292510 FE	241	ret = pmic_dialog_init(I2C_PMIC);
	242	if (ret)
	243	return ret;
c7336815 ŁM	244
	245	p = pmic_get("DIALOG_PMIC");
	246	if (!p)
	247	return -ENODEV;
e7e33722	248
4ccaf5dd FE	249	setenv("fdt_file", "imx53-qsb.dtb");
4ccaf5dd FE	250
5b547f3c FE	251	/* Set VDDA to 1.25V */
	252	val = DA9052_BUCKCORE_BCOREEN \| DA_BUCKCORE_VBCORE_1_250V;
	253	ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
085e728a FE	254	if (ret) {
	255	printf("Writing to BUCKCORE_REG failed: %d\n", ret);
	256	return ret;
	257	}
e7e33722	258
085e728a	259	pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
5b547f3c	260	val \|= DA9052_SUPPLY_VBCOREGO;
085e728a FE	261	ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
	262	if (ret) {
	263	printf("Writing to SUPPLY_REG failed: %d\n", ret);
	264	return ret;
	265	}
e7e33722	266
5b547f3c	267	/* Set Vcc peripheral to 1.30V */
085e728a FE	268	ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
	269	if (ret) {
	270	printf("Writing to BUCKPRO_REG failed: %d\n", ret);
	271	return ret;
	272	}
	273
	274	ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
	275	if (ret) {
	276	printf("Writing to SUPPLY_REG failed: %d\n", ret);
	277	return ret;
	278	}
	279
	280	return ret;
5b547f3c FE	281	}
	282
	283	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
570aa2fa	284	ret = pmic_init(I2C_0);
d2292510 FE	285	if (ret)
d2292510 FE	286	return ret;
c7336815	287
8965112b	288	p = pmic_get("FSL_PMIC");
c7336815 ŁM	289	if (!p)
c7336815 ŁM	290	return -ENODEV;
5b547f3c	291
4ccaf5dd FE	292	setenv("fdt_file", "imx53-qsrb.dtb");
4ccaf5dd FE	293
5b547f3c FE	294	/* Set VDDGP to 1.25V for 1GHz on SW1 */
	295	pmic_reg_read(p, REG_SW_0, &val);
	296	val = (val & ~SWx_VOLT_MASK_MC34708) \| SWx_1_250V_MC34708;
	297	ret = pmic_reg_write(p, REG_SW_0, val);
085e728a FE	298	if (ret) {
	299	printf("Writing to REG_SW_0 failed: %d\n", ret);
	300	return ret;
	301	}
5b547f3c FE	302
	303	/* Set VCC as 1.30V on SW2 */
	304	pmic_reg_read(p, REG_SW_1, &val);
	305	val = (val & ~SWx_VOLT_MASK_MC34708) \| SWx_1_300V_MC34708;
085e728a FE	306	ret = pmic_reg_write(p, REG_SW_1, val);
	307	if (ret) {
	308	printf("Writing to REG_SW_1 failed: %d\n", ret);
	309	return ret;
	310	}
5b547f3c FE	311
	312	/* Set global reset timer to 4s */
	313	pmic_reg_read(p, REG_POWER_CTL2, &val);
	314	val = (val & ~TIMER_MASK_MC34708) \| TIMER_4S_MC34708;
085e728a FE	315	ret = pmic_reg_write(p, REG_POWER_CTL2, val);
	316	if (ret) {
	317	printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
	318	return ret;
	319	}
768a0597 FE	320
	321	/* Set VUSBSEL and VUSBEN for USB PHY supply*/
	322	pmic_reg_read(p, REG_MODE_0, &val);
	323	val \|= (VUSBSEL_MC34708 \| VUSBEN_MC34708);
085e728a FE	324	ret = pmic_reg_write(p, REG_MODE_0, val);
	325	if (ret) {
	326	printf("Writing to REG_MODE_0 failed: %d\n", ret);
	327	return ret;
	328	}
768a0597 FE	329
	330	/* Set SWBST to 5V in auto mode */
	331	val = SWBST_AUTO;
085e728a FE	332	ret = pmic_reg_write(p, SWBST_CTRL, val);
	333	if (ret) {
	334	printf("Writing to SWBST_CTRL failed: %d\n", ret);
	335	return ret;
	336	}
	337
	338	return ret;
5b547f3c	339	}
e7e33722	340
085e728a	341	return -1;
e7e33722 FE	342	}
	343
	344	static void clock_1GHz(void)
	345	{
	346	int ret;
833b6435	347	u32 ref_clk = MXC_HCLK;
e7e33722 FE	348	/*
	349	* After increasing voltage to 1.25V, we can switch
	350	* CPU clock to 1GHz and DDR to 400MHz safely
	351	*/
	352	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
	353	if (ret)
	354	printf("CPU: Switch CPU clock to 1GHZ failed\n");
	355
	356	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
	357	ret \|= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
	358	if (ret)
	359	printf("CPU: Switch DDR clock to 400MHz failed\n");
	360	}
	361
938080dc JL	362	int board_early_init_f(void)
	363	{
	364	setup_iomux_uart();
	365	setup_iomux_fec();
30ea4be9	366	setup_iomux_lcd();
938080dc JL	367
	368	return 0;
	369	}
	370
3e077370 SB	371	/*
	372	* Do not overwrite the console
	373	* Use always serial for U-Boot console
	374	*/
	375	int overwrite_console(void)
1fc56f1c	376	{
3e077370	377	return 1;
1fc56f1c	378	}
1fc56f1c	379
938080dc JL	380	int board_init(void)
938080dc JL	381	{
938080dc JL	382	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
938080dc JL	383
f92e4e6c	384	mxc_set_sata_internal_clock();
eae08eb2	385	setup_iomux_i2c();
54bb8411	386
54bb8411 FE	387	return 0;
	388	}
	389
	390	int board_late_init(void)
	391	{
eae08eb2 FE	392	if (!power_init())
eae08eb2 FE	393	clock_1GHz();
f92e4e6c	394
938080dc JL	395	return 0;
	396	}
	397
	398	int checkboard(void)
	399	{
	400	puts("Board: MX53 LOCO\n");
	401
	402	return 0;
	403	}