[people/ms/u-boot.git] / board / freescale / mx6qarm2 / mx6qarm2.c

/*
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6q_pins.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

	return 0;
}

iomux_v3_cfg_t const uart4_pads[] = {
	MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_CS0__GPIO_6_11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};

iomux_v3_cfg_t const usdhc4_pads[] = {
	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

iomux_v3_cfg_t const enet_pads[] = {
	MX6_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};


static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC3_BASE_ADDR},
	{USDHC4_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
		gpio_direction_input(IMX_GPIO_NR(6, 11));
		ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
	} else /* Don't have the CD GPIO pin on board */
		ret = 1;

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	s32 status = 0;
	u32 index = 0;

	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
		switch (index) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
			break;
		default:
			printf("Warning: you configured more USDHC controllers"
				"(%d) then supported by the board (%d)\n",
				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
			return status;
		}

		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
	}

	return status;
}
#endif

#define MII_MMD_ACCESS_CTRL_REG		0xd
#define MII_MMD_ACCESS_ADDR_DATA_REG	0xe
#define MII_DBG_PORT_REG		0x1d
#define MII_DBG_PORT2_REG		0x1e

int fecmxc_mii_postcall(int phy)
{
	unsigned short val;

	/*
	 * Due to the i.MX6Q Armadillo2 board HW design,there is
	 * no 125Mhz clock input from SOC. In order to use RGMII,
	 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
	 */
	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
	val &= 0xffe3;
	val |= 0x18;
	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);

	/* For the RGMII phy, we need enable tx clock delay */
	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
	val |= 0x0100;
	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);

	miiphy_write("FEC", phy, MII_BMCR, 0xa100);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	struct eth_device *dev;
	int ret;

	ret = cpu_eth_init(bis);
	if (ret) {
		printf("FEC MXC: %s:failed\n", __func__);
		return ret;
	}

	dev = eth_get_dev_by_name("FEC");
	if (!dev) {
		printf("FEC MXC: Unable to get FEC device entry\n");
		return -EINVAL;
	}

	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
	if (ret) {
		printf("FEC MXC: Unable to register FEC mii postcall\n");
		return ret;
	}

	return 0;
}

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_enet();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	return 0;
}

int checkboard(void)
{
	puts("Board: MX6Q-Armadillo2\n");

	return 0;
}
Commit	Line	Data
76d7f574 JL	1	/*
	2	* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
76d7f574 JL	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/imx-regs.h>
cfb8b9d3	10	#include <asm/arch/mx6q_pins.h>
a2ac1b3a	11	#include <asm/arch/clock.h>
76d7f574 JL	12	#include <asm/errno.h>
76d7f574 JL	13	#include <asm/gpio.h>
af2a35fb	14	#include <asm/imx-common/iomux-v3.h>
76d7f574 JL	15	#include <mmc.h>
76d7f574 JL	16	#include <fsl_esdhc.h>
473c6359 JL	17	#include <miiphy.h>
473c6359 JL	18	#include <netdev.h>
76d7f574 JL	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
7e2173cf BT	22	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	23	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	24	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
76d7f574	25
7e2173cf BT	26	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	27	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	28	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
76d7f574	29
7e2173cf BT	30	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
7e2173cf BT	31	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
473c6359	32
76d7f574 JL	33	int dram_init(void)
	34	{
	35	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	36
	37	return 0;
	38	}
	39
6e142320	40	iomux_v3_cfg_t const uart4_pads[] = {
cfb8b9d3 EN	41	MX6_PAD_KEY_COL0__UART4_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
cfb8b9d3 EN	42	MX6_PAD_KEY_ROW0__UART4_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
76d7f574 JL	43	};
76d7f574 JL	44
6e142320	45	iomux_v3_cfg_t const usdhc3_pads[] = {
cfb8b9d3 EN	46	MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	47	MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	48	MX6_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	49	MX6_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	50	MX6_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	51	MX6_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	52	MX6_PAD_SD3_DAT4__USDHC3_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	53	MX6_PAD_SD3_DAT5__USDHC3_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	54	MX6_PAD_SD3_DAT6__USDHC3_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	55	MX6_PAD_SD3_DAT7__USDHC3_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	56	MX6_PAD_NANDF_CS0__GPIO_6_11 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
76d7f574 JL	57	};
76d7f574 JL	58
6e142320	59	iomux_v3_cfg_t const usdhc4_pads[] = {
cfb8b9d3 EN	60	MX6_PAD_SD4_CLK__USDHC4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	61	MX6_PAD_SD4_CMD__USDHC4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	62	MX6_PAD_SD4_DAT0__USDHC4_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	63	MX6_PAD_SD4_DAT1__USDHC4_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	64	MX6_PAD_SD4_DAT2__USDHC4_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	65	MX6_PAD_SD4_DAT3__USDHC4_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	66	MX6_PAD_SD4_DAT4__USDHC4_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	67	MX6_PAD_SD4_DAT5__USDHC4_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	68	MX6_PAD_SD4_DAT6__USDHC4_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	69	MX6_PAD_SD4_DAT7__USDHC4_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
76d7f574 JL	70	};
76d7f574 JL	71
6e142320	72	iomux_v3_cfg_t const enet_pads[] = {
cfb8b9d3 EN	73	MX6_PAD_KEY_COL1__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	74	MX6_PAD_KEY_COL2__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	75	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	76	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	77	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	78	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	79	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	80	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	81	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	82	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	83	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	84	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	85	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	86	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	87	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
473c6359 JL	88	};
	89
	90
76d7f574 JL	91	static void setup_iomux_uart(void)
	92	{
	93	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
	94	}
	95
473c6359 JL	96	static void setup_iomux_enet(void)
	97	{
	98	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	99	}
	100
76d7f574 JL	101	#ifdef CONFIG_FSL_ESDHC
76d7f574 JL	102	struct fsl_esdhc_cfg usdhc_cfg[2] = {
16e43f35 BT	103	{USDHC3_BASE_ADDR},
16e43f35 BT	104	{USDHC4_BASE_ADDR},
76d7f574 JL	105	};
76d7f574 JL	106
b125e7bd	107	int board_mmc_getcd(struct mmc *mmc)
76d7f574 JL	108	{
76d7f574 JL	109	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
b125e7bd	110	int ret;
76d7f574 JL	111
76d7f574 JL	112	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
acbdea2e AKR	113	gpio_direction_input(IMX_GPIO_NR(6, 11));
acbdea2e AKR	114	ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
76d7f574	115	} else /* Don't have the CD GPIO pin on board */
b125e7bd	116	ret = 1;
76d7f574	117
b125e7bd	118	return ret;
76d7f574 JL	119	}
	120
	121	int board_mmc_init(bd_t *bis)
	122	{
	123	s32 status = 0;
	124	u32 index = 0;
	125
a2ac1b3a BT	126	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	127	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	128
76d7f574 JL	129	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
	130	switch (index) {
	131	case 0:
	132	imx_iomux_v3_setup_multiple_pads(
	133	usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	134	break;
	135	case 1:
	136	imx_iomux_v3_setup_multiple_pads(
	137	usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
	138	break;
	139	default:
	140	printf("Warning: you configured more USDHC controllers"
	141	"(%d) then supported by the board (%d)\n",
	142	index + 1, CONFIG_SYS_FSL_USDHC_NUM);
	143	return status;
	144	}
	145
	146	status \|= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
	147	}
	148
	149	return status;
	150	}
	151	#endif
	152
473c6359 JL	153	#define MII_MMD_ACCESS_CTRL_REG 0xd
	154	#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
	155	#define MII_DBG_PORT_REG 0x1d
	156	#define MII_DBG_PORT2_REG 0x1e
	157
	158	int fecmxc_mii_postcall(int phy)
	159	{
	160	unsigned short val;
	161
	162	/*
	163	* Due to the i.MX6Q Armadillo2 board HW design,there is
	164	* no 125Mhz clock input from SOC. In order to use RGMII,
	165	* We need enable AR8031 ouput a 125MHz clk from CLK_25M
	166	*/
	167	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
	168	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
	169	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
	170	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
	171	val &= 0xffe3;
	172	val \|= 0x18;
	173	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
	174
	175	/* For the RGMII phy, we need enable tx clock delay */
	176	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
	177	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
	178	val \|= 0x0100;
	179	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
	180
	181	miiphy_write("FEC", phy, MII_BMCR, 0xa100);
	182
	183	return 0;
	184	}
	185
	186	int board_eth_init(bd_t *bis)
	187	{
	188	struct eth_device *dev;
	189	int ret;
	190
	191	ret = cpu_eth_init(bis);
	192	if (ret) {
	193	printf("FEC MXC: %s:failed\n", __func__);
	194	return ret;
	195	}
	196
	197	dev = eth_get_dev_by_name("FEC");
	198	if (!dev) {
	199	printf("FEC MXC: Unable to get FEC device entry\n");
	200	return -EINVAL;
	201	}
	202
	203	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
	204	if (ret) {
	205	printf("FEC MXC: Unable to register FEC mii postcall\n");
	206	return ret;
	207	}
	208
	209	return 0;
	210	}
	211
76d7f574 JL	212	int board_early_init_f(void)
	213	{
	214	setup_iomux_uart();
473c6359	215	setup_iomux_enet();
76d7f574 JL	216
	217	return 0;
	218	}
	219
	220	int board_init(void)
	221	{
	222	/* address of boot parameters */
	223	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	224
	225	return 0;
	226	}
	227
	228	int checkboard(void)
	229	{
	230	puts("Board: MX6Q-Armadillo2\n");
	231
	232	return 0;
	233	}