[people/ms/u-boot.git] / board / freescale / mx6qsabreauto / mx6qsabreauto.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6q_pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
	PAD_CTL_ODE | PAD_CTL_SRE_FAST)

#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

	return 0;
}

iomux_v3_cfg_t const uart4_pads[] = {
	MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

iomux_v3_cfg_t const enet_pads[] = {
	MX6_PAD_KEY_COL1__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_COL2__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
};

/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
		.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
		.gp = IMX_GPIO_NR(2, 30)
	},
	.sda = {
		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
		.gp = IMX_GPIO_NR(4, 13)
	}
};

/*
 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
 * Compass Sensor, Accelerometer, Res Touch
 */
struct i2c_pads_info i2c_pad_info2 = {
	.scl = {
		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
		.gp = IMX_GPIO_NR(1, 3)
	},
	.sda = {
		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
		.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
		.gp = IMX_GPIO_NR(3, 18)
	}
};

iomux_v3_cfg_t const i2c3_pads[] = {
	MX6_PAD_EIM_A24__GPIO_5_4		| MUX_PAD_CTRL(NO_PAD_CTRL),
};

iomux_v3_cfg_t const port_exp[] = {
	MX6_PAD_SD2_DAT0__GPIO_1_15		| MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}

iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__USDHC3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__USDHC3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__USDHC3_DAT0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__USDHC3_DAT1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__USDHC3_DAT2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__USDHC3_DAT3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__USDHC3_DAT4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__USDHC3_DAT5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__USDHC3_DAT6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__USDHC3_DAT7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_CS2__GPIO_6_15   | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC3_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	gpio_direction_input(IMX_GPIO_NR(6, 15));
	return !gpio_get_value(IMX_GPIO_NR(6, 15));
}

int board_mmc_init(bd_t *bis)
{
	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif

int mx6_rgmii_rework(struct phy_device *phydev)
{
	unsigned short val;

	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* introduce tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	val |= 0x0100;
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	int ret;

	setup_iomux_enet();

	ret = cpu_eth_init(bis);
	if (ret)
		printf("FEC MXC: %s:failed\n", __func__);

	return 0;
}

#define BOARD_REV_B  0x200
#define BOARD_REV_A  0x100

static int mx6sabre_rev(void)
{
	/*
	 * Get Board ID information from OCOTP_GP1[15:8]
	 * i.MX6Q ARD RevA: 0x01
	 * i.MX6Q ARD RevB: 0x02
	 */
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;
	int reg = readl(&fuse->gp1);
	int ret;

	switch (reg >> 8 & 0x0F) {
	case 0x02:
		ret = BOARD_REV_B;
		break;
	case 0x01:
	default:
		ret = BOARD_REV_A;
		break;
	}

	return ret;
}

u32 get_board_rev(void)
{
	int rev = mx6sabre_rev();

	return (get_cpu_rev() & ~(0xF << 8)) | rev;
}

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	/* I2C 3 Steer */
	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{NULL,   0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

	return 0;
}

int checkboard(void)
{
	int rev = mx6sabre_rev();
	char *revname;

	switch (rev) {
	case BOARD_REV_B:
		revname = "B";
		break;
	case BOARD_REV_A:
	default:
		revname = "A";
		break;
	}

	printf("Board: MX6Q-Sabreauto rev%s\n", revname);

	return 0;
}
Commit	Line	Data
7dd6545d FE	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
7dd6545d FE	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/clock.h>
	12	#include <asm/arch/imx-regs.h>
	13	#include <asm/arch/iomux.h>
cfb8b9d3	14	#include <asm/arch/mx6q_pins.h>
7dd6545d FE	15	#include <asm/errno.h>
	16	#include <asm/gpio.h>
	17	#include <asm/imx-common/iomux-v3.h>
19578165	18	#include <asm/imx-common/mxc_i2c.h>
85449dbd	19	#include <asm/imx-common/boot_mode.h>
7dd6545d FE	20	#include <mmc.h>
7dd6545d FE	21	#include <fsl_esdhc.h>
fe5ebe97 FE	22	#include <miiphy.h>
fe5ebe97 FE	23	#include <netdev.h>
dce67bd5	24	#include <asm/arch/sys_proto.h>
19578165	25	#include <i2c.h>
dce67bd5	26
7dd6545d FE	27	DECLARE_GLOBAL_DATA_PTR;
7dd6545d FE	28
7e2173cf BT	29	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	30	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	31	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
7dd6545d	32
7e2173cf BT	33	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	34	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	35	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
7dd6545d	36
7e2173cf BT	37	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
7e2173cf BT	38	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
fe5ebe97	39
19578165 RF	40	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	41	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	42	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	43
	44	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	45
7dd6545d FE	46	int dram_init(void)
	47	{
	48	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	49
	50	return 0;
	51	}
	52
6e142320	53	iomux_v3_cfg_t const uart4_pads[] = {
cfb8b9d3 EN	54	MX6_PAD_KEY_COL0__UART4_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
cfb8b9d3 EN	55	MX6_PAD_KEY_ROW0__UART4_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
7dd6545d FE	56	};
7dd6545d FE	57
6e142320	58	iomux_v3_cfg_t const enet_pads[] = {
cfb8b9d3 EN	59	MX6_PAD_KEY_COL1__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	60	MX6_PAD_KEY_COL2__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	61	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	62	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	63	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	64	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	65	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	66	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	67	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	68	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	69	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	70	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	71	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	72	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	73	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
fe5ebe97 FE	74	};
fe5ebe97 FE	75
19578165 RF	76	/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
	77	struct i2c_pads_info i2c_pad_info1 = {
	78	.scl = {
	79	.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL \| PC,
	80	.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 \| PC,
	81	.gp = IMX_GPIO_NR(2, 30)
	82	},
	83	.sda = {
	84	.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA \| PC,
	85	.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 \| PC,
	86	.gp = IMX_GPIO_NR(4, 13)
	87	}
	88	};
	89
	90	/*
	91	* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
	92	* Compass Sensor, Accelerometer, Res Touch
	93	*/
	94	struct i2c_pads_info i2c_pad_info2 = {
	95	.scl = {
	96	.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL \| PC,
	97	.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 \| PC,
	98	.gp = IMX_GPIO_NR(1, 3)
	99	},
	100	.sda = {
	101	.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA \| PC,
	102	.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 \| PC,
	103	.gp = IMX_GPIO_NR(3, 18)
	104	}
	105	};
	106
	107	iomux_v3_cfg_t const i2c3_pads[] = {
	108	MX6_PAD_EIM_A24__GPIO_5_4 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	109	};
	110
a1f67807 RF	111	iomux_v3_cfg_t const port_exp[] = {
	112	MX6_PAD_SD2_DAT0__GPIO_1_15 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	113	};
	114
fe5ebe97 FE	115	static void setup_iomux_enet(void)
	116	{
	117	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	118	}
	119
6e142320	120	iomux_v3_cfg_t const usdhc3_pads[] = {
cfb8b9d3 EN	121	MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	122	MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	123	MX6_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	124	MX6_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	125	MX6_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	126	MX6_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	127	MX6_PAD_SD3_DAT4__USDHC3_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	128	MX6_PAD_SD3_DAT5__USDHC3_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	129	MX6_PAD_SD3_DAT6__USDHC3_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	130	MX6_PAD_SD3_DAT7__USDHC3_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	131	MX6_PAD_GPIO_18__USDHC3_VSELECT \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	132	MX6_PAD_NANDF_CS2__GPIO_6_15 \| MUX_PAD_CTRL(NO_PAD_CTRL),
7dd6545d FE	133	};
	134
	135	static void setup_iomux_uart(void)
	136	{
	137	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
	138	}
	139
	140	#ifdef CONFIG_FSL_ESDHC
	141	struct fsl_esdhc_cfg usdhc_cfg[1] = {
	142	{USDHC3_BASE_ADDR},
	143	};
	144
	145	int board_mmc_getcd(struct mmc *mmc)
	146	{
	147	gpio_direction_input(IMX_GPIO_NR(6, 15));
	148	return !gpio_get_value(IMX_GPIO_NR(6, 15));
	149	}
	150
	151	int board_mmc_init(bd_t *bis)
	152	{
	153	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	154
a2ac1b3a	155	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
7dd6545d FE	156	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	157	}
	158	#endif
	159
fe5ebe97 FE	160	int mx6_rgmii_rework(struct phy_device *phydev)
	161	{
	162	unsigned short val;
	163
	164	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	165	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	166	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	167	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	168
	169	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	170	val &= 0xffe3;
	171	val \|= 0x18;
	172	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	173
	174	/* introduce tx clock delay */
	175	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	176	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	177	val \|= 0x0100;
	178	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	179
	180	return 0;
	181	}
	182
	183	int board_phy_config(struct phy_device *phydev)
	184	{
	185	mx6_rgmii_rework(phydev);
	186
	187	if (phydev->drv->config)
	188	phydev->drv->config(phydev);
	189
	190	return 0;
	191	}
	192
	193	int board_eth_init(bd_t *bis)
	194	{
	195	int ret;
	196
	197	setup_iomux_enet();
	198
	199	ret = cpu_eth_init(bis);
	200	if (ret)
	201	printf("FEC MXC: %s:failed\n", __func__);
	202
	203	return 0;
	204	}
	205
dce67bd5 FE	206	#define BOARD_REV_B 0x200
	207	#define BOARD_REV_A 0x100
	208
	209	static int mx6sabre_rev(void)
	210	{
	211	/*
	212	* Get Board ID information from OCOTP_GP1[15:8]
	213	* i.MX6Q ARD RevA: 0x01
	214	* i.MX6Q ARD RevB: 0x02
	215	*/
	216	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	217	struct fuse_bank *bank = &ocotp->bank[4];
	218	struct fuse_bank4_regs *fuse =
	219	(struct fuse_bank4_regs *)bank->fuse_regs;
	220	int reg = readl(&fuse->gp1);
dce67bd5 FE	221	int ret;
	222
	223	switch (reg >> 8 & 0x0F) {
	224	case 0x02:
	225	ret = BOARD_REV_B;
	226	break;
	227	case 0x01:
	228	default:
	229	ret = BOARD_REV_A;
	230	break;
	231	}
	232
	233	return ret;
	234	}
	235
7dd6545d FE	236	u32 get_board_rev(void)
7dd6545d FE	237	{
dce67bd5 FE	238	int rev = mx6sabre_rev();
	239
	240	return (get_cpu_rev() & ~(0xF << 8)) \| rev;
7dd6545d FE	241	}
	242
	243	int board_early_init_f(void)
	244	{
	245	setup_iomux_uart();
	246
	247	return 0;
	248	}
	249
	250	int board_init(void)
	251	{
	252	/* address of boot parameters */
	253	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	254
19578165 RF	255	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
	256	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	257	/* I2C 3 Steer */
	258	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
	259	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
	260	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	261
a1f67807 RF	262	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
	263	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
	264
7dd6545d FE	265	return 0;
	266	}
	267
85449dbd OS	268	#ifdef CONFIG_CMD_BMODE
	269	static const struct boot_mode board_boot_modes[] = {
	270	/* 4 bit bus width */
	271	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	272	{NULL, 0},
	273	};
	274	#endif
	275
	276	int board_late_init(void)
	277	{
	278	#ifdef CONFIG_CMD_BMODE
	279	add_board_boot_modes(board_boot_modes);
	280	#endif
	281
	282	return 0;
	283	}
	284
7dd6545d FE	285	int checkboard(void)
7dd6545d FE	286	{
dce67bd5 FE	287	int rev = mx6sabre_rev();
	288	char *revname;
	289
	290	switch (rev) {
	291	case BOARD_REV_B:
	292	revname = "B";
	293	break;
	294	case BOARD_REV_A:
	295	default:
	296	revname = "A";
	297	break;
	298	}
	299
	300	printf("Board: MX6Q-Sabreauto rev%s\n", revname);
7dd6545d FE	301
	302	return 0;
	303	}