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[people/ms/u-boot.git] / board / freescale / mx6qsabreauto / mx6qsabreauto.c
CommitLineData
7dd6545d
FE		 1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
7dd6545d
FE		 7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
b47abc36 14#include <asm/arch/mx6-pins.h>
1221ce45 15#include <linux/errno.h>
7dd6545d
FE		 16#include <asm/gpio.h>
17#include <asm/imx-common/iomux-v3.h>
19578165 18#include <asm/imx-common/mxc_i2c.h>
85449dbd 19#include <asm/imx-common/boot_mode.h>
3acb011c 20#include <asm/imx-common/spi.h>
7dd6545d
FE		 21#include <mmc.h>
22#include <fsl_esdhc.h>
fe5ebe97
FE		 23#include <miiphy.h>
24#include <netdev.h>
dce67bd5 25#include <asm/arch/sys_proto.h>
19578165 26#include <i2c.h>
510922ac
FE		 27#include <asm/arch/mxc_hdmi.h>
28#include <asm/imx-common/video.h>
29#include <asm/arch/crm_regs.h>
8fe280f3 30#include <pca953x.h>
593243d3 31#include <power/pmic.h>
258c98f8 32#include <power/pfuze100_pmic.h>
593243d3 33#include "../common/pfuze.h"
dce67bd5 34
7dd6545d
FE		 35DECLARE_GLOBAL_DATA_PTR;
36
7e2173cf
BT		 37#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
7dd6545d 40
7e2173cf
BT		 41#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
7dd6545d 44
7e2173cf
BT		 45#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
fe5ebe97 47
19578165
RF		 48#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
83bb3215
YL		 52#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
53#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
54 PAD_CTL_SRE_FAST)
55#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
56
19578165
RF		 57#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
58
cdbdde3f
FE		 59#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
593243d3
YL		 63#define I2C_PMIC 1
64
7dd6545d
FE		 65int dram_init(void)
66{
369012e7 67 gd->ram_size = imx_ddr_size();
7dd6545d
FE		 68
69 return 0;
70}
71
067a6593 72static iomux_v3_cfg_t const uart4_pads[] = {
10fda487
EN		 73 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
7dd6545d
FE		 75};
76
067a6593 77static iomux_v3_cfg_t const enet_pads[] = {
cfb8b9d3
EN		 78 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
10fda487
EN		 80 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
cfb8b9d3
EN		 85 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
10fda487
EN		 87 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
cfb8b9d3 92 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
fe5ebe97
FE		 93};
94
19578165 95/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
067a6593 96static struct i2c_pads_info i2c_pad_info1 = {
19578165
RF		 97 .scl = {
98 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
10fda487 99 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
19578165
RF		 100 .gp = IMX_GPIO_NR(2, 30)
101 },
102 .sda = {
103 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
10fda487 104 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
19578165
RF		 105 .gp = IMX_GPIO_NR(4, 13)
106 }
107};
108
cdbdde3f 109#ifndef CONFIG_SYS_FLASH_CFI
19578165
RF		 110/*
111 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
112 * Compass Sensor, Accelerometer, Res Touch
113 */
067a6593 114static struct i2c_pads_info i2c_pad_info2 = {
19578165
RF		 115 .scl = {
116 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
10fda487 117 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
19578165
RF		 118 .gp = IMX_GPIO_NR(1, 3)
119 },
120 .sda = {
121 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
10fda487 122 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
19578165
RF		 123 .gp = IMX_GPIO_NR(3, 18)
124 }
125};
cdbdde3f 126#endif
19578165 127
067a6593 128static iomux_v3_cfg_t const i2c3_pads[] = {
10fda487 129 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
19578165
RF		 130};
131
067a6593 132static iomux_v3_cfg_t const port_exp[] = {
10fda487 133 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
a1f67807
RF		 134};
135
8fe280f3
YL		 136/*Define for building port exp gpio, pin starts from 0*/
137#define PORTEXP_IO_NR(chip, pin) \
138 ((chip << 5) + pin)
139
140/*Get the chip addr from a ioexp gpio*/
141#define PORTEXP_IO_TO_CHIP(gpio_nr) \
142 (gpio_nr >> 5)
143
144/*Get the pin number from a ioexp gpio*/
145#define PORTEXP_IO_TO_PIN(gpio_nr) \
146 (gpio_nr & 0x1f)
147
148static int port_exp_direction_output(unsigned gpio, int value)
149{
150 int ret;
151
152 i2c_set_bus_num(2);
153 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
154 if (ret)
155 return ret;
156
157 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
158 (1 << PORTEXP_IO_TO_PIN(gpio)),
159 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
160
161 if (ret)
162 return ret;
163
164 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
165 (1 << PORTEXP_IO_TO_PIN(gpio)),
166 (value << PORTEXP_IO_TO_PIN(gpio)));
167
168 if (ret)
169 return ret;
170
171 return 0;
172}
173
cdbdde3f
FE		 174static iomux_v3_cfg_t const eimnor_pads[] = {
175 MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
176 MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
177 MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
178 MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
179 MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
180 MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
181 MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
182 MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
183 MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
184 MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
185 MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
186 MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
187 MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
188 MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
189 MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
190 MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
191 MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
192 MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
193 MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
194 MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
195 MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
196 MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
197 MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
198 MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
199 MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
200 MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
201 MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
202 MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
203 MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
204 MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
205 MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
206 MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
207 MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
208 MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
209 MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
210 MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
211 MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
212 MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
213 MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
214 MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
215 MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
216 MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
217 MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
218};
219
220static void eimnor_cs_setup(void)
221{
222 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
223
224 writel(0x00020181, &weim_regs->cs0gcr1);
225 writel(0x00000001, &weim_regs->cs0gcr2);
226 writel(0x0a020000, &weim_regs->cs0rcr1);
227 writel(0x0000c000, &weim_regs->cs0rcr2);
228 writel(0x0804a240, &weim_regs->cs0wcr1);
229 writel(0x00000120, &weim_regs->wcr);
230
231 set_chipselect_size(CS0_128);
232}
233
cfb37772
FE		 234static void eim_clk_setup(void)
235{
236 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
237 int cscmr1, ccgr6;
238
239
240 /* Turn off EIM clock */
241 ccgr6 = readl(&imx_ccm->CCGR6);
242 ccgr6 &= ~(0x3 << 10);
243 writel(ccgr6, &imx_ccm->CCGR6);
244
245 /*
246 * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
247 * and aclk_eim_slow_podf = 01 --> divide by 2
248 * so that we can have EIM at the maximum clock of 132MHz
249 */
250 cscmr1 = readl(&imx_ccm->cscmr1);
251 cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
252 MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
253 cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
254 writel(cscmr1, &imx_ccm->cscmr1);
255
256 /* Turn on EIM clock */
257 ccgr6 |= (0x3 << 10);
258 writel(ccgr6, &imx_ccm->CCGR6);
259}
260
cdbdde3f
FE		 261static void setup_iomux_eimnor(void)
262{
263 imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
264
265 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
266
267 eimnor_cs_setup();
268}
269
fe5ebe97
FE		 270static void setup_iomux_enet(void)
271{
272 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
273}
274
067a6593 275static iomux_v3_cfg_t const usdhc3_pads[] = {
10fda487
EN		 276 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
277 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
278 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
279 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
280 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
281 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
282 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
283 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
284 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
285 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
286 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
287 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
7dd6545d
FE		 288};
289
290static void setup_iomux_uart(void)
291{
292 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
293}
294
295#ifdef CONFIG_FSL_ESDHC
067a6593 296static struct fsl_esdhc_cfg usdhc_cfg[1] = {
7dd6545d
FE		 297 {USDHC3_BASE_ADDR},
298};
299
300int board_mmc_getcd(struct mmc *mmc)
301{
302 gpio_direction_input(IMX_GPIO_NR(6, 15));
303 return !gpio_get_value(IMX_GPIO_NR(6, 15));
304}
305
306int board_mmc_init(bd_t *bis)
307{
308 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
309
a2ac1b3a 310 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
7dd6545d
FE		 311 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
312}
313#endif
314
83bb3215
YL		 315#ifdef CONFIG_NAND_MXS
316static iomux_v3_cfg_t gpmi_pads[] = {
317 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
318 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
319 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
320 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
321 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
322 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
323 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
324 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
325 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
326 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
327 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
328 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
329 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
330 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
331 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
332 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
333};
334
335static void setup_gpmi_nand(void)
336{
337 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
338
339 /* config gpmi nand iomux */
340 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
341
5f22d88f 342 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
83bb3215 343 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
5f22d88f 344 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
83bb3215
YL		 345
346 /* enable apbh clock gating */
347 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
348}
349#endif
350
361b715b 351static void setup_fec(void)
fe5ebe97 352{
361b715b
PF		 353 if (is_mx6dqp()) {
354 /*
355 * select ENET MAC0 TX clock from PLL
356 */
357 imx_iomux_set_gpr_register(5, 9, 1, 1);
6d97dc10 358 enable_fec_anatop_clock(0, ENET_125MHZ);
361b715b
PF		 359 }
360
fe5ebe97 361 setup_iomux_enet();
361b715b
PF		 362}
363
364int board_eth_init(bd_t *bis)
365{
366 setup_fec();
fe5ebe97 367
579be2f7 368 return cpu_eth_init(bis);
fe5ebe97
FE		 369}
370
dce67bd5
FE		 371#define BOARD_REV_B 0x200
372#define BOARD_REV_A 0x100
373
374static int mx6sabre_rev(void)
375{
376 /*
377 * Get Board ID information from OCOTP_GP1[15:8]
378 * i.MX6Q ARD RevA: 0x01
379 * i.MX6Q ARD RevB: 0x02
380 */
381 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
8f3ff11c
BT		 382 struct fuse_bank *bank = &ocotp->bank[4];
383 struct fuse_bank4_regs *fuse =
384 (struct fuse_bank4_regs *)bank->fuse_regs;
385 int reg = readl(&fuse->gp1);
dce67bd5
FE		 386 int ret;
387
388 switch (reg >> 8 & 0x0F) {
389 case 0x02:
390 ret = BOARD_REV_B;
391 break;
392 case 0x01:
393 default:
394 ret = BOARD_REV_A;
395 break;
396 }
397
398 return ret;
399}
400
7dd6545d
FE		 401u32 get_board_rev(void)
402{
dce67bd5
FE		 403 int rev = mx6sabre_rev();
404
405 return (get_cpu_rev() & ~(0xF << 8)) | rev;
7dd6545d
FE		 406}
407
510922ac 408#if defined(CONFIG_VIDEO_IPUV3)
ccf4326b
PF		 409static void disable_lvds(struct display_info_t const *dev)
410{
411 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
412
413 clrbits_le32(&iomux->gpr[2],
414 IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
415 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
416}
417
510922ac
FE		 418static void do_enable_hdmi(struct display_info_t const *dev)
419{
ccf4326b 420 disable_lvds(dev);
510922ac
FE		 421 imx_enable_hdmi_phy();
422}
423
424struct display_info_t const displays[] = {{
ccf4326b
PF		 425 .bus = -1,
426 .addr = 0,
427 .pixfmt = IPU_PIX_FMT_RGB666,
428 .detect = NULL,
429 .enable = NULL,
430 .mode = {
431 .name = "Hannstar-XGA",
432 .refresh = 60,
433 .xres = 1024,
434 .yres = 768,
435 .pixclock = 15385,
436 .left_margin = 220,
437 .right_margin = 40,
438 .upper_margin = 21,
439 .lower_margin = 7,
440 .hsync_len = 60,
441 .vsync_len = 10,
442 .sync = FB_SYNC_EXT,
443 .vmode = FB_VMODE_NONINTERLACED
444} }, {
510922ac
FE		 445 .bus = -1,
446 .addr = 0,
447 .pixfmt = IPU_PIX_FMT_RGB24,
448 .detect = detect_hdmi,
449 .enable = do_enable_hdmi,
450 .mode = {
451 .name = "HDMI",
452 .refresh = 60,
453 .xres = 1024,
454 .yres = 768,
455 .pixclock = 15385,
456 .left_margin = 220,
457 .right_margin = 40,
458 .upper_margin = 21,
459 .lower_margin = 7,
460 .hsync_len = 60,
461 .vsync_len = 10,
462 .sync = FB_SYNC_EXT,
463 .vmode = FB_VMODE_NONINTERLACED,
464} } };
465size_t display_count = ARRAY_SIZE(displays);
466
ccf4326b
PF		 467iomux_v3_cfg_t const backlight_pads[] = {
468 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
469};
470
471static void setup_iomux_backlight(void)
472{
473 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
474 imx_iomux_v3_setup_multiple_pads(backlight_pads,
475 ARRAY_SIZE(backlight_pads));
476}
477
510922ac
FE		 478static void setup_display(void)
479{
480 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
ccf4326b 481 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
510922ac
FE		 482 int reg;
483
ccf4326b 484 setup_iomux_backlight();
510922ac
FE		 485 enable_ipu_clock();
486 imx_setup_hdmi();
487
ccf4326b
PF		 488 /* Turn on LDB_DI0 and LDB_DI1 clocks */
489 reg = readl(&mxc_ccm->CCGR3);
490 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
491 writel(reg, &mxc_ccm->CCGR3);
492
493 /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
494 reg = readl(&mxc_ccm->cs2cdr);
495 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
496 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
497 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
498 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
499 writel(reg, &mxc_ccm->cs2cdr);
500
501 reg = readl(&mxc_ccm->cscmr2);
502 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
503 writel(reg, &mxc_ccm->cscmr2);
504
510922ac
FE		 505 reg = readl(&mxc_ccm->chsccdr);
506 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
507 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
ccf4326b
PF		 508 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
509 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
510922ac 510 writel(reg, &mxc_ccm->chsccdr);
ccf4326b
PF		 511
512 reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
513 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
514 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
515 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
516 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
517 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
518 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
519 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
520 writel(reg, &iomux->gpr[2]);
521
522 reg = readl(&iomux->gpr[3]);
523 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
524 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
525 reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
526 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
527 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
528 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
529 writel(reg, &iomux->gpr[3]);
510922ac
FE		 530}
531#endif /* CONFIG_VIDEO_IPUV3 */
532
533/*
534 * Do not overwrite the console
535 * Use always serial for U-Boot console
536 */
537int overwrite_console(void)
538{
539 return 1;
540}
541
7dd6545d
FE		 542int board_early_init_f(void)
543{
544 setup_iomux_uart();
83bb3215
YL		 545
546#ifdef CONFIG_NAND_MXS
547 setup_gpmi_nand();
548#endif
cfb37772 549 eim_clk_setup();
cdbdde3f 550
7dd6545d
FE		 551 return 0;
552}
553
554int board_init(void)
555{
556 /* address of boot parameters */
557 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
558
19578165
RF		 559 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
560 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
561 /* I2C 3 Steer */
562 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
563 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
cdbdde3f 564#ifndef CONFIG_SYS_FLASH_CFI
19578165 565 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
cdbdde3f 566#endif
a1f67807
RF		 567 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
568 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
569
ccf4326b
PF		 570#ifdef CONFIG_VIDEO_IPUV3
571 setup_display();
572#endif
cdbdde3f 573 setup_iomux_eimnor();
7dd6545d
FE		 574 return 0;
575}
576
155fa9af
NK		 577#ifdef CONFIG_MXC_SPI
578int board_spi_cs_gpio(unsigned bus, unsigned cs)
579{
580 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
581}
582#endif
583
593243d3
YL		 584int power_init_board(void)
585{
586 struct pmic *p;
361b715b 587 unsigned int value;
593243d3
YL		 588
589 p = pfuze_common_init(I2C_PMIC);
590 if (!p)
591 return -ENODEV;
592
361b715b
PF		 593 if (is_mx6dqp()) {
594 /* set SW2 staby volatage 0.975V*/
595 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
596 value &= ~0x3f;
597 value |= 0x17;
598 pmic_reg_write(p, PFUZE100_SW2STBY, value);
599 }
258c98f8 600
361b715b 601 return pfuze_mode_init(p, APS_PFM);
593243d3
YL		 602}
603
85449dbd
OS		 604#ifdef CONFIG_CMD_BMODE
605static const struct boot_mode board_boot_modes[] = {
606 /* 4 bit bus width */
607 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
608 {NULL, 0},
609};
610#endif
611
612int board_late_init(void)
613{
614#ifdef CONFIG_CMD_BMODE
615 add_board_boot_modes(board_boot_modes);
616#endif
617
e6fc8995
PF		 618#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
619 setenv("board_name", "SABREAUTO");
620
361b715b
PF		 621 if (is_mx6dqp())
622 setenv("board_rev", "MX6QP");
83e13942 623 else if (is_mx6dq())
e6fc8995 624 setenv("board_rev", "MX6Q");
83e13942 625 else if (is_mx6sdl())
e6fc8995
PF		 626 setenv("board_rev", "MX6DL");
627#endif
628
85449dbd
OS		 629 return 0;
630}
631
7dd6545d
FE		 632int checkboard(void)
633{
dce67bd5
FE		 634 int rev = mx6sabre_rev();
635 char *revname;
636
637 switch (rev) {
638 case BOARD_REV_B:
639 revname = "B";
640 break;
641 case BOARD_REV_A:
642 default:
643 revname = "A";
644 break;
645 }
646
647 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
7dd6545d
FE		 648
649 return 0;
650}
8fe280f3
YL		 651
652#ifdef CONFIG_USB_EHCI_MX6
653#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
654#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
655
656iomux_v3_cfg_t const usb_otg_pads[] = {
657 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
658};
659
660int board_ehci_hcd_init(int port)
661{
662 switch (port) {
663 case 0:
664 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
665 ARRAY_SIZE(usb_otg_pads));
666
667 /*
668 * Set daisy chain for otg_pin_id on 6q.
669 * For 6dl, this bit is reserved.
670 */
671 imx_iomux_set_gpr_register(1, 13, 1, 0);
672 break;
673 case 1:
674 break;
675 default:
676 printf("MXC USB port %d not yet supported\n", port);
677 return -EINVAL;
678 }
679 return 0;
680}
681
682int board_ehci_power(int port, int on)
683{
684 switch (port) {
685 case 0:
686 if (on)
687 port_exp_direction_output(USB_OTG_PWR, 1);
688 else
689 port_exp_direction_output(USB_OTG_PWR, 0);
690 break;
691 case 1:
692 if (on)
693 port_exp_direction_output(USB_HOST1_PWR, 1);
694 else
695 port_exp_direction_output(USB_HOST1_PWR, 0);
696 break;
697 default:
698 printf("MXC USB port %d not yet supported\n", port);
699 return -EINVAL;
700 }
701
702 return 0;
703}
704#endif
"Das U-Boot" Source Tree