[people/ms/u-boot.git] / board / freescale / mx6qsabrelite / mx6qsabrelite.c

/*
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6x_pins.h>
#include <asm/arch/iomux-v3.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)

#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)

int dram_init(void)
{
       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

       return 0;
}

iomux_v3_cfg_t uart1_pads[] = {
	MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

iomux_v3_cfg_t uart2_pads[] = {
       MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
       MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

iomux_v3_cfg_t usdhc3_pads[] = {
       MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};

iomux_v3_cfg_t usdhc4_pads[] = {
       MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
       MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};

iomux_v3_cfg_t enet_pads1[] = {
	MX6Q_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	/* pin 35 - 1 (PHY_AD2) on reset */
	MX6Q_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
	/* pin 32 - 1 - (MODE0) all */
	MX6Q_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
	/* pin 31 - 1 - (MODE1) all */
	MX6Q_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
	/* pin 28 - 1 - (MODE2) all */
	MX6Q_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
	/* pin 27 - 1 - (MODE3) all */
	MX6Q_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
	MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24	| MUX_PAD_CTRL(NO_PAD_CTRL),
	/* pin 42 PHY nRST */
	MX6Q_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
};

iomux_v3_cfg_t enet_pads2[] = {
	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
};

static void setup_iomux_enet(void)
{
	gpio_direction_output(87, 0);  /* GPIO 3-23 */
	gpio_direction_output(190, 1); /* GPIO 6-30 */
	gpio_direction_output(185, 1); /* GPIO 6-25 */
	gpio_direction_output(187, 1); /* GPIO 6-27 */
	gpio_direction_output(188, 1); /* GPIO 6-28*/
	gpio_direction_output(189, 1); /* GPIO 6-29 */
	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
	gpio_direction_output(184, 1); /* GPIO 6-24 */

	/* Need delay 10ms according to KSZ9021 spec */
	udelay(1000 * 10);
	gpio_direction_output(87, 1);  /* GPIO 3-23 */

	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
}

iomux_v3_cfg_t usb_pads[] = {
	MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
       imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}

#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));

	/* Reset USB hub */
	gpio_direction_output(GPIO_NUMBER(7, 12), 0);
	mdelay(2);
	gpio_set_value(GPIO_NUMBER(7, 12), 1);

	return 0;
}
#endif

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
       {USDHC3_BASE_ADDR, 1},
       {USDHC4_BASE_ADDR, 1},
};

int board_mmc_getcd(struct mmc *mmc)
{
       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
       int ret;

       if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
               gpio_direction_input(192); /*GPIO7_0*/
               ret = !gpio_get_value(192);
       } else {
               gpio_direction_input(38); /*GPIO2_6*/
               ret = !gpio_get_value(38);
       }

       return ret;
}

int board_mmc_init(bd_t *bis)
{
       s32 status = 0;
       u32 index = 0;

       for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
               switch (index) {
               case 0:
                       imx_iomux_v3_setup_multiple_pads(
                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
                       break;
               case 1:
                       imx_iomux_v3_setup_multiple_pads(
                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
                       break;
               default:
                       printf("Warning: you configured more USDHC controllers"
                               "(%d) then supported by the board (%d)\n",
                               index + 1, CONFIG_SYS_FSL_USDHC_NUM);
                       return status;
               }

               status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
       }

       return status;
}
#endif

#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t ecspi1_pads[] = {
	/* SS1 */
	MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
};

void setup_spi(void)
{
	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
					 ARRAY_SIZE(ecspi1_pads));
}
#endif

int board_phy_config(struct phy_device *phydev)
{
	/* min rx data delay */
	ksz9021_phy_extended_write(phydev,
			MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
	/* min tx data delay */
	ksz9021_phy_extended_write(phydev,
			MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
	/* max rx/tx clock delay, min rx/tx control */
	ksz9021_phy_extended_write(phydev,
			MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
	if (phydev->drv->config)
		phydev->drv->config(phydev);
 
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int ret;

	setup_iomux_enet();

	ret = cpu_eth_init(bis);
	if (ret)
		printf("FEC MXC: %s:failed\n", __func__);

#ifdef CONFIG_MXC_SPI
	setup_spi();
#endif

	return 0;
}

int board_early_init_f(void)
{
       setup_iomux_uart();

       return 0;
}

int board_init(void)
{
       /* address of boot parameters */
       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

       return 0;
}

int checkboard(void)
{
       puts("Board: MX6Q-Sabre Lite\n");

       return 0;
}
Commit	Line	Data
bc5833c4 JL	1	/*
	2	* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <asm/io.h>
	25	#include <asm/arch/imx-regs.h>
	26	#include <asm/arch/mx6x_pins.h>
	27	#include <asm/arch/iomux-v3.h>
	28	#include <asm/errno.h>
	29	#include <asm/gpio.h>
	30	#include <mmc.h>
	31	#include <fsl_esdhc.h>
2bf3359e	32	#include <micrel.h>
2af81e27 JL	33	#include <miiphy.h>
2af81e27 JL	34	#include <netdev.h>
bc5833c4 JL	35	DECLARE_GLOBAL_DATA_PTR;
	36
	37	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	38	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	39	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	40
	41	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	42	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	43	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	44
2af81e27 JL	45	#define ENET_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	46	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	47	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	48
373a1d8c EN	49	#define SPI_PAD_CTRL (PAD_CTL_HYS \| \
	50	PAD_CTL_PUS_100K_DOWN \| PAD_CTL_SPEED_MED \| \
	51	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	52
bc5833c4 JL	53	int dram_init(void)
	54	{
	55	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	56
	57	return 0;
	58	}
	59
8e7d7b6b TK	60	iomux_v3_cfg_t uart1_pads[] = {
	61	MX6Q_PAD_SD3_DAT6__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	62	MX6Q_PAD_SD3_DAT7__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	63	};
	64
bc5833c4 JL	65	iomux_v3_cfg_t uart2_pads[] = {
	66	MX6Q_PAD_EIM_D26__UART2_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	67	MX6Q_PAD_EIM_D27__UART2_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	68	};
	69
	70	iomux_v3_cfg_t usdhc3_pads[] = {
	71	MX6Q_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	72	MX6Q_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	73	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	74	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	75	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	76	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	77	MX6Q_PAD_SD3_DAT5__GPIO_7_0 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
	78	};
	79
	80	iomux_v3_cfg_t usdhc4_pads[] = {
	81	MX6Q_PAD_SD4_CLK__USDHC4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	82	MX6Q_PAD_SD4_CMD__USDHC4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	83	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	84	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	85	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	86	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	87	MX6Q_PAD_NANDF_D6__GPIO_2_6 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
	88	};
	89
2af81e27 JL	90	iomux_v3_cfg_t enet_pads1[] = {
	91	MX6Q_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	92	MX6Q_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	93	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	94	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	95	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	96	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	97	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	98	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	99	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	100	/* pin 35 - 1 (PHY_AD2) on reset */
	101	MX6Q_PAD_RGMII_RXC__GPIO_6_30 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	102	/* pin 32 - 1 - (MODE0) all */
	103	MX6Q_PAD_RGMII_RD0__GPIO_6_25 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	104	/* pin 31 - 1 - (MODE1) all */
	105	MX6Q_PAD_RGMII_RD1__GPIO_6_27 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	106	/* pin 28 - 1 - (MODE2) all */
	107	MX6Q_PAD_RGMII_RD2__GPIO_6_28 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	108	/* pin 27 - 1 - (MODE3) all */
	109	MX6Q_PAD_RGMII_RD3__GPIO_6_29 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	110	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
	111	MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	112	/* pin 42 PHY nRST */
	113	MX6Q_PAD_EIM_D23__GPIO_3_23 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	114	};
	115
	116	iomux_v3_cfg_t enet_pads2[] = {
	117	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	118	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	119	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	120	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	121	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	122	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	123	};
	124
	125	static void setup_iomux_enet(void)
	126	{
	127	gpio_direction_output(87, 0); /* GPIO 3-23 */
	128	gpio_direction_output(190, 1); /* GPIO 6-30 */
	129	gpio_direction_output(185, 1); /* GPIO 6-25 */
	130	gpio_direction_output(187, 1); /* GPIO 6-27 */
	131	gpio_direction_output(188, 1); /* GPIO 6-28*/
	132	gpio_direction_output(189, 1); /* GPIO 6-29 */
	133	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
	134	gpio_direction_output(184, 1); /* GPIO 6-24 */
	135
	136	/* Need delay 10ms according to KSZ9021 spec */
	137	udelay(1000 * 10);
	138	gpio_direction_output(87, 1); /* GPIO 3-23 */
	139
	140	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
	141	}
	142
2ea73e9e WG	143	iomux_v3_cfg_t usb_pads[] = {
	144	MX6Q_PAD_GPIO_17__GPIO_7_12 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	145	};
	146
bc5833c4 JL	147	static void setup_iomux_uart(void)
bc5833c4 JL	148	{
8e7d7b6b	149	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
bc5833c4 JL	150	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
	151	}
	152
2ea73e9e WG	153	#ifdef CONFIG_USB_EHCI_MX6
	154	int board_ehci_hcd_init(int port)
	155	{
	156	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
	157
	158	/* Reset USB hub */
	159	gpio_direction_output(GPIO_NUMBER(7, 12), 0);
	160	mdelay(2);
	161	gpio_set_value(GPIO_NUMBER(7, 12), 1);
	162
	163	return 0;
	164	}
	165	#endif
	166
bc5833c4 JL	167	#ifdef CONFIG_FSL_ESDHC
	168	struct fsl_esdhc_cfg usdhc_cfg[2] = {
	169	{USDHC3_BASE_ADDR, 1},
	170	{USDHC4_BASE_ADDR, 1},
	171	};
	172
	173	int board_mmc_getcd(struct mmc *mmc)
	174	{
	175	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	176	int ret;
	177
	178	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
	179	gpio_direction_input(192); /GPIO7_0/
	180	ret = !gpio_get_value(192);
	181	} else {
	182	gpio_direction_input(38); /GPIO2_6/
	183	ret = !gpio_get_value(38);
	184	}
	185
	186	return ret;
	187	}
	188
	189	int board_mmc_init(bd_t *bis)
	190	{
	191	s32 status = 0;
	192	u32 index = 0;
	193
	194	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
	195	switch (index) {
	196	case 0:
	197	imx_iomux_v3_setup_multiple_pads(
	198	usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	199	break;
	200	case 1:
	201	imx_iomux_v3_setup_multiple_pads(
	202	usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
	203	break;
	204	default:
	205	printf("Warning: you configured more USDHC controllers"
	206	"(%d) then supported by the board (%d)\n",
	207	index + 1, CONFIG_SYS_FSL_USDHC_NUM);
	208	return status;
	209	}
	210
	211	status \|= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
	212	}
	213
	214	return status;
	215	}
	216	#endif
	217
373a1d8c EN	218	#ifdef CONFIG_MXC_SPI
	219	iomux_v3_cfg_t ecspi1_pads[] = {
	220	/* SS1 */
	221	MX6Q_PAD_EIM_D19__GPIO_3_19 \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	222	MX6Q_PAD_EIM_D17__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	223	MX6Q_PAD_EIM_D18__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	224	MX6Q_PAD_EIM_D16__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	225	};
	226
	227	void setup_spi(void)
	228	{
ba54b927	229	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
373a1d8c EN	230	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
	231	ARRAY_SIZE(ecspi1_pads));
	232	}
	233	#endif
	234
2bf3359e	235	int board_phy_config(struct phy_device *phydev)
2af81e27	236	{
2af81e27	237	/* min rx data delay */
2bf3359e TK	238	ksz9021_phy_extended_write(phydev,
	239	MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
	240	/* min tx data delay */
	241	ksz9021_phy_extended_write(phydev,
	242	MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
	243	/* max rx/tx clock delay, min rx/tx control */
	244	ksz9021_phy_extended_write(phydev,
	245	MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
	246	if (phydev->drv->config)
	247	phydev->drv->config(phydev);
	248
2af81e27 JL	249	return 0;
	250	}
	251
	252	int board_eth_init(bd_t *bis)
	253	{
2af81e27 JL	254	int ret;
	255
	256	setup_iomux_enet();
	257
	258	ret = cpu_eth_init(bis);
2bf3359e	259	if (ret)
2af81e27	260	printf("FEC MXC: %s:failed\n", __func__);
2af81e27	261
373a1d8c EN	262	#ifdef CONFIG_MXC_SPI
	263	setup_spi();
	264	#endif
	265
2af81e27 JL	266	return 0;
	267	}
	268
bc5833c4 JL	269	int board_early_init_f(void)
	270	{
	271	setup_iomux_uart();
	272
	273	return 0;
	274	}
	275
	276	int board_init(void)
	277	{
	278	/* address of boot parameters */
	279	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	280
	281	return 0;
	282	}
	283
	284	int checkboard(void)
	285	{
	286	puts("Board: MX6Q-Sabre Lite\n");
	287
	288	return 0;
	289	}