[people/ms/u-boot.git] / board / freescale / mx6sabresd / mx6sabresd.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

	return 0;
}

iomux_v3_cfg_t const uart1_pads[] = {
	MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

iomux_v3_cfg_t const enet_pads[] = {
	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	/* AR8031 PHY Reset */
	MX6_PAD_ENET_CRS_DV__GPIO_1_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

	/* Reset AR8031 PHY */
	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
	udelay(500);
	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}

iomux_v3_cfg_t const usdhc2_pads[] = {
	MX6_PAD_SD2_CLK__USDHC2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_CMD__USDHC2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT0__USDHC2_DAT0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT1__USDHC2_DAT1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT2__USDHC2_DAT2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT3__USDHC2_DAT3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_D4__USDHC2_DAT4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_D5__USDHC2_DAT5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_D6__USDHC2_DAT6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_D7__USDHC2_DAT7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_D2__GPIO_2_2	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};

iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};

iomux_v3_cfg_t const usdhc4_pads[] = {
	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[3] = {
	{USDHC2_BASE_ADDR},
	{USDHC3_BASE_ADDR},
	{USDHC4_BASE_ADDR},
};

#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		ret = !gpio_get_value(USDHC3_CD_GPIO);
		break;
	case USDHC4_BASE_ADDR:
		ret = 1; /* eMMC/uSDHC4 is always present */
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	s32 status = 0;
	int i;

	/*
	 * According to the board_mmc_init() the following map is done:
	 * (U-boot device node)    (Physical Port)
	 * mmc0                    SD2
	 * mmc1                    SD3
	 * mmc2                    eMMC
	 */
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
			gpio_direction_input(USDHC2_CD_GPIO);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
			gpio_direction_input(USDHC3_CD_GPIO);
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			break;
		case 2:
			imx_iomux_v3_setup_multiple_pads(
				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
			break;
		default:
			printf("Warning: you configured more USDHC controllers"
			       "(%d) then supported by the board (%d)\n",
			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
			return status;
		}

		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	}

	return status;
}
#endif

int mx6_rgmii_rework(struct phy_device *phydev)
{
	unsigned short val;

	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* introduce tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	val |= 0x0100;
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	int ret;

	setup_iomux_enet();

	ret = cpu_eth_init(bis);
	if (ret)
		printf("FEC MXC: %s:failed\n", __func__);

	return 0;
}

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	/* 8 bit bus width */
	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: MX6-SabreSD\n");
	return 0;
}
Commit	Line	Data
7891e258 FE	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
7891e258 FE	7	*/
7891e258 FE	8
7891e258 FE	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/imx-regs.h>
	11	#include <asm/arch/iomux.h>
c1747970	12	#include <asm/arch/mx6-pins.h>
7891e258 FE	13	#include <asm/errno.h>
	14	#include <asm/gpio.h>
	15	#include <asm/imx-common/iomux-v3.h>
85449dbd	16	#include <asm/imx-common/boot_mode.h>
7891e258 FE	17	#include <mmc.h>
	18	#include <fsl_esdhc.h>
	19	#include <miiphy.h>
	20	#include <netdev.h>
85449dbd	21
7891e258 FE	22	DECLARE_GLOBAL_DATA_PTR;
7891e258 FE	23
7e2173cf BT	24	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	25	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	26	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
7891e258	27
7e2173cf BT	28	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	29	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	30	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
7891e258	31
7e2173cf BT	32	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
7e2173cf BT	33	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
7891e258 FE	34
	35	int dram_init(void)
	36	{
	37	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	38
	39	return 0;
	40	}
	41
6e142320	42	iomux_v3_cfg_t const uart1_pads[] = {
cfb8b9d3 EN	43	MX6_PAD_CSI0_DAT10__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
cfb8b9d3 EN	44	MX6_PAD_CSI0_DAT11__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
7891e258 FE	45	};
7891e258 FE	46
6e142320	47	iomux_v3_cfg_t const enet_pads[] = {
cfb8b9d3 EN	48	MX6_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	49	MX6_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	50	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	51	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	52	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	53	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	54	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	55	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	56	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	57	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	58	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	59	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	60	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	61	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	62	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
a0d21fc0	63	/* AR8031 PHY Reset */
cfb8b9d3	64	MX6_PAD_ENET_CRS_DV__GPIO_1_25 \| MUX_PAD_CTRL(NO_PAD_CTRL),
a0d21fc0 FE	65	};
	66
	67	static void setup_iomux_enet(void)
	68	{
	69	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	70
	71	/* Reset AR8031 PHY */
	72	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
	73	udelay(500);
	74	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
	75	}
	76
de7d02ae	77	iomux_v3_cfg_t const usdhc2_pads[] = {
cfb8b9d3 EN	78	MX6_PAD_SD2_CLK__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	79	MX6_PAD_SD2_CMD__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	80	MX6_PAD_SD2_DAT0__USDHC2_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	81	MX6_PAD_SD2_DAT1__USDHC2_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	82	MX6_PAD_SD2_DAT2__USDHC2_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	83	MX6_PAD_SD2_DAT3__USDHC2_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	84	MX6_PAD_NANDF_D4__USDHC2_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	85	MX6_PAD_NANDF_D5__USDHC2_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	86	MX6_PAD_NANDF_D6__USDHC2_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	87	MX6_PAD_NANDF_D7__USDHC2_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	88	MX6_PAD_NANDF_D2__GPIO_2_2 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
de7d02ae SG	89	};
de7d02ae SG	90
6e142320	91	iomux_v3_cfg_t const usdhc3_pads[] = {
cfb8b9d3 EN	92	MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	93	MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	94	MX6_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	95	MX6_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	96	MX6_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	97	MX6_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	98	MX6_PAD_SD3_DAT4__USDHC3_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	99	MX6_PAD_SD3_DAT5__USDHC3_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	100	MX6_PAD_SD3_DAT6__USDHC3_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	101	MX6_PAD_SD3_DAT7__USDHC3_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	102	MX6_PAD_NANDF_D0__GPIO_2_0 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
7891e258 FE	103	};
7891e258 FE	104
de7d02ae	105	iomux_v3_cfg_t const usdhc4_pads[] = {
cfb8b9d3 EN	106	MX6_PAD_SD4_CLK__USDHC4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	107	MX6_PAD_SD4_CMD__USDHC4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	108	MX6_PAD_SD4_DAT0__USDHC4_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	109	MX6_PAD_SD4_DAT1__USDHC4_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	110	MX6_PAD_SD4_DAT2__USDHC4_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	111	MX6_PAD_SD4_DAT3__USDHC4_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	112	MX6_PAD_SD4_DAT4__USDHC4_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	113	MX6_PAD_SD4_DAT5__USDHC4_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	114	MX6_PAD_SD4_DAT6__USDHC4_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	115	MX6_PAD_SD4_DAT7__USDHC4_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
de7d02ae SG	116	};
de7d02ae SG	117
7891e258 FE	118	static void setup_iomux_uart(void)
	119	{
	120	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	121	}
	122
	123	#ifdef CONFIG_FSL_ESDHC
de7d02ae SG	124	struct fsl_esdhc_cfg usdhc_cfg[3] = {
de7d02ae SG	125	{USDHC2_BASE_ADDR},
7891e258	126	{USDHC3_BASE_ADDR},
de7d02ae	127	{USDHC4_BASE_ADDR},
7891e258 FE	128	};
7891e258 FE	129
de7d02ae SG	130	#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
	131	#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
	132
7891e258 FE	133	int board_mmc_getcd(struct mmc *mmc)
7891e258 FE	134	{
de7d02ae	135	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
60bb4621	136	int ret = 0;
de7d02ae SG	137
	138	switch (cfg->esdhc_base) {
	139	case USDHC2_BASE_ADDR:
60bb4621 OS	140	ret = !gpio_get_value(USDHC2_CD_GPIO);
60bb4621 OS	141	break;
de7d02ae	142	case USDHC3_BASE_ADDR:
60bb4621 OS	143	ret = !gpio_get_value(USDHC3_CD_GPIO);
	144	break;
	145	case USDHC4_BASE_ADDR:
	146	ret = 1; /* eMMC/uSDHC4 is always present */
	147	break;
de7d02ae	148	}
60bb4621 OS	149
60bb4621 OS	150	return ret;
7891e258 FE	151	}
	152
	153	int board_mmc_init(bd_t *bis)
	154	{
f07e286c	155	s32 status = 0;
de7d02ae SG	156	int i;
de7d02ae SG	157
28ff917c OS	158	/*
	159	* According to the board_mmc_init() the following map is done:
	160	* (U-boot device node) (Physical Port)
	161	* mmc0 SD2
	162	* mmc1 SD3
	163	* mmc2 eMMC
	164	*/
de7d02ae SG	165	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	166	switch (i) {
	167	case 0:
	168	imx_iomux_v3_setup_multiple_pads(
	169	usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
	170	gpio_direction_input(USDHC2_CD_GPIO);
	171	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	172	break;
	173	case 1:
	174	imx_iomux_v3_setup_multiple_pads(
	175	usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	176	gpio_direction_input(USDHC3_CD_GPIO);
	177	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	178	break;
	179	case 2:
	180	imx_iomux_v3_setup_multiple_pads(
	181	usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
	182	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	183	break;
	184	default:
	185	printf("Warning: you configured more USDHC controllers"
f07e286c OS	186	"(%d) then supported by the board (%d)\n",
	187	i + 1, CONFIG_SYS_FSL_USDHC_NUM);
	188	return status;
	189	}
de7d02ae	190
f07e286c	191	status \|= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
de7d02ae	192	}
7891e258	193
f07e286c	194	return status;
7891e258 FE	195	}
	196	#endif
	197
a0d21fc0 FE	198	int mx6_rgmii_rework(struct phy_device *phydev)
	199	{
	200	unsigned short val;
	201
	202	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	203	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	204	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	205	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	206
	207	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	208	val &= 0xffe3;
	209	val \|= 0x18;
	210	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	211
	212	/* introduce tx clock delay */
	213	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	214	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	215	val \|= 0x0100;
	216	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	217
	218	return 0;
	219	}
	220
	221	int board_phy_config(struct phy_device *phydev)
	222	{
	223	mx6_rgmii_rework(phydev);
	224
	225	if (phydev->drv->config)
	226	phydev->drv->config(phydev);
	227
	228	return 0;
	229	}
	230
	231	int board_eth_init(bd_t *bis)
	232	{
	233	int ret;
	234
	235	setup_iomux_enet();
	236
	237	ret = cpu_eth_init(bis);
	238	if (ret)
	239	printf("FEC MXC: %s:failed\n", __func__);
	240
	241	return 0;
	242	}
	243
7891e258 FE	244	int board_early_init_f(void)
	245	{
	246	setup_iomux_uart();
	247
	248	return 0;
	249	}
	250
	251	int board_init(void)
	252	{
	253	/* address of boot parameters */
	254	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	255
	256	return 0;
	257	}
	258
85449dbd OS	259	#ifdef CONFIG_CMD_BMODE
	260	static const struct boot_mode board_boot_modes[] = {
	261	/* 4 bit bus width */
	262	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	263	{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	264	/* 8 bit bus width */
	265	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	266	{NULL, 0},
	267	};
	268	#endif
	269
	270	int board_late_init(void)
	271	{
	272	#ifdef CONFIG_CMD_BMODE
	273	add_board_boot_modes(board_boot_modes);
	274	#endif
	275
	276	return 0;
	277	}
	278
7891e258 FE	279	int checkboard(void)
7891e258 FE	280	{
c1747970	281	puts("Board: MX6-SabreSD\n");
7891e258 FE	282	return 0;
7891e258 FE	283	}