[people/ms/u-boot.git] / board / freescale / mx6slevk / mx6slevk.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <mmc.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)

#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)

#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
			PAD_CTL_SRE_FAST)

#define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const uart1_pads[] = {
	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc1_pads[] = {
	/* 8 bit SD */
	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/*CD pin*/
	MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc2_pads[] = {
	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/*CD pin*/
	MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/*CD pin*/
	MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const fec_pads[] = {
	MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

#ifdef CONFIG_MXC_SPI
static iomux_v3_cfg_t ecspi1_pads[] = {
	MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
};

int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
}

static void setup_spi(void)
{
	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
#endif

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

static void setup_iomux_fec(void)
{
	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));

	/* Power up LAN8720 PHY */
	gpio_direction_output(ETH_PHY_POWER , 1);
	udelay(15000);
}

#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)

static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	{USDHC1_BASE_ADDR},
	{USDHC2_BASE_ADDR, 0, 4},
	{USDHC3_BASE_ADDR, 0, 4},
};

int board_mmc_get_env_dev(int devno)
{
	return devno;
}

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		ret = !gpio_get_value(USDHC3_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
	int i, ret;

	/*
	 * According to the board_mmc_init() the following map is done:
	 * (U-Boot device node)    (Physical Port)
	 * mmc0                    USDHC1
	 * mmc1                    USDHC2
	 * mmc2                    USDHC3
	 */
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
			gpio_direction_input(USDHC1_CD_GPIO);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
			gpio_direction_input(USDHC2_CD_GPIO);
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
			break;
		case 2:
			imx_iomux_v3_setup_multiple_pads(
				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
			gpio_direction_input(USDHC3_CD_GPIO);
			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			break;
		default:
			printf("Warning: you configured more USDHC controllers"
				"(%d) than supported by the board\n", i + 1);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize "
				"mmc dev %d\n", i);
			return ret;
		}
	}

	return 0;
#else
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
	u32 val;
	u32 port;

	val = readl(&src_regs->sbmr1);

	/* Boot from USDHC */
	port = (val >> 11) & 0x3;
	switch (port) {
	case 0:
		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
						 ARRAY_SIZE(usdhc1_pads));
		gpio_direction_input(USDHC1_CD_GPIO);
		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
		break;
	case 1:
		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
						 ARRAY_SIZE(usdhc2_pads));
		gpio_direction_input(USDHC2_CD_GPIO);
		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
		usdhc_cfg[0].max_bus_width = 4;
		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
		break;
	case 2:
		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
						 ARRAY_SIZE(usdhc3_pads));
		gpio_direction_input(USDHC3_CD_GPIO);
		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
		usdhc_cfg[0].max_bus_width = 4;
		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
		break;
	}

	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}

#ifdef CONFIG_SYS_I2C_MXC
#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
	.sda = {
		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
		.gp = IMX_GPIO_NR(3, 13),
	},
	.scl = {
		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
		.gp = IMX_GPIO_NR(3, 12),
	},
};

int power_init_board(void)
{
	struct pmic *p;

	p = pfuze_common_init(I2C_PMIC);
	if (!p)
		return -ENODEV;

	return pfuze_mode_init(p, APS_PFM);
}
#endif

#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
	setup_iomux_fec();

	return cpu_eth_init(bis);
}

static int setup_fec(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);

	return enable_fec_anatop_clock(0, ENET_50MHZ);
}
#endif

#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET	0x800
#define UCTRL_PWR_POL		(1 << 9)

static iomux_v3_cfg_t const usb_otg_pads[] = {
	/* OTG1 */
	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
	/* OTG2 */
	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};

static void setup_usb(void)
{
	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
					 ARRAY_SIZE(usb_otg_pads));
}

int board_usb_phy_mode(int port)
{
	if (port == 1)
		return USB_INIT_HOST;
	else
		return usb_phy_mode(port);
}

int board_ehci_hcd_init(int port)
{
	u32 *usbnc_usb_ctrl;

	if (port > 1)
		return -EINVAL;

	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
				 port * 4);

	/* Set Power polarity */
	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);

	return 0;
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();
#ifdef CONFIG_MXC_SPI
	setup_spi();
#endif
	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_SYS_I2C_MXC
	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif

#ifdef	CONFIG_FEC_MXC
	setup_fec();
#endif

#ifdef CONFIG_USB_EHCI_MX6
	setup_usb();
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: MX6SLEVK\n");

	return 0;
}

#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#include <libfdt.h>

const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
	.dram_sdqs0 = 0x00003030,
	.dram_sdqs1 = 0x00003030,
	.dram_sdqs2 = 0x00003030,
	.dram_sdqs3 = 0x00003030,
	.dram_dqm0 = 0x00000030,
	.dram_dqm1 = 0x00000030,
	.dram_dqm2 = 0x00000030,
	.dram_dqm3 = 0x00000030,
	.dram_cas  = 0x00000030,
	.dram_ras  = 0x00000030,
	.dram_sdclk_0 = 0x00000028,
	.dram_reset = 0x00000030,
	.dram_sdba2 = 0x00000000,
	.dram_odt0 = 0x00000008,
	.dram_odt1 = 0x00000008,
};

const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_addds = 0x00000030,
	.grp_ctlds = 0x00000030,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_ddrmode = 0x00020000,
	.grp_ddr_type = 0x00080000,
};

const struct mx6_mmdc_calibration mx6_mmcd_calib = {
	.p0_mpdgctrl0 =  0x20000000,
	.p0_mpdgctrl1 =  0x00000000,
	.p0_mprddlctl =  0x4241444a,
	.p0_mpwrdlctl =  0x3030312b,
	.mpzqlp2ctl = 0x1b4700c7,
};

static struct mx6_lpddr2_cfg mem_ddr = {
	.mem_speed = 800,
	.density = 4,
	.width = 32,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.trcd_lp = 2000,
	.trppb_lp = 2000,
	.trpab_lp = 2250,
	.trasmin = 4200,
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0xFFFFFFFF, &ccm->CCGR0);
	writel(0xFFFFFFFF, &ccm->CCGR1);
	writel(0xFFFFFFFF, &ccm->CCGR2);
	writel(0xFFFFFFFF, &ccm->CCGR3);
	writel(0xFFFFFFFF, &ccm->CCGR4);
	writel(0xFFFFFFFF, &ccm->CCGR5);
	writel(0xFFFFFFFF, &ccm->CCGR6);

	writel(0x00260324, &ccm->cbcmr);
}

static void spl_dram_init(void)
{
	struct mx6_ddr_sysinfo sysinfo = {
		.dsize = mem_ddr.width / 32,
		.cs_density = 20,
		.ncs = 2,
		.cs1_mirror = 0,
		.walat = 0,
		.ralat = 2,
		.mif3_mode = 3,
		.bi_on = 1,
		.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
		.rtt_nom = 0,
		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
		.ddr_type = DDR_TYPE_LPDDR2,
		.refsel = 0,	/* Refresh cycles at 64KHz */
		.refr = 3,	/* 4 refresh commands per refresh cycle */
	};
	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}

void board_init_f(ulong dummy)
{
	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	ccgr_init();

	/* iomux and setup of i2c */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif
Commit	Line	Data
57ca432f FE	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
57ca432f FE	7	*/
	8
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/iomux.h>
e7d3b21b	11	#include <asm/arch/crm_regs.h>
57ca432f	12	#include <asm/arch/imx-regs.h>
e7d3b21b	13	#include <asm/arch/mx6-ddr.h>
57ca432f FE	14	#include <asm/arch/mx6-pins.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/gpio.h>
	17	#include <asm/imx-common/iomux-v3.h>
af38bf6b	18	#include <asm/imx-common/mxc_i2c.h>
3acb011c	19	#include <asm/imx-common/spi.h>
57ca432f	20	#include <asm/io.h>
1ace4022	21	#include <linux/sizes.h>
57ca432f FE	22	#include <common.h>
57ca432f FE	23	#include <fsl_esdhc.h>
af38bf6b	24	#include <i2c.h>
57ca432f	25	#include <mmc.h>
31f07964	26	#include <netdev.h>
af38bf6b PF	27	#include <power/pmic.h>
	28	#include <power/pfuze100_pmic.h>
	29	#include "../common/pfuze.h"
3b9c1a5d	30	#include <usb.h>
e162c6b1	31	#include <usb/ehci-ci.h>
57ca432f FE	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
7e2173cf BT	35	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	36	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	37	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
57ca432f	38
7e2173cf BT	39	#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP \| \
	40	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	41	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
57ca432f	42
31f07964 FE	43	#define ENET_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	44	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	45	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	46
694c3bc1 FE	47	#define SPI_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
	48	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	49
af38bf6b PF	50	#define I2C_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	51	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	52	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	53	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	54
16edd347 FE	55	#define OTGID_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	56	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \|\
	57	PAD_CTL_DSE_80ohm \| PAD_CTL_HYS \| \
	58	PAD_CTL_SRE_FAST)
	59
ae765f3a	60	#define ETH_PHY_POWER IMX_GPIO_NR(4, 21)
31f07964	61
57ca432f FE	62	int dram_init(void)
57ca432f FE	63	{
8259e9c9	64	gd->ram_size = imx_ddr_size();
57ca432f FE	65
	66	return 0;
	67	}
	68
	69	static iomux_v3_cfg_t const uart1_pads[] = {
	70	MX6_PAD_UART1_TXD__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	71	MX6_PAD_UART1_RXD__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	72	};
	73
36255d67 YL	74	static iomux_v3_cfg_t const usdhc1_pads[] = {
	75	/* 8 bit SD */
	76	MX6_PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	77	MX6_PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	78	MX6_PAD_SD1_DAT0__USDHC1_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	79	MX6_PAD_SD1_DAT1__USDHC1_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	80	MX6_PAD_SD1_DAT2__USDHC1_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	81	MX6_PAD_SD1_DAT3__USDHC1_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	82	MX6_PAD_SD1_DAT4__USDHC1_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	83	MX6_PAD_SD1_DAT5__USDHC1_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	84	MX6_PAD_SD1_DAT6__USDHC1_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	85	MX6_PAD_SD1_DAT7__USDHC1_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	86
	87	/CD pin/
	88	MX6_PAD_KEY_ROW7__GPIO_4_7 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	89	};
	90
57ca432f FE	91	static iomux_v3_cfg_t const usdhc2_pads[] = {
	92	MX6_PAD_SD2_CLK__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	93	MX6_PAD_SD2_CMD__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	94	MX6_PAD_SD2_DAT0__USDHC2_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	95	MX6_PAD_SD2_DAT1__USDHC2_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	96	MX6_PAD_SD2_DAT2__USDHC2_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	97	MX6_PAD_SD2_DAT3__USDHC2_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
36255d67 YL	98
	99	/CD pin/
	100	MX6_PAD_SD2_DAT7__GPIO_5_0 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	101	};
	102
	103	static iomux_v3_cfg_t const usdhc3_pads[] = {
	104	MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	105	MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	106	MX6_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	107	MX6_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	108	MX6_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	109	MX6_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	110
	111	/CD pin/
	112	MX6_PAD_REF_CLK_32K__GPIO_3_22 \| MUX_PAD_CTRL(NO_PAD_CTRL),
57ca432f FE	113	};
57ca432f FE	114
31f07964 FE	115	static iomux_v3_cfg_t const fec_pads[] = {
	116	MX6_PAD_FEC_MDC__FEC_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	117	MX6_PAD_FEC_MDIO__FEC_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	118	MX6_PAD_FEC_CRS_DV__FEC_RX_DV \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	119	MX6_PAD_FEC_RXD0__FEC_RX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	120	MX6_PAD_FEC_RXD1__FEC_RX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	121	MX6_PAD_FEC_TX_EN__FEC_TX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	122	MX6_PAD_FEC_TXD0__FEC_TX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	123	MX6_PAD_FEC_TXD1__FEC_TX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	124	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	125	MX6_PAD_FEC_RX_ER__GPIO_4_19 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	126	MX6_PAD_FEC_TX_CLK__GPIO_4_21 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	127	};
	128
694c3bc1 FE	129	#ifdef CONFIG_MXC_SPI
	130	static iomux_v3_cfg_t ecspi1_pads[] = {
	131	MX6_PAD_ECSPI1_MISO__ECSPI_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	132	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	133	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	134	MX6_PAD_ECSPI1_SS0__GPIO4_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	135	};
	136
155fa9af NK	137	int board_spi_cs_gpio(unsigned bus, unsigned cs)
	138	{
	139	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
	140	}
	141
694c3bc1 FE	142	static void setup_spi(void)
	143	{
	144	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
	145	}
	146	#endif
	147
57ca432f FE	148	static void setup_iomux_uart(void)
	149	{
	150	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	151	}
	152
31f07964 FE	153	static void setup_iomux_fec(void)
	154	{
	155	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
	156
ae765f3a FE	157	/* Power up LAN8720 PHY */
	158	gpio_direction_output(ETH_PHY_POWER , 1);
	159	udelay(15000);
31f07964 FE	160	}
31f07964 FE	161
36255d67 YL	162	#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
	163	#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
	164	#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
	165
	166	static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	167	{USDHC1_BASE_ADDR},
	168	{USDHC2_BASE_ADDR, 0, 4},
	169	{USDHC3_BASE_ADDR, 0, 4},
57ca432f FE	170	};
57ca432f FE	171
fb0d0428 PF	172	int board_mmc_get_env_dev(int devno)
	173	{
	174	return devno;
	175	}
	176
57ca432f FE	177	int board_mmc_getcd(struct mmc *mmc)
57ca432f FE	178	{
36255d67 YL	179	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	180	int ret = 0;
	181
	182	switch (cfg->esdhc_base) {
	183	case USDHC1_BASE_ADDR:
	184	ret = !gpio_get_value(USDHC1_CD_GPIO);
	185	break;
	186	case USDHC2_BASE_ADDR:
	187	ret = !gpio_get_value(USDHC2_CD_GPIO);
	188	break;
	189	case USDHC3_BASE_ADDR:
	190	ret = !gpio_get_value(USDHC3_CD_GPIO);
	191	break;
	192	}
	193
	194	return ret;
57ca432f FE	195	}
	196
	197	int board_mmc_init(bd_t *bis)
	198	{
e7d3b21b	199	#ifndef CONFIG_SPL_BUILD
36255d67 YL	200	int i, ret;
	201
	202	/*
	203	* According to the board_mmc_init() the following map is done:
a187559e	204	* (U-Boot device node) (Physical Port)
36255d67 YL	205	* mmc0 USDHC1
	206	* mmc1 USDHC2
	207	* mmc2 USDHC3
	208	*/
	209	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	210	switch (i) {
	211	case 0:
	212	imx_iomux_v3_setup_multiple_pads(
	213	usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
	214	gpio_direction_input(USDHC1_CD_GPIO);
	215	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	216	break;
	217	case 1:
	218	imx_iomux_v3_setup_multiple_pads(
	219	usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
	220	gpio_direction_input(USDHC2_CD_GPIO);
	221	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	222	break;
	223	case 2:
	224	imx_iomux_v3_setup_multiple_pads(
	225	usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	226	gpio_direction_input(USDHC3_CD_GPIO);
	227	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	228	break;
	229	default:
	230	printf("Warning: you configured more USDHC controllers"
	231	"(%d) than supported by the board\n", i + 1);
	232	return -EINVAL;
cb82c38e SB	233	}
	234
	235	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	236	if (ret) {
	237	printf("Warning: failed to initialize "
	238	"mmc dev %d\n", i);
	239	return ret;
	240	}
36255d67	241	}
57ca432f	242
36255d67	243	return 0;
e7d3b21b PF	244	#else
	245	struct src src_regs = (struct src )SRC_BASE_ADDR;
	246	u32 val;
	247	u32 port;
	248
	249	val = readl(&src_regs->sbmr1);
	250
	251	/* Boot from USDHC */
	252	port = (val >> 11) & 0x3;
	253	switch (port) {
	254	case 0:
	255	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
	256	ARRAY_SIZE(usdhc1_pads));
	257	gpio_direction_input(USDHC1_CD_GPIO);
	258	usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
	259	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	260	break;
	261	case 1:
	262	imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
	263	ARRAY_SIZE(usdhc2_pads));
	264	gpio_direction_input(USDHC2_CD_GPIO);
	265	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
	266	usdhc_cfg[0].max_bus_width = 4;
	267	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	268	break;
	269	case 2:
	270	imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
	271	ARRAY_SIZE(usdhc3_pads));
	272	gpio_direction_input(USDHC3_CD_GPIO);
	273	usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
	274	usdhc_cfg[0].max_bus_width = 4;
	275	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	276	break;
	277	}
	278
	279	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
	280	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	281	#endif
57ca432f FE	282	}
57ca432f FE	283
af38bf6b PF	284	#ifdef CONFIG_SYS_I2C_MXC
	285	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	286	/* I2C1 for PMIC */
	287	struct i2c_pads_info i2c_pad_info1 = {
	288	.sda = {
	289	.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA \| PC,
	290	.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 \| PC,
	291	.gp = IMX_GPIO_NR(3, 13),
	292	},
	293	.scl = {
	294	.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL \| PC,
	295	.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 \| PC,
	296	.gp = IMX_GPIO_NR(3, 12),
	297	},
	298	};
	299
	300	int power_init_board(void)
	301	{
	302	struct pmic *p;
	303
	304	p = pfuze_common_init(I2C_PMIC);
	305	if (!p)
	306	return -ENODEV;
	307
	308	return pfuze_mode_init(p, APS_PFM);
	309	}
	310	#endif
	311
31f07964 FE	312	#ifdef CONFIG_FEC_MXC
	313	int board_eth_init(bd_t *bis)
	314	{
31f07964 FE	315	setup_iomux_fec();
31f07964 FE	316
12c20c0c	317	return cpu_eth_init(bis);
31f07964 FE	318	}
	319
	320	static int setup_fec(void)
	321	{
0a11d6f2	322	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
31f07964 FE	323
	324	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
	325	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
	326
6d97dc10	327	return enable_fec_anatop_clock(0, ENET_50MHZ);
31f07964 FE	328	}
	329	#endif
	330
3b9c1a5d PF	331	#ifdef CONFIG_USB_EHCI_MX6
	332	#define USB_OTHERREGS_OFFSET 0x800
	333	#define UCTRL_PWR_POL (1 << 9)
	334
	335	static iomux_v3_cfg_t const usb_otg_pads[] = {
	336	/* OTG1 */
	337	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL),
16edd347	338	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID \| MUX_PAD_CTRL(OTGID_PAD_CTRL),
3b9c1a5d PF	339	/* OTG2 */
	340	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL)
	341	};
	342
	343	static void setup_usb(void)
	344	{
	345	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
	346	ARRAY_SIZE(usb_otg_pads));
	347	}
	348
	349	int board_usb_phy_mode(int port)
	350	{
	351	if (port == 1)
	352	return USB_INIT_HOST;
	353	else
	354	return usb_phy_mode(port);
	355	}
	356
	357	int board_ehci_hcd_init(int port)
	358	{
	359	u32 *usbnc_usb_ctrl;
	360
	361	if (port > 1)
	362	return -EINVAL;
	363
	364	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
	365	port * 4);
	366
	367	/* Set Power polarity */
	368	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
	369
	370	return 0;
	371	}
	372	#endif
31f07964	373
57ca432f FE	374	int board_early_init_f(void)
	375	{
	376	setup_iomux_uart();
694c3bc1 FE	377	#ifdef CONFIG_MXC_SPI
	378	setup_spi();
	379	#endif
57ca432f FE	380	return 0;
	381	}
	382
	383	int board_init(void)
	384	{
	385	/* address of boot parameters */
	386	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	387
af38bf6b PF	388	#ifdef CONFIG_SYS_I2C_MXC
	389	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	390	#endif
	391
31f07964 FE	392	#ifdef CONFIG_FEC_MXC
	393	setup_fec();
	394	#endif
3b9c1a5d PF	395
	396	#ifdef CONFIG_USB_EHCI_MX6
	397	setup_usb();
	398	#endif
	399
57ca432f FE	400	return 0;
	401	}
	402
57ca432f FE	403	int checkboard(void)
	404	{
	405	puts("Board: MX6SLEVK\n");
	406
	407	return 0;
	408	}
e7d3b21b PF	409
	410	#ifdef CONFIG_SPL_BUILD
	411	#include <spl.h>
	412	#include <libfdt.h>
	413
	414	const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
	415	.dram_sdqs0 = 0x00003030,
	416	.dram_sdqs1 = 0x00003030,
	417	.dram_sdqs2 = 0x00003030,
	418	.dram_sdqs3 = 0x00003030,
	419	.dram_dqm0 = 0x00000030,
	420	.dram_dqm1 = 0x00000030,
	421	.dram_dqm2 = 0x00000030,
	422	.dram_dqm3 = 0x00000030,
	423	.dram_cas = 0x00000030,
	424	.dram_ras = 0x00000030,
	425	.dram_sdclk_0 = 0x00000028,
	426	.dram_reset = 0x00000030,
	427	.dram_sdba2 = 0x00000000,
	428	.dram_odt0 = 0x00000008,
	429	.dram_odt1 = 0x00000008,
	430	};
	431
	432	const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
	433	.grp_b0ds = 0x00000030,
	434	.grp_b1ds = 0x00000030,
	435	.grp_b2ds = 0x00000030,
	436	.grp_b3ds = 0x00000030,
	437	.grp_addds = 0x00000030,
	438	.grp_ctlds = 0x00000030,
	439	.grp_ddrmode_ctl = 0x00020000,
	440	.grp_ddrpke = 0x00000000,
	441	.grp_ddrmode = 0x00020000,
	442	.grp_ddr_type = 0x00080000,
	443	};
	444
	445	const struct mx6_mmdc_calibration mx6_mmcd_calib = {
	446	.p0_mpdgctrl0 = 0x20000000,
	447	.p0_mpdgctrl1 = 0x00000000,
	448	.p0_mprddlctl = 0x4241444a,
	449	.p0_mpwrdlctl = 0x3030312b,
	450	.mpzqlp2ctl = 0x1b4700c7,
	451	};
	452
	453	static struct mx6_lpddr2_cfg mem_ddr = {
	454	.mem_speed = 800,
	455	.density = 4,
	456	.width = 32,
	457	.banks = 8,
	458	.rowaddr = 14,
	459	.coladdr = 10,
	460	.trcd_lp = 2000,
	461	.trppb_lp = 2000,
	462	.trpab_lp = 2250,
	463	.trasmin = 4200,
	464	};
	465
	466	static void ccgr_init(void)
	467	{
	468	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	469
	470	writel(0xFFFFFFFF, &ccm->CCGR0);
	471	writel(0xFFFFFFFF, &ccm->CCGR1);
	472	writel(0xFFFFFFFF, &ccm->CCGR2);
473	writel(0xFFFFFFFF, &ccm->CCGR3);
474	writel(0xFFFFFFFF, &ccm->CCGR4);
475	writel(0xFFFFFFFF, &ccm->CCGR5);
476	writel(0xFFFFFFFF, &ccm->CCGR6);
477
478	writel(0x00260324, &ccm->cbcmr);
479	}
480
481	static void spl_dram_init(void)
482	{
483	struct mx6_ddr_sysinfo sysinfo = {
484	.dsize = mem_ddr.width / 32,
485	.cs_density = 20,
486	.ncs = 2,
487	.cs1_mirror = 0,
488	.walat = 0,
489	.ralat = 2,
490	.mif3_mode = 3,
491	.bi_on = 1,
492	.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
493	.rtt_nom = 0,
494	.sde_to_rst = 0, /* LPDDR2 does not need this field */
495	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
496	.ddr_type = DDR_TYPE_LPDDR2,
edf00937 FE	497	.refsel = 0, /* Refresh cycles at 64KHz */
edf00937 FE	498	.refr = 3, /* 4 refresh commands per refresh cycle */
e7d3b21b PF	499	};
	500	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	501	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
	502	}
	503
	504	void board_init_f(ulong dummy)
	505	{
	506	/* setup AIPS and disable watchdog */
	507	arch_cpu_init();
	508
	509	ccgr_init();
	510
	511	/* iomux and setup of i2c */
	512	board_early_init_f();
	513
	514	/* setup GP timer */
	515	timer_init();
	516
	517	/* UART clocks enabled and gd valid - init serial console */
	518	preloader_console_init();
	519
	520	/* DDR initialization */
	521	spl_dram_init();
	522
	523	/* Clear the BSS. */
	524	memset(__bss_start, 0, __bss_end - __bss_start);
	525
	526	/* load/boot image from boot device */
	527	board_init_r(NULL, 0);
	528	}
e7d3b21b	529	#endif