[people/ms/u-boot.git] / board / freescale / p1010rdb / p1010rdb.c

/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
#include <pci.h>
#include <asm/fsl_serdes.h>
#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include <hwconfig.h>
#include <i2c.h>

DECLARE_GLOBAL_DATA_PTR;

#define GPIO4_PCIE_RESET_SET		0x08000000
#define MUX_CPLD_CAN_UART		0x00
#define MUX_CPLD_TDM			0x01
#define MUX_CPLD_SPICS0_FLASH		0x00
#define MUX_CPLD_SPICS0_SLIC		0x02
#define PMUXCR1_IFC_MASK       0x00ffff00
#define PMUXCR1_SDHC_MASK      0x00fff000
#define PMUXCR1_SDHC_ENABLE    0x00555000

enum {
	MUX_TYPE_IFC,
	MUX_TYPE_SDHC,
	MUX_TYPE_SPIFLASH,
	MUX_TYPE_TDM,
	MUX_TYPE_CAN,
	MUX_TYPE_CS0_NOR,
	MUX_TYPE_CS0_NAND,
};

enum {
	I2C_READ_BANK,
	I2C_READ_PCB_VER,
};

static uint sd_ifc_mux;

struct cpld_data {
	u8 cpld_ver; /* cpld revision */
#if defined(CONFIG_TARGET_P1010RDB_PA)
	u8 pcba_ver; /* pcb revision number */
	u8 twindie_ddr3;
	u8 res1[6];
	u8 bank_sel; /* NOR Flash bank */
	u8 res2[5];
	u8 usb2_sel;
	u8 res3[1];
	u8 porsw_sel;
	u8 tdm_can_sel;
	u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
	u8 por0; /* POR Options */
	u8 por1; /* POR Options */
	u8 por2; /* POR Options */
	u8 por3; /* POR Options */
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	u8 rom_loc;
#endif
};

int board_early_init_f(void)
{
	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
	/* Clock configuration to access CPLD using IFC(GPCM) */
	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
	/*
	* Reset PCIe slots via GPIO4
	*/
	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);

	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_16M, 1);

	set_tlb(1, flashbase + 0x1000000,
			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
	return 0;
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */

int config_board_mux(int ctrl_type)
{
	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u8 tmp;

#if defined(CONFIG_TARGET_P1010RDB_PA)
	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);

	switch (ctrl_type) {
	case MUX_TYPE_IFC:
		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
		tmp = 0xf0;
		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
		tmp = 0x01;
		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_IFC;
		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
		break;
	case MUX_TYPE_SDHC:
		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
		tmp = 0xf0;
		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
		tmp = 0x05;
		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_SDHC;
		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
				PMUXCR1_SDHC_ENABLE);
		break;
	case MUX_TYPE_SPIFLASH:
		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
		break;
	case MUX_TYPE_TDM:
		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
		break;
	case MUX_TYPE_CAN:
		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
		break;
	default:
		break;
	}
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	uint orig_bus = i2c_get_bus_num();
	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);

	switch (ctrl_type) {
	case MUX_TYPE_IFC:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_IFC;
		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
		break;
	case MUX_TYPE_SDHC:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		setbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_SDHC;
		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
				PMUXCR1_SDHC_ENABLE);
		break;
	case MUX_TYPE_SPIFLASH:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x80);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x80);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_TDM:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		setbits_8(&tmp, 0x82);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x82);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_CAN:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x02);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x02);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_CS0_NOR:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_CS0_NAND:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		setbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	default:
		break;
	}
	i2c_set_bus_num(orig_bus);
#endif
	return 0;
}

#ifdef CONFIG_TARGET_P1010RDB_PB
int i2c_pca9557_read(int type)
{
	u8 val;

	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);

	switch (type) {
	case I2C_READ_BANK:
		val = (val & 0x10) >> 4;
		break;
	case I2C_READ_PCB_VER:
		val = ((val & 0x60) >> 5) + 1;
		break;
	default:
		break;
	}

	return val;
}
#endif

int checkboard(void)
{
	struct cpu_type *cpu;
	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
	u8 val;

	cpu = gd->arch.cpu;
#if defined(CONFIG_TARGET_P1010RDB_PA)
	printf("Board: %sRDB-PA, ", cpu->name);
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	printf("Board: %sRDB-PB, ", cpu->name);
	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
	val = 0x0;  /* no polarity inversion */
	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
#endif

#ifdef CONFIG_SDCARD
	/* switch to IFC to read info from CPLD */
	config_board_mux(MUX_TYPE_IFC);
#endif

#if defined(CONFIG_TARGET_P1010RDB_PA)
	val = (in_8(&cpld_data->pcba_ver) & 0xf);
	printf("PCB: v%x.0\n", val);
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	val = in_8(&cpld_data->cpld_ver);
	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
	val = in_8(&cpld_data->rom_loc) & 0xf;
	puts("Boot from: ");
	switch (val) {
	case 0xf:
		config_board_mux(MUX_TYPE_CS0_NOR);
		printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
		break;
	case 0xe:
		puts("SDHC\n");
		val = 0x60; /* set pca9557 pin input/output */
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
		break;
	case 0x5:
		config_board_mux(MUX_TYPE_IFC);
		config_board_mux(MUX_TYPE_CS0_NAND);
		puts("NAND\n");
		break;
	case 0x6:
		config_board_mux(MUX_TYPE_IFC);
		puts("SPI\n");
		break;
	default:
		puts("unknown\n");
		break;
	}
#endif
	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	struct cpu_type *cpu;
	int num = 0;

	cpu = gd->arch.cpu;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif
#ifdef CONFIG_TSEC3
	/* P1014 and it's derivatives do not support eTSEC3 */
	if (cpu->soc_ver != SVR_P1014) {
		SET_STD_TSEC_INFO(tsec_info[num], 3);
		num++;
	}
#endif
	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;

	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);
#endif

	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"fsl,p1010-flexcan")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_spi_flash(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"spansion,s25sl12801")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_spi_slic(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"zarlink,le88266")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_tdm(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"fsl,starlite-tdm")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_sdhc(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
			"fsl,esdhc")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_ifc(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"fsl,ifc")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_disable_uart1(void *blob)
{
	int nodeoff;

	nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
					CONFIG_SYS_NS16550_COM2);

	if (nodeoff > 0) {
		fdt_status_disabled(blob, nodeoff);
	} else {
		printf("WARNING unable to set status for fsl,ns16550 "
			"uart1: %s\n", fdt_strerror(nodeoff));
	}
}

int ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;
	struct cpu_type *cpu;

	cpu = gd->arch.cpu;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

#if defined(CONFIG_PCI)
	FT_FSL_PCI_SETUP;
#endif

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#if defined(CONFIG_HAS_FSL_DR_USB)
	fsl_fdt_fixup_dr_usb(blob, bd);
#endif

       /* P1014 and it's derivatives don't support CAN and eTSEC3 */
	if (cpu->soc_ver == SVR_P1014) {
		fdt_del_flexcan(blob);
		fdt_del_node_and_alias(blob, "ethernet2");
	}

	/* Delete IFC node as IFC pins are multiplexing with SDHC */
	if (sd_ifc_mux != MUX_TYPE_IFC)
		fdt_del_ifc(blob);
	else
		fdt_del_sdhc(blob);

	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
		fdt_del_tdm(blob);
		fdt_del_spi_slic(blob);
	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
		fdt_del_flexcan(blob);
		fdt_del_spi_flash(blob);
		fdt_disable_uart1(blob);
	} else {
		/*
		 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
		 * explicitly, defaultly spi_cs_sel to spi-flash instead of
		 * to tdm/slic.
		 */
		fdt_del_tdm(blob);
		fdt_del_flexcan(blob);
		fdt_disable_uart1(blob);
	}

	return 0;
}
#endif

#ifdef CONFIG_SDCARD
int board_mmc_init(bd_t *bis)
{
	config_board_mux(MUX_TYPE_SDHC);
		return -1;
}
#else
void board_reset(void)
{
	/* mux to IFC to enable CPLD for reset */
	if (sd_ifc_mux != MUX_TYPE_IFC)
		config_board_mux(MUX_TYPE_IFC);
}
#endif


int misc_init_r(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
				MPC85xx_PMUXCR_CAN1_UART |
				MPC85xx_PMUXCR_CAN2_TDM |
				MPC85xx_PMUXCR_CAN2_UART);
		config_board_mux(MUX_TYPE_CAN);
	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
				MPC85xx_PMUXCR_CAN1_UART);
		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
				MPC85xx_PMUXCR_CAN1_TDM);
		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
		config_board_mux(MUX_TYPE_TDM);
	} else {
		/* defaultly spi_cs_sel to flash */
		config_board_mux(MUX_TYPE_SPIFLASH);
	}

	if (hwconfig("esdhc"))
		config_board_mux(MUX_TYPE_SDHC);
	else if (hwconfig("ifc"))
		config_board_mux(MUX_TYPE_IFC);

#ifdef CONFIG_TARGET_P1010RDB_PB
	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
#endif
	return 0;
}

static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
				char * const argv[])
{
	if (argc < 2)
		return CMD_RET_USAGE;
	if (strcmp(argv[1], "ifc") == 0)
		config_board_mux(MUX_TYPE_IFC);
	else if (strcmp(argv[1], "sdhc") == 0)
		config_board_mux(MUX_TYPE_SDHC);
	else
		return CMD_RET_USAGE;
	return 0;
}

U_BOOT_CMD(
	mux, 2, 0, pin_mux_cmd,
	"configure multiplexing pin for IFC/SDHC bus in runtime",
	"bus_type (e.g. mux sdhc)"
);
Commit	Line	Data
49249e13 PA	1	/*
	2	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
49249e13 PA	5	*/
	6
	7	#include <common.h>
	8	#include <asm/processor.h>
	9	#include <asm/mmu.h>
	10	#include <asm/cache.h>
	11	#include <asm/immap_85xx.h>
	12	#include <asm/io.h>
	13	#include <miiphy.h>
	14	#include <libfdt.h>
	15	#include <fdt_support.h>
	16	#include <fsl_mdio.h>
	17	#include <tsec.h>
	18	#include <mmc.h>
	19	#include <netdev.h>
	20	#include <pci.h>
	21	#include <asm/fsl_serdes.h>
0b66513b	22	#include <fsl_ifc.h>
49249e13	23	#include <asm/fsl_pci.h>
49249e13	24	#include <hwconfig.h>
ad89da0c	25	#include <i2c.h>
49249e13 PA	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
	29	#define GPIO4_PCIE_RESET_SET 0x08000000
	30	#define MUX_CPLD_CAN_UART 0x00
	31	#define MUX_CPLD_TDM 0x01
	32	#define MUX_CPLD_SPICS0_FLASH 0x00
	33	#define MUX_CPLD_SPICS0_SLIC 0x02
ad89da0c SL	34	#define PMUXCR1_IFC_MASK 0x00ffff00
	35	#define PMUXCR1_SDHC_MASK 0x00fff000
	36	#define PMUXCR1_SDHC_ENABLE 0x00555000
	37
	38	enum {
	39	MUX_TYPE_IFC,
	40	MUX_TYPE_SDHC,
e512c50b SL	41	MUX_TYPE_SPIFLASH,
	42	MUX_TYPE_TDM,
	43	MUX_TYPE_CAN,
	44	MUX_TYPE_CS0_NOR,
	45	MUX_TYPE_CS0_NAND,
	46	};
	47
	48	enum {
	49	I2C_READ_BANK,
	50	I2C_READ_PCB_VER,
ad89da0c SL	51	};
	52
	53	static uint sd_ifc_mux;
49249e13	54
49249e13 PA	55	struct cpld_data {
49249e13 PA	56	u8 cpld_ver; /* cpld revision */
7601686c	57	#if defined(CONFIG_TARGET_P1010RDB_PA)
49249e13 PA	58	u8 pcba_ver; /* pcb revision number */
	59	u8 twindie_ddr3;
	60	u8 res1[6];
	61	u8 bank_sel; /* NOR Flash bank */
	62	u8 res2[5];
	63	u8 usb2_sel;
	64	u8 res3[1];
	65	u8 porsw_sel;
	66	u8 tdm_can_sel;
	67	u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
	68	u8 por0; /* POR Options */
	69	u8 por1; /* POR Options */
	70	u8 por2; /* POR Options */
	71	u8 por3; /* POR Options */
7601686c	72	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b SL	73	u8 rom_loc;
e512c50b SL	74	#endif
49249e13	75	};
49249e13 PA	76
	77	int board_early_init_f(void)
	78	{
	79	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
39b0bbbb	80	struct fsl_ifc ifc = {(void )CONFIG_SYS_IFC_ADDR, (void )NULL};
49249e13	81	/* Clock configuration to access CPLD using IFC(GPCM) */
39b0bbbb	82	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
49249e13 PA	83	/*
	84	* Reset PCIe slots via GPIO4
	85	*/
	86	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
	87	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
	88
	89	return 0;
	90	}
	91
	92	int board_early_init_r(void)
	93	{
49249e13	94	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	95	int flash_esel = find_tlb_idx((void *)flashbase, 1);
49249e13 PA	96
	97	/*
	98	* Remap Boot flash region to caching-inhibited
	99	* so that flash can be erased properly.
	100	*/
	101
	102	/* Flush d-cache and invalidate i-cache of any FLASH data */
	103	flush_dcache();
	104	invalidate_icache();
	105
9d045682 YS	106	if (flash_esel == -1) {
	107	/* very unlikely unless something is messed up */
	108	puts("Error: Could not find TLB for FLASH BASE\n");
	109	flash_esel = 2; /* give our best effort to continue */
	110	} else {
	111	/* invalidate existing TLB entry for flash */
	112	disable_tlb(flash_esel);
	113	}
49249e13 PA	114
	115	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	116	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	117	0, flash_esel, BOOKE_PAGESZ_16M, 1);
	118
	119	set_tlb(1, flashbase + 0x1000000,
	120	CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
	121	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	122	0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
49249e13 PA	123	return 0;
	124	}
	125
	126	#ifdef CONFIG_PCI
	127	void pci_init_board(void)
	128	{
	129	fsl_pcie_init_board(0);
	130	}
	131	#endif /* ifdef CONFIG_PCI */
	132
ad89da0c SL	133	int config_board_mux(int ctrl_type)
	134	{
	135	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	136	u8 tmp;
	137
7601686c	138	#if defined(CONFIG_TARGET_P1010RDB_PA)
e512c50b SL	139	struct cpld_data cpld_data = (void )(CONFIG_SYS_CPLD_BASE);
e512c50b SL	140
ad89da0c SL	141	switch (ctrl_type) {
	142	case MUX_TYPE_IFC:
	143	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	144	tmp = 0xf0;
	145	i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
	146	tmp = 0x01;
	147	i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
	148	sd_ifc_mux = MUX_TYPE_IFC;
	149	clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
	150	break;
	151	case MUX_TYPE_SDHC:
	152	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	153	tmp = 0xf0;
	154	i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
	155	tmp = 0x05;
	156	i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
	157	sd_ifc_mux = MUX_TYPE_SDHC;
	158	clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
	159	PMUXCR1_SDHC_ENABLE);
	160	break;
e512c50b SL	161	case MUX_TYPE_SPIFLASH:
	162	out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
	163	break;
	164	case MUX_TYPE_TDM:
	165	out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
	166	out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
	167	break;
	168	case MUX_TYPE_CAN:
	169	out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
	170	break;
ad89da0c SL	171	default:
	172	break;
	173	}
7601686c	174	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b SL	175	uint orig_bus = i2c_get_bus_num();
e512c50b SL	176	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
ad89da0c	177
e512c50b SL	178	switch (ctrl_type) {
	179	case MUX_TYPE_IFC:
	180	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	181	clrbits_8(&tmp, 0x04);
	182	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	183	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	184	clrbits_8(&tmp, 0x04);
	185	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	186	sd_ifc_mux = MUX_TYPE_IFC;
	187	clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
	188	break;
	189	case MUX_TYPE_SDHC:
	190	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	191	setbits_8(&tmp, 0x04);
	192	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	193	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	194	clrbits_8(&tmp, 0x04);
	195	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	196	sd_ifc_mux = MUX_TYPE_SDHC;
	197	clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
	198	PMUXCR1_SDHC_ENABLE);
	199	break;
	200	case MUX_TYPE_SPIFLASH:
	201	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	202	clrbits_8(&tmp, 0x80);
	203	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	204	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	205	clrbits_8(&tmp, 0x80);
	206	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	207	break;
	208	case MUX_TYPE_TDM:
	209	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	210	setbits_8(&tmp, 0x82);
	211	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	212	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	213	clrbits_8(&tmp, 0x82);
	214	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	215	break;
	216	case MUX_TYPE_CAN:
	217	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	218	clrbits_8(&tmp, 0x02);
	219	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	220	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	221	clrbits_8(&tmp, 0x02);
	222	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	223	break;
	224	case MUX_TYPE_CS0_NOR:
	225	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	226	clrbits_8(&tmp, 0x08);
	227	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	228	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	229	clrbits_8(&tmp, 0x08);
	230	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	231	break;
	232	case MUX_TYPE_CS0_NAND:
	233	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	234	setbits_8(&tmp, 0x08);
	235	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	236	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	237	clrbits_8(&tmp, 0x08);
	238	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	239	break;
	240	default:
	241	break;
242	}
243	i2c_set_bus_num(orig_bus);
244	#endif
ad89da0c SL	245	return 0;
	246	}
	247
7601686c	248	#ifdef CONFIG_TARGET_P1010RDB_PB
e512c50b SL	249	int i2c_pca9557_read(int type)
	250	{
	251	u8 val;
	252
	253	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	254	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
	255
	256	switch (type) {
	257	case I2C_READ_BANK:
	258	val = (val & 0x10) >> 4;
	259	break;
	260	case I2C_READ_PCB_VER:
	261	val = ((val & 0x60) >> 5) + 1;
	262	break;
	263	default:
	264	break;
	265	}
	266
	267	return val;
	268	}
	269	#endif
	270
49249e13 PA	271	int checkboard(void)
	272	{
	273	struct cpu_type *cpu;
e512c50b SL	274	struct cpld_data cpld_data = (void )(CONFIG_SYS_CPLD_BASE);
e512c50b SL	275	u8 val;
49249e13	276
67ac13b1	277	cpu = gd->arch.cpu;
7601686c	278	#if defined(CONFIG_TARGET_P1010RDB_PA)
e512c50b	279	printf("Board: %sRDB-PA, ", cpu->name);
7601686c	280	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b SL	281	printf("Board: %sRDB-PB, ", cpu->name);
	282	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	283	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
	284	val = 0x0; /* no polarity inversion */
	285	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
	286	#endif
49249e13	287
ad89da0c SL	288	#ifdef CONFIG_SDCARD
	289	/* switch to IFC to read info from CPLD */
	290	config_board_mux(MUX_TYPE_IFC);
	291	#endif
	292
7601686c	293	#if defined(CONFIG_TARGET_P1010RDB_PA)
e512c50b SL	294	val = (in_8(&cpld_data->pcba_ver) & 0xf);
e512c50b SL	295	printf("PCB: v%x.0\n", val);
7601686c	296	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b SL	297	val = in_8(&cpld_data->cpld_ver);
	298	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
	299	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
	300	val = in_8(&cpld_data->rom_loc) & 0xf;
	301	puts("Boot from: ");
	302	switch (val) {
	303	case 0xf:
	304	config_board_mux(MUX_TYPE_CS0_NOR);
	305	printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
	306	break;
	307	case 0xe:
	308	puts("SDHC\n");
	309	val = 0x60; /* set pca9557 pin input/output */
	310	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
	311	break;
	312	case 0x5:
	313	config_board_mux(MUX_TYPE_IFC);
	314	config_board_mux(MUX_TYPE_CS0_NAND);
	315	puts("NAND\n");
	316	break;
	317	case 0x6:
	318	config_board_mux(MUX_TYPE_IFC);
	319	puts("SPI\n");
	320	break;
	321	default:
	322	puts("unknown\n");
	323	break;
	324	}
	325	#endif
49249e13 PA	326	return 0;
	327	}
	328
49249e13 PA	329	int board_eth_init(bd_t *bis)
49249e13 PA	330	{
c712df1d	331	#ifdef CONFIG_TSEC_ENET
49249e13 PA	332	struct fsl_pq_mdio_info mdio_info;
	333	struct tsec_info_struct tsec_info[4];
	334	struct cpu_type *cpu;
	335	int num = 0;
	336
67ac13b1	337	cpu = gd->arch.cpu;
49249e13 PA	338
	339	#ifdef CONFIG_TSEC1
	340	SET_STD_TSEC_INFO(tsec_info[num], 1);
	341	num++;
	342	#endif
	343	#ifdef CONFIG_TSEC2
	344	SET_STD_TSEC_INFO(tsec_info[num], 2);
	345	num++;
	346	#endif
	347	#ifdef CONFIG_TSEC3
	348	/* P1014 and it's derivatives do not support eTSEC3 */
48f6a5c3	349	if (cpu->soc_ver != SVR_P1014) {
49249e13 PA	350	SET_STD_TSEC_INFO(tsec_info[num], 3);
	351	num++;
	352	}
	353	#endif
	354	if (!num) {
	355	printf("No TSECs initialized\n");
	356	return 0;
	357	}
	358
	359	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	360	mdio_info.name = DEFAULT_MII_NAME;
	361
	362	fsl_pq_mdio_init(bis, &mdio_info);
	363
	364	tsec_eth_init(bis, tsec_info, num);
c712df1d	365	#endif
49249e13 PA	366
	367	return pci_eth_init(bis);
	368	}
49249e13 PA	369
	370	#if defined(CONFIG_OF_BOARD_SETUP)
	371	void fdt_del_flexcan(void *blob)
	372	{
	373	int nodeoff = 0;
	374
	375	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
f68a7305	376	"fsl,p1010-flexcan")) >= 0) {
49249e13 PA	377	fdt_del_node(blob, nodeoff);
	378	}
	379	}
	380
	381	void fdt_del_spi_flash(void *blob)
	382	{
	383	int nodeoff = 0;
	384
	385	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	386	"spansion,s25sl12801")) >= 0) {
	387	fdt_del_node(blob, nodeoff);
	388	}
	389	}
	390
	391	void fdt_del_spi_slic(void *blob)
	392	{
	393	int nodeoff = 0;
	394
	395	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	396	"zarlink,le88266")) >= 0) {
	397	fdt_del_node(blob, nodeoff);
	398	}
	399	}
	400
	401	void fdt_del_tdm(void *blob)
	402	{
	403	int nodeoff = 0;
	404
	405	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	406	"fsl,starlite-tdm")) >= 0) {
	407	fdt_del_node(blob, nodeoff);
	408	}
	409	}
	410
487e8abb SL	411	void fdt_del_sdhc(void *blob)
	412	{
	413	int nodeoff = 0;
	414
	415	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	416	"fsl,esdhc")) >= 0) {
	417	fdt_del_node(blob, nodeoff);
	418	}
	419	}
	420
ad89da0c SL	421	void fdt_del_ifc(void *blob)
	422	{
	423	int nodeoff = 0;
	424
	425	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	426	"fsl,ifc")) >= 0) {
	427	fdt_del_node(blob, nodeoff);
	428	}
	429	}
	430
487e8abb SL	431	void fdt_disable_uart1(void *blob)
	432	{
	433	int nodeoff;
	434
	435	nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
	436	CONFIG_SYS_NS16550_COM2);
	437
	438	if (nodeoff > 0) {
	439	fdt_status_disabled(blob, nodeoff);
	440	} else {
	441	printf("WARNING unable to set status for fsl,ns16550 "
	442	"uart1: %s\n", fdt_strerror(nodeoff));
	443	}
	444	}
	445
e895a4b0	446	int ft_board_setup(void blob, bd_t bd)
49249e13 PA	447	{
	448	phys_addr_t base;
	449	phys_size_t size;
	450	struct cpu_type *cpu;
	451
67ac13b1	452	cpu = gd->arch.cpu;
49249e13 PA	453
	454	ft_cpu_setup(blob, bd);
	455
	456	base = getenv_bootm_low();
	457	size = getenv_bootm_size();
	458
	459	#if defined(CONFIG_PCI)
	460	FT_FSL_PCI_SETUP;
	461	#endif
	462
	463	fdt_fixup_memory(blob, (u64)base, (u64)size);
	464
a311db69	465	#if defined(CONFIG_HAS_FSL_DR_USB)
a5c289b9	466	fsl_fdt_fixup_dr_usb(blob, bd);
a311db69	467	#endif
49249e13 PA	468
49249e13 PA	469	/* P1014 and it's derivatives don't support CAN and eTSEC3 */
48f6a5c3	470	if (cpu->soc_ver == SVR_P1014) {
49249e13 PA	471	fdt_del_flexcan(blob);
	472	fdt_del_node_and_alias(blob, "ethernet2");
	473	}
ad89da0c SL	474
	475	/* Delete IFC node as IFC pins are multiplexing with SDHC */
	476	if (sd_ifc_mux != MUX_TYPE_IFC)
	477	fdt_del_ifc(blob);
	478	else
	479	fdt_del_sdhc(blob);
	480
49249e13	481	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
49249e13 PA	482	fdt_del_tdm(blob);
49249e13 PA	483	fdt_del_spi_slic(blob);
487e8abb	484	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
49249e13 PA	485	fdt_del_flexcan(blob);
49249e13 PA	486	fdt_del_spi_flash(blob);
487e8abb SL	487	fdt_disable_uart1(blob);
	488	} else {
	489	/*
	490	* If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
	491	* explicitly, defaultly spi_cs_sel to spi-flash instead of
	492	* to tdm/slic.
	493	*/
	494	fdt_del_tdm(blob);
	495	fdt_del_flexcan(blob);
	496	fdt_disable_uart1(blob);
49249e13	497	}
e895a4b0 SG	498
e895a4b0 SG	499	return 0;
ad89da0c	500	}
49249e13	501	#endif
ad89da0c SL	502
	503	#ifdef CONFIG_SDCARD
	504	int board_mmc_init(bd_t *bis)
	505	{
	506	config_board_mux(MUX_TYPE_SDHC);
	507	return -1;
	508	}
	509	#else
	510	void board_reset(void)
	511	{
	512	/* mux to IFC to enable CPLD for reset */
	513	if (sd_ifc_mux != MUX_TYPE_IFC)
	514	config_board_mux(MUX_TYPE_IFC);
49249e13 PA	515	}
	516	#endif
	517
ad89da0c	518
49249e13 PA	519	int misc_init_r(void)
49249e13 PA	520	{
49249e13 PA	521	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	522
	523	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
	524	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM \|
	525	MPC85xx_PMUXCR_CAN1_UART \|
	526	MPC85xx_PMUXCR_CAN2_TDM \|
	527	MPC85xx_PMUXCR_CAN2_UART);
e512c50b	528	config_board_mux(MUX_TYPE_CAN);
487e8abb	529	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
49249e13 PA	530	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART \|
	531	MPC85xx_PMUXCR_CAN1_UART);
	532	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM \|
	533	MPC85xx_PMUXCR_CAN1_TDM);
	534	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
	535	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
e512c50b	536	config_board_mux(MUX_TYPE_TDM);
487e8abb SL	537	} else {
487e8abb SL	538	/* defaultly spi_cs_sel to flash */
e512c50b	539	config_board_mux(MUX_TYPE_SPIFLASH);
487e8abb SL	540	}
487e8abb SL	541
ad89da0c SL	542	if (hwconfig("esdhc"))
	543	config_board_mux(MUX_TYPE_SDHC);
	544	else if (hwconfig("ifc"))
	545	config_board_mux(MUX_TYPE_IFC);
	546
7601686c	547	#ifdef CONFIG_TARGET_P1010RDB_PB
e512c50b SL	548	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
e512c50b SL	549	#endif
49249e13 PA	550	return 0;
49249e13 PA	551	}
ad89da0c SL	552
	553	static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
	554	char * const argv[])
	555	{
	556	if (argc < 2)
	557	return CMD_RET_USAGE;
	558	if (strcmp(argv[1], "ifc") == 0)
	559	config_board_mux(MUX_TYPE_IFC);
	560	else if (strcmp(argv[1], "sdhc") == 0)
	561	config_board_mux(MUX_TYPE_SDHC);
	562	else
	563	return CMD_RET_USAGE;
	564	return 0;
	565	}
	566
	567	U_BOOT_CMD(
	568	mux, 2, 0, pin_mux_cmd,
	569	"configure multiplexing pin for IFC/SDHC bus in runtime",
	570	"bus_type (e.g. mux sdhc)"
	571	);